| 08f3c2bc | 19-Aug-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(fvp): fdts: merge motherboard .dtsi files
For no real reason we were shipping two separate DT include files for the
base FVP motherboard peripherals, one for aarch32, one for aarch64.
There
refactor(fvp): fdts: merge motherboard .dtsi files
For no real reason we were shipping two separate DT include files for the
base FVP motherboard peripherals, one for aarch32, one for aarch64.
There is no difference in the hardware description when using a
different instruction set, and the diff between the two files was about
a missing interrupt map for the 64-bit DT files.
Consolidate the situation by just using a single motherboard .dtsi file,
which relies on an interrupt map by the including files.
Provide that map in the two files where it was missing before, and
change the filenames to let all users include the same file now.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I19b77ecc8da9b4bfbd61d02f910b9ab05dbf92e9
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| a25349b7 | 25-Aug-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
The DT files for the Cortex-A5 and Cortex-A7 FVP models include the
shared rtsm_ve-motherboard.dtsi file, which we need to sync with the
up
refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
The DT files for the Cortex-A5 and Cortex-A7 FVP models include the
shared rtsm_ve-motherboard.dtsi file, which we need to sync with the
upstream Linux version soon.
To prepare for its changed structure there, adjust the top-level
#address-cells and #size-cells properties to be compatible with the
expectations of the Linux version.
Also extend the interrupt map to cover all peripherals listed in the
motherboard file, and use the proper GIC macros to make them more
readable on the way.
Change-Id: I7d1493f1a200e8350530f912833f9ffcc5f94b21
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 6b2721c0 | 10-Dec-2021 |
Andre Przywara <andre.przywara@arm.com> |
fix(fvp): fdts: unify and fix PSCI nodes
The PSCI DT nodes used for the various fvp-base model variants provide
explicit function IDs, as required for the pre-v0.2 PSCI specification.
This prevents
fix(fvp): fdts: unify and fix PSCI nodes
The PSCI DT nodes used for the various fvp-base model variants provide
explicit function IDs, as required for the pre-v0.2 PSCI specification.
This prevents them from being used from both AArch32 and AArch64 DT
clients, and using this version of the PSCI spec is long deprecated
anyway.
Remove the old compatible string and the function properties, to
force clients to use the standard function IDs as described in the PSCI
spec. sys_poweroff and sys_reset were never standardised or used anyway.
There should be no client software around that cannot deal with PSCI
v0.2.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie87deb9898eae79b7307c15bcefcd4b311d4dc22
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| 93ed4f08 | 03-Oct-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp13-fdts): correct PLL nodes name
Align aliases and node names for PLL nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I863995eb884fc61c10d512bed0fd404b75ead353 |
| b139f1cf | 15-Aug-2022 |
Mikael Olsson <mikael.olsson@arm.com> |
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
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| 066450ab | 28-Sep-2022 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(tc): resolve the static-checks errors
Converted the space indentation to tabs to fix the
errors listed under tf-static-checks CI job.
Change-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068
Signed
fix(tc): resolve the static-checks errors
Converted the space indentation to tabs to fix the
errors listed under tf-static-checks CI job.
Change-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 0f2ab75f | 27-Sep-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(tc): add RTC PL031 device tree node" into integration |
| a816de56 | 12-Sep-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
feat(tc): add RTC PL031 device tree node
It enables RTC PL031 driver in kernel.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: I6d7c1a5b6ce11b3d594f7575a747e72826c8d9b8 |
| 9dedc1ab | 14-Sep-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "morello-dt-fix" into integration
* changes:
fix(morello): dts: remove #a-c and #s-c from memory node
fix(morello): dts: fix GICv3 compatible string
fix(morello): dts:
Merge changes from topic "morello-dt-fix" into integration
* changes:
fix(morello): dts: remove #a-c and #s-c from memory node
fix(morello): dts: fix GICv3 compatible string
fix(morello): dts: fix DT node naming
fix(morello): dts: fix SCMI shmem/mboxes grouping
fix(morello): dts: use documented DPU compatible string
fix(morello): dts: fix DP SMMU IRQ ordering
fix(morello): dts: fix SMMU IRQ ordering
fix(morello): dts: add model names
fix(morello): dts: fix stdout-path target
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| 8a858913 | 07-Sep-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "stm32mp15-dt-updates" into integration
* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refa
Merge changes from topic "stm32mp15-dt-updates" into integration
* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refactor(stm32mp15-fdts): remove RCC secure-status
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| 2974d2f2 | 18-Jun-2022 |
sahil <sahil@arm.com> |
fix(n1sdp): add numa node id for pcie controllers
If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-
fix(n1sdp): add numa node id for pcie controllers
If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-id=0 and
pcie_secondary_ctlr is assigned numa-node-id=1.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I533abdd6ea162df7b15ee04cbfc48ba7a544b91a
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| e6ffafbe | 20-Jun-2022 |
SAHIL <sahil@arm.com> |
fix(n1sdp): replace non-inclusive terms from dts file
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I6aa3b6dcf7c2fea18ea2d4f44a2293123ff34bdf |
| 5dbda5cb | 17-Aug-2022 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp15-fdts): remove timers15 node
The node is currently not used in TF-A. Remove it.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f06
refactor(stm32mp15-fdts): remove timers15 node
The node is currently not used in TF-A. Remove it.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f0689f
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| f0c19f25 | 30-Mar-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(stm32mp15-fdts): remove unused secure-status properties
For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED)
refactor(stm32mp15-fdts): remove unused secure-status properties
For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137
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| 0791aaf4 | 29-Mar-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(stm32mp15-fdts): remove RCC secure-status
The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.
refactor(stm32mp15-fdts): remove RCC secure-status
The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.
[1] 812daf916c ("feat(st): update the security based on new compatible")
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6
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| 51e22305 | 13-Jul-2022 |
Johann Neuhauser <jneuhauser@dh-electronics.com> |
feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM
This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition an
feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM
This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition and the
Avenger96 baseboard like it's done in Linux and U-Boot.
Differences to stm32mp157a-avenger96.dts:
- Enable sdmmc2 for booting from eMMC
- improved clock settings like in U-Boot commit b6055945
"ARM: dts: stm32: Adjust PLL4 settings on AV96 again"
- improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74
"ARM: dts: stm32: Synchronize DDR setttings on DH SoMs"
TF-A with this new dts(i) files on this board was fully tested with
the latest OP-TEE developer setup.
Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
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| 936f29f6 | 30-Jun-2022 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config
Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.
Signed-off-by: Yann Gautier <yann.gautier@st.c
feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config
Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib31bed1ffe89ff221fab1884a2db729ce1e21846
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| 4c07deb5 | 02-May-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp13-fdts): cleanup DT files
Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals th
fix(stm32mp13-fdts): cleanup DT files
Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals that are not used in TF-A on STM32MP13.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I0c408d29b55cb94644c92539460fc62485781223
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| c9a4cb55 | 02-May-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp13-fdts): update SDMMC max frequency
On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.
fix(stm32mp13-fdts): update SDMMC max frequency
On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If4b364f53f87d4b5d276a976af486a3bf083f49b
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| c7ac7d65 | 02-May-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp13-fdts): align sdmmc pins with kernel
Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordi
fix(stm32mp13-fdts): align sdmmc pins with kernel
Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordingly.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e1f3cf78794bfb7bbe53cfc7e88623c7e79855d
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| 33223c3a | 29-Mar-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(stm32mp15-fdts): remove ETZPC status
The ETZPC is always secure, and the driver does no more rely on
secure-status (and status) DT property. Remove them from the SoC
DT file.
Signed-off-by
refactor(stm32mp15-fdts): remove ETZPC status
The ETZPC is always secure, and the driver does no more rely on
secure-status (and status) DT property. Remove them from the SoC
DT file.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5f1d3534679553d79e6866396cd70e21a595ef6a
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| f33e113c | 19-Jul-2022 |
Andre Przywara <andre.przywara@arm.com> |
fix(morello): dts: remove #a-c and #s-c from memory node
The #address-cells and #size-cells properties affect the size of reg
properties in *child* nodes only, they have no effect on the current
nod
fix(morello): dts: remove #a-c and #s-c from memory node
The #address-cells and #size-cells properties affect the size of reg
properties in *child* nodes only, they have no effect on the current
node.
The /memory node has no children, hence there is no need to specify
those properties. dt-validate complains about this:
==========
morello-soc.dtb: /: memory@80000000: '#address-cells', '#size-cells' do
not match any of the regexes: 'pinctrl-[0-9]+'
From schema: dt-schema.git/dtschema/schemas/memory.yaml
==========
Remove the unneeded properties.
Change-Id: I35058a00fa9bfa1007f31a4c21898dd45c586aa8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 982f2585 | 24-Mar-2022 |
Andre Przywara <andre.przywara@arm.com> |
fix(morello): dts: fix GICv3 compatible string
The official GICv3 DT bindings require only a limited number of
compatible string, and disavowes the naming of an implementation.
Linux' "make dtbs_che
fix(morello): dts: fix GICv3 compatible string
The official GICv3 DT bindings require only a limited number of
compatible string, and disavowes the naming of an implementation.
Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: interrupt-controller@2c010000: compatible: 'oneOf' conditional failed, one must be fixed:
['arm,gic-600', 'arm,gic-v3'] is too long
'arm,gic-600' is not one of ['qcom,msm8996-gic-v3']
'arm,gic-v3' was expected
From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
============
Drop the redundant (because runtime detectable) and undocumented
implementation version, and just use the standard compatible string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I05b207df271d6aa5bf3f2163f99ac0c594204c75
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| 41c310b4 | 24-Mar-2022 |
Andre Przywara <andre.przywara@arm.com> |
fix(morello): dts: fix DT node naming
The various official DT bindings only allow certain node name patterns.
Linux' "make dtbs_check" reports:
===========
.../morello-soc.dt.yaml: sram@45200000: 's
fix(morello): dts: fix DT node naming
The various official DT bindings only allow certain node name patterns.
Linux' "make dtbs_check" reports:
===========
.../morello-soc.dt.yaml: sram@45200000: 'scp-shmem@0', 'scp-shmem@80' do not match any of the regexes: '^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/sram/sram.yaml
.../morello-soc.dt.yaml: uart@2a400000: $nodename:0: 'uart@2a400000' does not match '^serial(@.*)?$'
From schema: Documentation/devicetree/bindings/serial/pl011.yaml
.../morello-soc.dt.yaml: interrupt-controller@2c010000: 'its@30040000', 'its@30060000', 'its@30080000', 'its@300a0000' do not match any of the regexes: '^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$', '^gic-its@', '^interrupt-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
===========
Rename the node names to improve bindings compliance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ieff576512853eb2bf932c7a2b338c91e0c116b87
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| 8aeb1fcf | 24-Mar-2022 |
Andre Przywara <andre.przywara@arm.com> |
fix(morello): dts: fix SCMI shmem/mboxes grouping
The official Arm MHU DT binding suggests to group the shmem (and mboxes)
values to signify the number of mailboxes supported.
Linux' "make dtbs_chec
fix(morello): dts: fix SCMI shmem/mboxes grouping
The official Arm MHU DT binding suggests to group the shmem (and mboxes)
values to signify the number of mailboxes supported.
Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: scmi: shmem:0: [17, 18] is too long
From schema: dt-schema.git/dtschema/schemas/mbox/mbox-consumer.yaml
============
Add angle brackets at the right location to mark the boundaries between
the two mailbox instances used.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: If585c98b5e8e55cd5c0b1261e03ce4b91a4c0413
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