1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause 2/* 3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> 4 * Copyright (C) 2022 DH electronics GmbH 5 */ 6 7#include "stm32mp15-pinctrl.dtsi" 8#include "stm32mp15xxaa-pinctrl.dtsi" 9#include <dt-bindings/clock/stm32mp1-clksrc.h> 10#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" 11 12/ { 13 memory@c0000000 { 14 device_type = "memory"; 15 reg = <0xC0000000 0x40000000>; 16 }; 17}; 18 19&bsec { 20 board_id: board_id@ec { 21 reg = <0xec 0x4>; 22 st,non-secure-otp; 23 }; 24}; 25 26&cpu0 { 27 cpu-supply = <&vddcore>; 28}; 29 30&cpu1 { 31 cpu-supply = <&vddcore>; 32}; 33 34&hash1 { 35 status = "okay"; 36}; 37 38&i2c4 { 39 pinctrl-names = "default"; 40 pinctrl-0 = <&i2c4_pins_a>; 41 i2c-scl-rising-time-ns = <185>; 42 i2c-scl-falling-time-ns = <20>; 43 status = "okay"; 44 45 pmic: stpmic@33 { 46 compatible = "st,stpmic1"; 47 reg = <0x33>; 48 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; 49 interrupt-controller; 50 #interrupt-cells = <2>; 51 status = "okay"; 52 53 regulators { 54 compatible = "st,stpmic1-regulators"; 55 ldo1-supply = <&v3v3>; 56 ldo2-supply = <&v3v3>; 57 ldo3-supply = <&vdd_ddr>; 58 ldo5-supply = <&v3v3>; 59 ldo6-supply = <&v3v3>; 60 pwr_sw1-supply = <&bst_out>; 61 pwr_sw2-supply = <&bst_out>; 62 63 vddcore: buck1 { 64 regulator-name = "vddcore"; 65 regulator-min-microvolt = <1200000>; 66 regulator-max-microvolt = <1350000>; 67 regulator-always-on; 68 regulator-initial-mode = <0>; 69 regulator-over-current-protection; 70 }; 71 72 vdd_ddr: buck2 { 73 regulator-name = "vdd_ddr"; 74 regulator-min-microvolt = <1350000>; 75 regulator-max-microvolt = <1350000>; 76 regulator-always-on; 77 regulator-initial-mode = <0>; 78 regulator-over-current-protection; 79 }; 80 81 vdd: buck3 { 82 regulator-name = "vdd"; 83 regulator-min-microvolt = <3300000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-always-on; 86 st,mask-reset; 87 regulator-initial-mode = <0>; 88 regulator-over-current-protection; 89 }; 90 91 v3v3: buck4 { 92 regulator-name = "v3v3"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 regulator-always-on; 96 regulator-over-current-protection; 97 regulator-initial-mode = <0>; 98 }; 99 100 vdda: ldo1 { 101 regulator-name = "vdda"; 102 regulator-min-microvolt = <2900000>; 103 regulator-max-microvolt = <2900000>; 104 regulator-always-on; 105 }; 106 107 v2v8: ldo2 { 108 regulator-name = "v2v8"; 109 regulator-min-microvolt = <2800000>; 110 regulator-max-microvolt = <2800000>; 111 }; 112 113 vtt_ddr: ldo3 { 114 regulator-name = "vtt_ddr"; 115 regulator-always-on; 116 regulator-over-current-protection; 117 st,regulator-sink-source; 118 }; 119 120 vdd_usb: ldo4 { 121 regulator-name = "vdd_usb"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 }; 125 126 vdd_sd: ldo5 { 127 regulator-name = "vdd_sd"; 128 regulator-min-microvolt = <2900000>; 129 regulator-max-microvolt = <2900000>; 130 regulator-boot-on; 131 }; 132 133 v1v8: ldo6 { 134 regulator-name = "v1v8"; 135 regulator-min-microvolt = <1800000>; 136 regulator-max-microvolt = <1800000>; 137 }; 138 139 vref_ddr: vref_ddr { 140 regulator-name = "vref_ddr"; 141 regulator-always-on; 142 }; 143 144 bst_out: boost { 145 regulator-name = "bst_out"; 146 }; 147 148 vbus_otg: pwr_sw1 { 149 regulator-name = "vbus_otg"; 150 }; 151 152 vbus_sw: pwr_sw2 { 153 regulator-name = "vbus_sw"; 154 regulator-active-discharge = <1>; 155 }; 156 }; 157 }; 158}; 159 160&iwdg2 { 161 timeout-sec = <32>; 162 status = "okay"; 163 secure-status = "okay"; 164}; 165 166&pwr_regulators { 167 vdd-supply = <&vdd>; 168 vdd_3v3_usbfs-supply = <&vdd_usb>; 169}; 170 171&qspi { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; 174 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 status = "okay"; 178 179 flash0: flash@0 { 180 compatible = "jedec,spi-nor"; 181 reg = <0>; 182 spi-rx-bus-width = <4>; 183 spi-max-frequency = <108000000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 }; 187}; 188 189&rcc { 190 st,clksrc = < 191 CLK_MPU_PLL1P 192 CLK_AXI_PLL2P 193 CLK_MCU_PLL3P 194 CLK_PLL12_HSE 195 CLK_PLL3_HSE 196 CLK_PLL4_HSE 197 CLK_RTC_LSE 198 CLK_MCO1_DISABLED 199 CLK_MCO2_PLL4P 200 >; 201 202 st,clkdiv = < 203 1 /*MPU*/ 204 0 /*AXI*/ 205 0 /*MCU*/ 206 1 /*APB1*/ 207 1 /*APB2*/ 208 1 /*APB3*/ 209 1 /*APB4*/ 210 2 /*APB5*/ 211 23 /*RTC*/ 212 0 /*MCO1*/ 213 1 /*MCO2*/ 214 >; 215 216 st,pkcs = < 217 CLK_CKPER_HSE 218 CLK_FMC_ACLK 219 CLK_QSPI_ACLK 220 CLK_ETH_PLL4P 221 CLK_SDMMC12_PLL4P 222 CLK_DSI_DSIPLL 223 CLK_STGEN_HSE 224 CLK_USBPHY_HSE 225 CLK_SPI2S1_PLL3Q 226 CLK_SPI2S23_PLL3Q 227 CLK_SPI45_HSI 228 CLK_SPI6_HSI 229 CLK_I2C46_HSI 230 CLK_SDMMC3_PLL4P 231 CLK_USBO_USBPHY 232 CLK_ADC_CKPER 233 CLK_CEC_LSE 234 CLK_I2C12_HSI 235 CLK_I2C35_HSI 236 CLK_UART1_HSI 237 CLK_UART24_HSI 238 CLK_UART35_HSI 239 CLK_UART6_HSI 240 CLK_UART78_HSI 241 CLK_SPDIF_PLL4P 242 CLK_FDCAN_PLL4R 243 CLK_SAI1_PLL3Q 244 CLK_SAI2_PLL3Q 245 CLK_SAI3_PLL3Q 246 CLK_SAI4_PLL3Q 247 CLK_RNG1_LSI 248 CLK_RNG2_LSI 249 CLK_LPTIM1_PCLK1 250 CLK_LPTIM23_PCLK3 251 CLK_LPTIM45_LSE 252 >; 253 254 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 255 pll1: st,pll@0 { 256 compatible = "st,stm32mp1-pll"; 257 reg = <0>; 258 cfg = <2 80 0 0 0 PQR(1,0,0)>; 259 frac = <0x800>; 260 }; 261 262 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 263 pll2: st,pll@1 { 264 compatible = "st,stm32mp1-pll"; 265 reg = <1>; 266 cfg = <2 65 1 0 0 PQR(1,1,1)>; 267 frac = <0x1400>; 268 }; 269 270 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 271 pll3: st,pll@2 { 272 compatible = "st,stm32mp1-pll"; 273 reg = <2>; 274 cfg = <1 33 1 16 36 PQR(1,1,1)>; 275 frac = <0x1a04>; 276 }; 277 278 /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ 279 pll4: st,pll@3 { 280 compatible = "st,stm32mp1-pll"; 281 reg = <3>; 282 cfg = <1 49 5 11 11 PQR(1,1,1)>; 283 }; 284}; 285 286&rng1 { 287 status = "okay"; 288}; 289 290&rtc { 291 status = "okay"; 292}; 293 294&sdmmc1 { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 297 disable-wp; 298 st,sig-dir; 299 st,neg-edge; 300 bus-width = <4>; 301 vmmc-supply = <&vdd_sd>; 302 status = "okay"; 303}; 304 305&sdmmc1_b4_pins_a { 306 /* 307 * SD bus pull-up resistors: 308 * - optional on SoMs with SD voltage translator 309 * - mandatory on SoMs without SD voltage translator 310 */ 311 pins1 { 312 bias-pull-up; 313 }; 314 pins2 { 315 bias-pull-up; 316 }; 317}; 318 319&sdmmc2 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 322 non-removable; 323 no-sd; 324 no-sdio; 325 st,neg-edge; 326 bus-width = <8>; 327 vmmc-supply = <&v3v3>; 328 vqmmc-supply = <&v3v3>; 329 mmc-ddr-3_3v; 330 status = "okay"; 331}; 332 333&uart4 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&uart4_pins_a>; 336 status = "okay"; 337}; 338