fix(drivers/nxp/sfp): fix compile warning

Fix compile warning that ‘mask’ may be used uninitialized.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I75a443dbc36d7bd174fe317616fd95cd09630

fix(drivers/nxp/sfp): fix compile warning

Fix compile warning that ‘mask’ may be used uninitialized.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I75a443dbc36d7bd174fe317616fd95cd096306fc

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fix(stpmic1): fix power switches activation

Add enable bit mask description because power switches
are not all enabled by bit 0.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: If7c9ae7

fix(stpmic1): fix power switches activation

Add enable bit mask description because power switches
are not all enabled by bit 0.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: If7c9ae7d800adee8e25416ca35db1be20452741f

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fix(stpmic1): update error cases return

Use errno values, or the return of called functions, instead of -1.
Correct some MISRA issues, like braces.

Change-Id: If7b53de5cbfb4d2c9979bce0e594dd92bf07a

fix(stpmic1): update error cases return

Use errno values, or the return of called functions, instead of -1.
Correct some MISRA issues, like braces.

Change-Id: If7b53de5cbfb4d2c9979bce0e594dd92bf07a77a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp1_clk): keep RTC clock always on

On battery powered systems the RTC keeps the date/time across
system reboot.
The RTC clock should not be disabled otherwise the date/time
counter gets sto

fix(stm32mp1_clk): keep RTC clock always on

On battery powered systems the RTC keeps the date/time across
system reboot.
The RTC clock should not be disabled otherwise the date/time
counter gets stopped.

Tag RTC clock as always on.

Signed-off-by: HE Shushan <shushan.he@st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I6455c3c740d2e5add28255eb84f8ebaf2870d9d8

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refactor(stm32_sdmmc2): use DT helpers

Use dt_match_instance_by_compatible() and dt_fill_device_info()
functions to simplify SDMMC driver code.

Change-Id: Id16aa849ac79a9d3c2dc72c947fe189743856292

refactor(stm32_sdmmc2): use DT helpers

Use dt_match_instance_by_compatible() and dt_fill_device_info()
functions to simplify SDMMC driver code.

Change-Id: Id16aa849ac79a9d3c2dc72c947fe189743856292
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(stm32mp1_clk): fix MPU clock rate

MPUDIV dividers are stored in a constant array, under bit shifts form.
They must be used in this way by the clock driver.

Change-Id: If758f7a4048eff956067a10a4

fix(stm32mp1_clk): fix MPU clock rate

MPUDIV dividers are stored in a constant array, under bit shifts form.
They must be used in this way by the clock driver.

Change-Id: If758f7a4048eff956067a10a42ab0983a20a000d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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fix(stm32mp1_clk): fix MCU/AXI parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is

fix(stm32mp1_clk): fix MCU/AXI parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is derived
from clock PLL2_P, not PLL2.

This change also renames MCU clock and AXI clock resources to
prevent confusion.

Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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refactor(stm32mp_clk): keep RCC node offset

To avoid parsing device tree file too often, keep the RCC node
offset value in a variable in fdt_get_rcc_node().

Change-Id: Ibb23ff92247d57c65a23517b8f34

refactor(stm32mp_clk): keep RCC node offset

To avoid parsing device tree file too often, keep the RCC node
offset value in a variable in fdt_get_rcc_node().

Change-Id: Ibb23ff92247d57c65a23517b8f3473f639794d2a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp1_clk): set other clocks as always on

AXI, MPU and MCU clocks are always on, put them in the list
in the function clock_is_always_on().

Change-Id: I969a442274d2da6c59636f3293de1c31b4c8e3

fix(stm32mp1_clk): set other clocks as always on

AXI, MPU and MCU clocks are always on, put them in the list
in the function clock_is_always_on().

Change-Id: I969a442274d2da6c59636f3293de1c31b4c8e3b1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "ethosn-multi-device" into integration

* changes:
feat(drivers/arm/ethosn)!: multi-device support
feat(fdt): add for_each_compatible_node macro

Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration

* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
fea

Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration

* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
feat(plat/rcar3): modify LifeC register setting for R-Car D3
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
feat(plat/rcar3): update DDR setting for R-Car D3
feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3
feat(plat/rcar3): add process of SSCG setting for R-Car D3
feat(plat/rcar3): add process to back up X6 and X7 register's value
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
feat(plat/rcar3): change the memory map for OP-TEE
feat(plat/rcar3): use PRR cut to determine DRAM size on M3
feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537
fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3
fix(plat/rcar3): fix eMMC boot support for R-Car D3
fix(plat/rcar3): fix version judgment for R-Car D3
fix(plat/rcar3): fix source file to make about GICv2
fix(drivers/rcar3): console: fix a return value of console_rcar_init

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Merge "refactor(drivers/st/clk): change fdt_get_rcc_node as static" into integration

Merge changes I16cac81b,I6c709c0c,I69581714,I018d158f,I23146f56, ... into integration

* changes:
fix(drivers/marvell/comphy-cp110): fix error code in pcie power on
fix(drivers/marvell/comphy-370

Merge changes I16cac81b,I6c709c0c,I69581714,I018d158f,I23146f56, ... into integration

* changes:
fix(drivers/marvell/comphy-cp110): fix error code in pcie power on
fix(drivers/marvell/comphy-3700): handle failures in power functions
fix(drivers/marvell/comphy-3700): fix address overflow
refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()
refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2
refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

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feat(drivers/arm/ethosn)!: multi-device support

Add support for Arm Ethos-N NPU multi-device.

The device tree parsing currently only supports one NPU device with
multiple cores. To be able to suppo

feat(drivers/arm/ethosn)!: multi-device support

Add support for Arm Ethos-N NPU multi-device.

The device tree parsing currently only supports one NPU device with
multiple cores. To be able to support multi-device NPU configurations
this patch adds support for having multiple NPU devices in the device
tree.

To be able to support multiple NPU devices in the SMC API, it has been
changed in an incompatible way so the API version has been bumped.

Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
Change-Id: Ide279ce949bd06e8939268b9601c267e45f3edc3

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fvp_r: load, auth, and transfer from BL1 to BL33

Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrme

fvp_r: load, auth, and transfer from BL1 to BL33

Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40

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Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk)

Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk): update RCC registers file
fix(stm32mp1_clk): keep RTCAPB clock always on
fix(stm32mp1_clk): fix RTC clock rating
fix(stm32mp1_clk): correctly manage RTC clock source
fix(spi_nand): check correct manufacturer id
fix(spi_nand): check that parameters have been set

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fix(drivers/marvell/comphy-cp110): fix error code in pcie power on

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to er

fix(drivers/marvell/comphy-cp110): fix error code in pcie power on

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to error code
-ETIMEDOUT on error like it is done in other functions.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I16cac81bbcbe2113e139722dc0e8fc2b85428d1b

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fix(drivers/marvell/comphy-3700): handle failures in power functions

Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropr

fix(drivers/marvell/comphy-3700): handle failures in power functions

Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropriate error
code in return value.

Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So return -ETIMEDOUT on error from power
functions like it is doing Marvell comphy-cp110 driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6c709c0c9616ab26829616a42a85b713f314b201

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fix(drivers/marvell/comphy-3700): fix address overflow

Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.

fix(drivers/marvell/comphy-3700): fix address overflow

Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.

Change type of 'offset' variables in mvebu_a3700_comphy_usb3_power_on()
and mvebu_a3700_comphy_sgmii_power_on() / off() functions to uintptr_t
as in this variable is stored physical address of registers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I69581714f8899d21cc1a27005747708f0f1cd933

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refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()

Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.

Remove pa

refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()

Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.

Remove parameter 'comphy_index' and instead of 32-bit variable 'mode',
pass only boolean value which represents 1 Gbps speed.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I018d158f689ddf7d1f57003717d709c00d988fba

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refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB

refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional
'mode' argument which is not needed anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85

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refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_S

refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_SATA_MODE, so
there is no need to pass comphy_mode parameter to this function. Use
directly COMPHY_SATA_MODE in mvebu_a3700_comphy_sata_power_off().

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib6b7c2bf62c1ef4d8a6af240c08696d5cd506b14

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refactor(drivers/st/clk): change fdt_get_rcc_node as static

Change the fdt_get_rcc_node function to static, as it is used only in
stm32mp_clkfunc.c file; it is only a cleanup change without function

refactor(drivers/st/clk): change fdt_get_rcc_node as static

Change the fdt_get_rcc_node function to static, as it is used only in
stm32mp_clkfunc.c file; it is only a cleanup change without functional
modification.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ib4ef110f6f1b16dbaa727a065e40275d3cf58a73

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fix(stm32_console): do not skip init for crash console

In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case

fix(stm32_console): do not skip init for crash console

In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case, UART should then be reconfigured.

[1] 7fa2e96e1 ("stm32mp1: add UART reset in crash console init")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I650d4c387b60dd74b780e6f3adfd629ea44f5834

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refactor(stm32mp1_clk): update RCC registers file

The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.

Change-Id: I4c

refactor(stm32mp1_clk): update RCC registers file

The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.

Change-Id: I4c222cf006caf27cda6da044eaf184ce66bb1442
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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