1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <endian.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/ufs.h> 19 #include <lib/mmio.h> 20 21 #define CDB_ADDR_MASK 127 22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK) 23 #define ALIGN_8(x) (((x) + 7) & ~7) 24 25 #define UFS_DESC_SIZE 0x400 26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */ 27 28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */ 29 30 static ufs_params_t ufs_params; 31 static int nutrs; /* Number of UTP Transfer Request Slots */ 32 33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd) 34 { 35 unsigned int data; 36 37 if (base == 0 || cmd == NULL) 38 return -EINVAL; 39 40 data = mmio_read_32(base + HCS); 41 if ((data & HCS_UCRDY) == 0) 42 return -EBUSY; 43 mmio_write_32(base + IS, ~0); 44 mmio_write_32(base + UCMDARG1, cmd->arg1); 45 mmio_write_32(base + UCMDARG2, cmd->arg2); 46 mmio_write_32(base + UCMDARG3, cmd->arg3); 47 mmio_write_32(base + UICCMD, cmd->op); 48 49 do { 50 data = mmio_read_32(base + IS); 51 } while ((data & UFS_INT_UCCS) == 0); 52 mmio_write_32(base + IS, UFS_INT_UCCS); 53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK; 54 } 55 56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val) 57 { 58 uintptr_t base; 59 unsigned int data; 60 int result, retries; 61 uic_cmd_t cmd; 62 63 assert(ufs_params.reg_base != 0); 64 65 if (val == NULL) 66 return -EINVAL; 67 68 base = ufs_params.reg_base; 69 for (retries = 0; retries < 100; retries++) { 70 data = mmio_read_32(base + HCS); 71 if ((data & HCS_UCRDY) != 0) 72 break; 73 mdelay(1); 74 } 75 if (retries >= 100) 76 return -EBUSY; 77 78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 79 cmd.arg2 = 0; 80 cmd.arg3 = 0; 81 cmd.op = DME_GET; 82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 83 result = ufshc_send_uic_cmd(base, &cmd); 84 if (result == 0) 85 break; 86 data = mmio_read_32(base + IS); 87 if (data & UFS_INT_UE) 88 return -EINVAL; 89 } 90 if (retries >= UFS_UIC_COMMAND_RETRIES) 91 return -EIO; 92 93 *val = mmio_read_32(base + UCMDARG3); 94 return 0; 95 } 96 97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val) 98 { 99 uintptr_t base; 100 unsigned int data; 101 int result, retries; 102 uic_cmd_t cmd; 103 104 assert((ufs_params.reg_base != 0)); 105 106 base = ufs_params.reg_base; 107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 108 cmd.arg2 = 0; 109 cmd.arg3 = val; 110 cmd.op = DME_SET; 111 112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 113 result = ufshc_send_uic_cmd(base, &cmd); 114 if (result == 0) 115 break; 116 data = mmio_read_32(base + IS); 117 if (data & UFS_INT_UE) 118 return -EINVAL; 119 } 120 if (retries >= UFS_UIC_COMMAND_RETRIES) 121 return -EIO; 122 123 return 0; 124 } 125 126 static void ufshc_reset(uintptr_t base) 127 { 128 unsigned int data; 129 130 /* Enable Host Controller */ 131 mmio_write_32(base + HCE, HCE_ENABLE); 132 /* Wait until basic initialization sequence completed */ 133 do { 134 data = mmio_read_32(base + HCE); 135 } while ((data & HCE_ENABLE) == 0); 136 137 /* Enable Interrupts */ 138 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES | 139 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES; 140 mmio_write_32(base + IE, data); 141 } 142 143 static int ufshc_link_startup(uintptr_t base) 144 { 145 uic_cmd_t cmd; 146 int data, result; 147 int retries; 148 149 for (retries = 10; retries > 0; retries--) { 150 memset(&cmd, 0, sizeof(cmd)); 151 cmd.op = DME_LINKSTARTUP; 152 result = ufshc_send_uic_cmd(base, &cmd); 153 if (result != 0) 154 continue; 155 while ((mmio_read_32(base + HCS) & HCS_DP) == 0) 156 ; 157 data = mmio_read_32(base + IS); 158 if (data & UFS_INT_ULSS) 159 mmio_write_32(base + IS, UFS_INT_ULSS); 160 return 0; 161 } 162 return -EIO; 163 } 164 165 /* Check Door Bell register to get an empty slot */ 166 static int get_empty_slot(int *slot) 167 { 168 unsigned int data; 169 int i; 170 171 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 172 for (i = 0; i < nutrs; i++) { 173 if ((data & 1) == 0) 174 break; 175 data = data >> 1; 176 } 177 if (i >= nutrs) 178 return -EBUSY; 179 *slot = i; 180 return 0; 181 } 182 183 static void get_utrd(utp_utrd_t *utrd) 184 { 185 uintptr_t base; 186 int slot = 0, result; 187 utrd_header_t *hd; 188 189 assert(utrd != NULL); 190 result = get_empty_slot(&slot); 191 assert(result == 0); 192 193 /* clear utrd */ 194 memset((void *)utrd, 0, sizeof(utp_utrd_t)); 195 base = ufs_params.desc_base + (slot * UFS_DESC_SIZE); 196 /* clear the descriptor */ 197 memset((void *)base, 0, UFS_DESC_SIZE); 198 199 utrd->header = base; 200 utrd->task_tag = slot + 1; 201 /* CDB address should be aligned with 128 bytes */ 202 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t)); 203 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t)); 204 utrd->size_upiu = utrd->resp_upiu - utrd->upiu; 205 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t)); 206 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu; 207 208 hd = (utrd_header_t *)utrd->header; 209 hd->ucdba = utrd->upiu & UINT32_MAX; 210 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX; 211 /* Both RUL and RUO is based on DWORD */ 212 hd->rul = utrd->size_resp_upiu >> 2; 213 hd->ruo = utrd->size_upiu >> 2; 214 (void)result; 215 } 216 217 /* 218 * Prepare UTRD, Command UPIU, Response UPIU. 219 */ 220 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, 221 int lba, uintptr_t buf, size_t length) 222 { 223 utrd_header_t *hd; 224 cmd_upiu_t *upiu; 225 prdt_t *prdt; 226 unsigned int ulba; 227 unsigned int lba_cnt; 228 int prdt_size; 229 230 231 mmio_write_32(ufs_params.reg_base + UTRLBA, 232 utrd->header & UINT32_MAX); 233 mmio_write_32(ufs_params.reg_base + UTRLBAU, 234 (utrd->upiu >> 32) & UINT32_MAX); 235 236 hd = (utrd_header_t *)utrd->header; 237 upiu = (cmd_upiu_t *)utrd->upiu; 238 239 hd->i = 1; 240 hd->ct = CT_UFS_STORAGE; 241 hd->ocs = OCS_MASK; 242 243 upiu->trans_type = CMD_UPIU; 244 upiu->task_tag = utrd->task_tag; 245 upiu->cdb[0] = op; 246 ulba = (unsigned int)lba; 247 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT); 248 switch (op) { 249 case CDBCMD_TEST_UNIT_READY: 250 break; 251 case CDBCMD_READ_CAPACITY_10: 252 hd->dd = DD_OUT; 253 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 254 upiu->lun = lun; 255 break; 256 case CDBCMD_READ_10: 257 hd->dd = DD_OUT; 258 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 259 upiu->lun = lun; 260 upiu->cdb[1] = RW_WITHOUT_CACHE; 261 /* set logical block address */ 262 upiu->cdb[2] = (ulba >> 24) & 0xff; 263 upiu->cdb[3] = (ulba >> 16) & 0xff; 264 upiu->cdb[4] = (ulba >> 8) & 0xff; 265 upiu->cdb[5] = ulba & 0xff; 266 /* set transfer length */ 267 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 268 upiu->cdb[8] = lba_cnt & 0xff; 269 break; 270 case CDBCMD_WRITE_10: 271 hd->dd = DD_IN; 272 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S; 273 upiu->lun = lun; 274 upiu->cdb[1] = RW_WITHOUT_CACHE; 275 /* set logical block address */ 276 upiu->cdb[2] = (ulba >> 24) & 0xff; 277 upiu->cdb[3] = (ulba >> 16) & 0xff; 278 upiu->cdb[4] = (ulba >> 8) & 0xff; 279 upiu->cdb[5] = ulba & 0xff; 280 /* set transfer length */ 281 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 282 upiu->cdb[8] = lba_cnt & 0xff; 283 break; 284 default: 285 assert(0); 286 break; 287 } 288 if (hd->dd == DD_IN) 289 flush_dcache_range(buf, length); 290 else if (hd->dd == DD_OUT) 291 inv_dcache_range(buf, length); 292 if (length) { 293 upiu->exp_data_trans_len = htobe32(length); 294 assert(lba_cnt <= UINT16_MAX); 295 prdt = (prdt_t *)utrd->prdt; 296 297 prdt_size = 0; 298 while (length > 0) { 299 prdt->dba = (unsigned int)(buf & UINT32_MAX); 300 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX); 301 /* prdt->dbc counts from 0 */ 302 if (length > MAX_PRDT_SIZE) { 303 prdt->dbc = MAX_PRDT_SIZE - 1; 304 length = length - MAX_PRDT_SIZE; 305 } else { 306 prdt->dbc = length - 1; 307 length = 0; 308 } 309 buf += MAX_PRDT_SIZE; 310 prdt++; 311 prdt_size += sizeof(prdt_t); 312 } 313 utrd->size_prdt = ALIGN_8(prdt_size); 314 hd->prdtl = utrd->size_prdt >> 2; 315 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2; 316 } 317 318 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); 319 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 320 return 0; 321 } 322 323 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, 324 uint8_t index, uint8_t sel, 325 uintptr_t buf, size_t length) 326 { 327 utrd_header_t *hd; 328 query_upiu_t *query_upiu; 329 330 331 hd = (utrd_header_t *)utrd->header; 332 query_upiu = (query_upiu_t *)utrd->upiu; 333 334 mmio_write_32(ufs_params.reg_base + UTRLBA, 335 utrd->header & UINT32_MAX); 336 mmio_write_32(ufs_params.reg_base + UTRLBAU, 337 (utrd->header >> 32) & UINT32_MAX); 338 339 340 hd->i = 1; 341 hd->ct = CT_UFS_STORAGE; 342 hd->ocs = OCS_MASK; 343 344 query_upiu->trans_type = QUERY_REQUEST_UPIU; 345 query_upiu->task_tag = utrd->task_tag; 346 query_upiu->ts.desc.opcode = op; 347 query_upiu->ts.desc.idn = idn; 348 query_upiu->ts.desc.index = index; 349 query_upiu->ts.desc.selector = sel; 350 switch (op) { 351 case QUERY_READ_DESC: 352 query_upiu->query_func = QUERY_FUNC_STD_READ; 353 query_upiu->ts.desc.length = htobe16(length); 354 break; 355 case QUERY_WRITE_DESC: 356 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 357 query_upiu->ts.desc.length = htobe16(length); 358 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)), 359 (void *)buf, length); 360 break; 361 case QUERY_READ_ATTR: 362 case QUERY_READ_FLAG: 363 query_upiu->query_func = QUERY_FUNC_STD_READ; 364 break; 365 case QUERY_CLEAR_FLAG: 366 case QUERY_SET_FLAG: 367 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 368 break; 369 case QUERY_WRITE_ATTR: 370 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 371 memcpy((void *)&query_upiu->ts.attr.value, (void *)buf, length); 372 break; 373 default: 374 assert(0); 375 break; 376 } 377 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); 378 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 379 return 0; 380 } 381 382 static void ufs_prepare_nop_out(utp_utrd_t *utrd) 383 { 384 utrd_header_t *hd; 385 nop_out_upiu_t *nop_out; 386 387 mmio_write_32(ufs_params.reg_base + UTRLBA, 388 utrd->header & UINT32_MAX); 389 mmio_write_32(ufs_params.reg_base + UTRLBAU, 390 (utrd->header >> 32) & UINT32_MAX); 391 392 hd = (utrd_header_t *)utrd->header; 393 nop_out = (nop_out_upiu_t *)utrd->upiu; 394 395 hd->i = 1; 396 hd->ct = CT_UFS_STORAGE; 397 hd->ocs = OCS_MASK; 398 399 nop_out->trans_type = 0; 400 nop_out->task_tag = utrd->task_tag; 401 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); 402 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 403 } 404 405 static void ufs_send_request(int task_tag) 406 { 407 unsigned int data; 408 int slot; 409 410 slot = task_tag - 1; 411 /* clear all interrupts */ 412 mmio_write_32(ufs_params.reg_base + IS, ~0); 413 414 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1); 415 do { 416 data = mmio_read_32(ufs_params.reg_base + UTRLRSR); 417 } while (data == 0); 418 419 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) | 420 UTRIACR_IATOVAL(0xFF); 421 mmio_write_32(ufs_params.reg_base + UTRIACR, data); 422 /* send request */ 423 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot); 424 } 425 426 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) 427 { 428 utrd_header_t *hd; 429 resp_upiu_t *resp; 430 unsigned int data; 431 int slot; 432 433 hd = (utrd_header_t *)utrd->header; 434 resp = (resp_upiu_t *)utrd->resp_upiu; 435 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); 436 inv_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); 437 do { 438 data = mmio_read_32(ufs_params.reg_base + IS); 439 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0) 440 return -EIO; 441 } while ((data & UFS_INT_UTRCS) == 0); 442 slot = utrd->task_tag - 1; 443 444 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 445 assert((data & (1 << slot)) == 0); 446 assert(hd->ocs == OCS_SUCCESS); 447 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); 448 (void)resp; 449 (void)slot; 450 return 0; 451 } 452 453 #ifdef UFS_RESP_DEBUG 454 static void dump_upiu(utp_utrd_t *utrd) 455 { 456 utrd_header_t *hd; 457 int i; 458 459 hd = (utrd_header_t *)utrd->header; 460 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n", 461 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs, 462 mmio_read_32(ufs_params.reg_base + UTRLDBR)); 463 for (i = 0; i < sizeof(utrd_header_t); i += 4) { 464 INFO("[%lx]:0x%x\n", 465 (uintptr_t)utrd->header + i, 466 *(unsigned int *)((uintptr_t)utrd->header + i)); 467 } 468 469 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) { 470 INFO("cmd[%lx]:0x%x\n", 471 utrd->upiu + i, 472 *(unsigned int *)(utrd->upiu + i)); 473 } 474 for (i = 0; i < sizeof(resp_upiu_t); i += 4) { 475 INFO("resp[%lx]:0x%x\n", 476 utrd->resp_upiu + i, 477 *(unsigned int *)(utrd->resp_upiu + i)); 478 } 479 for (i = 0; i < sizeof(prdt_t); i += 4) { 480 INFO("prdt[%lx]:0x%x\n", 481 utrd->prdt + i, 482 *(unsigned int *)(utrd->prdt + i)); 483 } 484 } 485 #endif 486 487 static void ufs_verify_init(void) 488 { 489 utp_utrd_t utrd; 490 int result; 491 492 get_utrd(&utrd); 493 ufs_prepare_nop_out(&utrd); 494 ufs_send_request(utrd.task_tag); 495 result = ufs_check_resp(&utrd, NOP_IN_UPIU); 496 assert(result == 0); 497 (void)result; 498 } 499 500 static void ufs_verify_ready(void) 501 { 502 utp_utrd_t utrd; 503 int result; 504 505 get_utrd(&utrd); 506 ufs_prepare_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); 507 ufs_send_request(utrd.task_tag); 508 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 509 assert(result == 0); 510 (void)result; 511 } 512 513 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, 514 uintptr_t buf, size_t size) 515 { 516 utp_utrd_t utrd; 517 query_resp_upiu_t *resp; 518 int result; 519 520 switch (op) { 521 case QUERY_READ_FLAG: 522 case QUERY_READ_ATTR: 523 case QUERY_READ_DESC: 524 case QUERY_WRITE_DESC: 525 case QUERY_WRITE_ATTR: 526 assert(((buf & 3) == 0) && (size != 0)); 527 break; 528 default: 529 /* Do nothing in default case */ 530 break; 531 } 532 get_utrd(&utrd); 533 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); 534 ufs_send_request(utrd.task_tag); 535 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU); 536 assert(result == 0); 537 resp = (query_resp_upiu_t *)utrd.resp_upiu; 538 #ifdef UFS_RESP_DEBUG 539 dump_upiu(&utrd); 540 #endif 541 assert(resp->query_resp == QUERY_RESP_SUCCESS); 542 543 switch (op) { 544 case QUERY_READ_FLAG: 545 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value; 546 break; 547 case QUERY_READ_ATTR: 548 case QUERY_READ_DESC: 549 memcpy((void *)buf, 550 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), 551 size); 552 break; 553 default: 554 /* Do nothing in default case */ 555 break; 556 } 557 (void)result; 558 } 559 560 unsigned int ufs_read_attr(int idn) 561 { 562 unsigned int value; 563 564 ufs_query(QUERY_READ_ATTR, idn, 0, 0, 565 (uintptr_t)&value, sizeof(value)); 566 return value; 567 } 568 569 void ufs_write_attr(int idn, unsigned int value) 570 { 571 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0, 572 (uintptr_t)&value, sizeof(value)); 573 } 574 575 unsigned int ufs_read_flag(int idn) 576 { 577 unsigned int value; 578 579 ufs_query(QUERY_READ_FLAG, idn, 0, 0, 580 (uintptr_t)&value, sizeof(value)); 581 return value; 582 } 583 584 void ufs_set_flag(int idn) 585 { 586 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0); 587 } 588 589 void ufs_clear_flag(int idn) 590 { 591 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0); 592 } 593 594 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size) 595 { 596 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size); 597 } 598 599 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size) 600 { 601 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size); 602 } 603 604 static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) 605 { 606 utp_utrd_t utrd; 607 resp_upiu_t *resp; 608 sense_data_t *sense; 609 unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; 610 uintptr_t buf; 611 int result; 612 int retry; 613 614 assert((ufs_params.reg_base != 0) && 615 (ufs_params.desc_base != 0) && 616 (ufs_params.desc_size >= UFS_DESC_SIZE) && 617 (num != NULL) && (size != NULL)); 618 619 /* align buf address */ 620 buf = (uintptr_t)data; 621 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) & 622 ~(CACHE_WRITEBACK_GRANULE - 1); 623 memset((void *)buf, 0, CACHE_WRITEBACK_GRANULE); 624 flush_dcache_range(buf, CACHE_WRITEBACK_GRANULE); 625 do { 626 get_utrd(&utrd); 627 ufs_prepare_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, 628 buf, READ_CAPACITY_LENGTH); 629 ufs_send_request(utrd.task_tag); 630 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 631 assert(result == 0); 632 #ifdef UFS_RESP_DEBUG 633 dump_upiu(&utrd); 634 #endif 635 resp = (resp_upiu_t *)utrd.resp_upiu; 636 retry = 0; 637 sense = &resp->sd.sense; 638 if (sense->resp_code == SENSE_DATA_VALID) { 639 if ((sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && 640 (sense->asc == 0x29) && (sense->ascq == 0)) { 641 retry = 1; 642 } 643 } 644 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); 645 /* last logical block address */ 646 *num = be32toh(*(unsigned int *)buf); 647 if (*num) 648 *num += 1; 649 /* logical block length in bytes */ 650 *size = be32toh(*(unsigned int *)(buf + 4)); 651 } while (retry); 652 (void)result; 653 } 654 655 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) 656 { 657 utp_utrd_t utrd; 658 resp_upiu_t *resp; 659 int result; 660 661 assert((ufs_params.reg_base != 0) && 662 (ufs_params.desc_base != 0) && 663 (ufs_params.desc_size >= UFS_DESC_SIZE)); 664 665 memset((void *)buf, 0, size); 666 get_utrd(&utrd); 667 ufs_prepare_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); 668 ufs_send_request(utrd.task_tag); 669 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 670 assert(result == 0); 671 #ifdef UFS_RESP_DEBUG 672 dump_upiu(&utrd); 673 #endif 674 resp = (resp_upiu_t *)utrd.resp_upiu; 675 (void)result; 676 return size - resp->res_trans_cnt; 677 } 678 679 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size) 680 { 681 utp_utrd_t utrd; 682 resp_upiu_t *resp; 683 int result; 684 685 assert((ufs_params.reg_base != 0) && 686 (ufs_params.desc_base != 0) && 687 (ufs_params.desc_size >= UFS_DESC_SIZE)); 688 689 memset((void *)buf, 0, size); 690 get_utrd(&utrd); 691 ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); 692 ufs_send_request(utrd.task_tag); 693 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 694 assert(result == 0); 695 #ifdef UFS_RESP_DEBUG 696 dump_upiu(&utrd); 697 #endif 698 resp = (resp_upiu_t *)utrd.resp_upiu; 699 (void)result; 700 return size - resp->res_trans_cnt; 701 } 702 703 static void ufs_enum(void) 704 { 705 unsigned int blk_num, blk_size; 706 int i; 707 708 /* 0 means 1 slot */ 709 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; 710 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) 711 nutrs = ufs_params.desc_size / UFS_DESC_SIZE; 712 713 ufs_verify_init(); 714 ufs_verify_ready(); 715 716 ufs_set_flag(FLAG_DEVICE_INIT); 717 mdelay(200); 718 /* dump available LUNs */ 719 for (i = 0; i < UFS_MAX_LUNS; i++) { 720 ufs_read_capacity(i, &blk_num, &blk_size); 721 if (blk_num && blk_size) { 722 INFO("UFS LUN%d contains %d blocks with %d-byte size\n", 723 i, blk_num, blk_size); 724 } 725 } 726 } 727 728 static void ufs_get_device_info(struct ufs_dev_desc *card_data) 729 { 730 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE]; 731 732 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0, 733 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE); 734 735 /* 736 * getting vendor (manufacturerID) and Bank Index in big endian 737 * format 738 */ 739 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) | 740 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1])); 741 } 742 743 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params) 744 { 745 int result; 746 unsigned int data; 747 uic_cmd_t cmd; 748 struct ufs_dev_desc card = {0}; 749 750 assert((params != NULL) && 751 (params->reg_base != 0) && 752 (params->desc_base != 0) && 753 (params->desc_size >= UFS_DESC_SIZE)); 754 755 memcpy(&ufs_params, params, sizeof(ufs_params_t)); 756 757 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { 758 result = ufshc_dme_get(0x1571, 0, &data); 759 assert(result == 0); 760 result = ufshc_dme_get(0x41, 0, &data); 761 assert(result == 0); 762 if (data == 1) { 763 /* prepare to exit hibernate mode */ 764 memset(&cmd, 0, sizeof(uic_cmd_t)); 765 cmd.op = DME_HIBERNATE_EXIT; 766 result = ufshc_send_uic_cmd(ufs_params.reg_base, 767 &cmd); 768 assert(result == 0); 769 data = mmio_read_32(ufs_params.reg_base + UCMDARG2); 770 assert(data == 0); 771 do { 772 data = mmio_read_32(ufs_params.reg_base + IS); 773 } while ((data & UFS_INT_UHXS) == 0); 774 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS); 775 data = mmio_read_32(ufs_params.reg_base + HCS); 776 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL); 777 } 778 result = ufshc_dme_get(0x1568, 0, &data); 779 assert(result == 0); 780 assert((data > 0) && (data <= 3)); 781 } else { 782 assert((ops != NULL) && (ops->phy_init != NULL) && 783 (ops->phy_set_pwr_mode != NULL)); 784 785 ufshc_reset(ufs_params.reg_base); 786 ops->phy_init(&ufs_params); 787 result = ufshc_link_startup(ufs_params.reg_base); 788 assert(result == 0); 789 790 ufs_enum(); 791 792 ufs_get_device_info(&card); 793 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) { 794 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX; 795 } 796 797 ops->phy_set_pwr_mode(&ufs_params); 798 } 799 800 (void)result; 801 return 0; 802 } 803