feat(imx93): add the trdc driver

Add the trdc driver that is used on NXP i.MX9 family

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie1fd86b76564fa7e20d74d5b4dbfe7ea0ee851fc

fix(st-uart): correctly check UART enabled in flush fonction

Use tst instead of ands to check USART_CR1_UE bit is set. If not exit
the flush function.

Signed-off-by: Yann Gautier <yann.gautier@st.c

fix(st-uart): correctly check UART enabled in flush fonction

Use tst instead of ands to check USART_CR1_UE bit is set. If not exit
the flush function.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibd2e18f6d8837073d0bbcb150e993985d3c0dd6f

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Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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fix(gicv3): move invocation of gicv3_get_multichip_base function

gicv3_get_multichip_base in case of GICV3_IMPL_GIC600_MULTICHIP flag
being set, only works if the id belongs to SPI range.
Moving inv

fix(gicv3): move invocation of gicv3_get_multichip_base function

gicv3_get_multichip_base in case of GICV3_IMPL_GIC600_MULTICHIP flag
being set, only works if the id belongs to SPI range.
Moving invocation of the function after confirming that the
intr_num belongs to SPI range.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I429eb473a7aeccb30309b1ffa5994663393ba0a2

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fix(gic600): fix gic600 maximum SPI ID

According to GIC-600 TRM, it supports up to 960 SPIs. With the
starting SPI_ID of 32, the maximum SPI_ID should be 991. This patch
fixes the value of GIC600_SP

fix(gic600): fix gic600 maximum SPI ID

According to GIC-600 TRM, it supports up to 960 SPIs. With the
starting SPI_ID of 32, the maximum SPI_ID should be 991. This patch
fixes the value of GIC600_SPI_ID_MAX which is currently configured
to be 960.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I441f9a607d160db8533f2a03e02afd1a9bab991e

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fix(auth): allow hashes of different lengths

Trusted Board Boot supports multiple hash algorithms, including SHA-256,
SHA-384, and SHA-512. These algorithms produce hashes of different
lengths, so

fix(auth): allow hashes of different lengths

Trusted Board Boot supports multiple hash algorithms, including SHA-256,
SHA-384, and SHA-512. These algorithms produce hashes of different
lengths, so the resulting DER-encoded hash objects are also of different
lengths. However, the common Trusted Board Boot code only stores the
contents of the object, not its length. Before commit
f47547b35462571636a76b737602e827ae43bc24, this was harmless: ASN.1
objects are self-delimiting, and any excess padding was ignored.
f47547b35462571636a76b737602e827ae43bc24 changed the code to reject
excess padding. However, this breaks using a shorter hash in a build
that supports longer hashes: the shorter hash will have padding after
it, and verify_hash() will reject it. This was found by an Arm
customer: TF-A v2.9 refused to boot, even though TF-A v2.6 (which did
not have f47547b35462571636a76b737602e827ae43bc24) worked just fine.

Storing the length of the hash turns out to be quite difficult.
However, it turns out that hashes verified by verify_hash() always come
from the ROTPK or an X.509 certificate extension. Furthermore, _all_
X.509 certificate extensions used by Trusted Board Boot are ASN.1
DER encoded, so it is possible to reject padding in get_ext(). Padding
after the ROTPK is harmless, and it is better to ignore that padding
than to refuse to boot the system.

Change-Id: I28a19d7783e6036b65e86426d78c8e5b2ed6f542
Fixes: f47547b35462571636a76b737602e827ae43bc24 ("fix(auth): reject invalid padding in digests")
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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Merge changes from topic "st-fixes" into integration

* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip

Merge changes from topic "st-fixes" into integration

* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip console flush if UART is disabled
fix(st): flush UART at the end of uart_read()
fix(stm32mp1): use the BSEC nodes compatible for stm32mp13
fix(stm32mp13-fdts): correct the BSEC nodes compatible
fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files
fix(stm32mp1): properly check PSCI functions return

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Merge changes from topic "cot_cca_nvctr" into integration

* changes:
feat(fvp): mock support for CCA NV ctr
feat(auth): add CCA NV ctr to CCA CoT
feat(build): pass CCA NV ctr option to cert_cr

Merge changes from topic "cot_cca_nvctr" into integration

* changes:
feat(fvp): mock support for CCA NV ctr
feat(auth): add CCA NV ctr to CCA CoT
feat(build): pass CCA NV ctr option to cert_create
feat(cert-create): add new option for CCA NV ctr

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fix(spi-nand): add Quad Enable management

The framework currently supports QE feature only for Macronix devices.
Kioxia devices also support this feature, but this feature can not be
set based on th

fix(spi-nand): add Quad Enable management

The framework currently supports QE feature only for Macronix devices.
Kioxia devices also support this feature, but this feature can not be
set based on the manufacturer ID as Kioxia first SPI NAND generation
does not support the QE feature when the second generation does.

Use a flag to manage QE feature. This flag will be added at board level
to manage the device.

Change-Id: I7a3683a2df8739967b17b4abbec32c51bf206b93
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>

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fix(st-clock): disabling CKPER clock is not functional on stm32mp13

The mask used to configure the CKPER MUX was wrong and unnecessary.

Change-Id: I40098f2a27b9e5ba8706ab5377d23f578c09838b
Signed-o

fix(st-clock): disabling CKPER clock is not functional on stm32mp13

The mask used to configure the CKPER MUX was wrong and unnecessary.

Change-Id: I40098f2a27b9e5ba8706ab5377d23f578c09838b
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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fix(st-uart): skip console flush if UART is disabled

Check the USART_CR1_UE bit and if it is 0, the UART is not enabled,
or not clocked (but the read won't freeze the bus and will return 0).
In this

fix(st-uart): skip console flush if UART is disabled

Check the USART_CR1_UE bit and if it is 0, the UART is not enabled,
or not clocked (but the read won't freeze the bus and will return 0).
In this case skip the console flush.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5d1ef7e51612b4795e314b2f2da04a514b6c96a0

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refactor(cpus): move cpu_ops field defines to a header

The cpu_macros.S file is loaded with lots of definitions for the cpu_ops
structure. However, since they are defined as .equ directives they are

refactor(cpus): move cpu_ops field defines to a header

The cpu_macros.S file is loaded with lots of definitions for the cpu_ops
structure. However, since they are defined as .equ directives they are
inaccessible for C code. Convert them to #defines, put them into order,
refactor them for readability, and extract them to a separate file to
make this possible.

This has the benefit of removing some Aarch differences and a lot of
duplicate code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I72861794b6c9131285a9297d5918822ed718b228

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feat(auth): add CCA NV ctr to CCA CoT

Modifying the CCA CoT description to put the CCA content certificate
under the new CCA NV counter.

Change-Id: Ib962cef5eaa15bb9ccce86012f21327d29d4adad
Signed-

feat(auth): add CCA NV ctr to CCA CoT

Modifying the CCA CoT description to put the CCA content certificate
under the new CCA NV counter.

Change-Id: Ib962cef5eaa15bb9ccce86012f21327d29d4adad
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

Merge changes from topic "bk/context_refactor" into integration

* changes:
fix(gicv3): restore scr_el3 after changing it
refactor(cm): make SVE and SME build dependencies logical

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge changes I06b35f11,If80573d6 into integration

* changes:
docs: remove plat_convert_pk() interface from release doc
chore(io): remove io_dummy driver

Merge changes from topic "assert_boolean_set" into integration

* changes:
build!: check boolean flags are not empty
fix(build): add a default value for INVERTED_MEMMAP
fix(a5ds): add default v

Merge changes from topic "assert_boolean_set" into integration

* changes:
build!: check boolean flags are not empty
fix(build): add a default value for INVERTED_MEMMAP
fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG
fix(st-crypto): move flag control into source code
fix(stm32mp1): always define PKA algos flags
fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

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fix(gicv3): restore scr_el3 after changing it

EL3's context is poorly defined as it is and polluting it further is not
a good idea. Put it back as it was before the function call.

Signed-off-by: Bo

fix(gicv3): restore scr_el3 after changing it

EL3's context is poorly defined as it is and polluting it further is not
a good idea. Put it back as it was before the function call.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9d13c9517962b501246989fd2126d08410191784

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feat(sbsa): helper api for refreshing watchdog timer

This patch adds a helper API to explicitly refresh SBSA secure watchdog
timer. Please refer section A.3 of the following spec:

https://developer

feat(sbsa): helper api for refreshing watchdog timer

This patch adds a helper API to explicitly refresh SBSA secure watchdog
timer. Please refer section A.3 of the following spec:

https://developer.arm.com/documentation/den0029/latest/

Change-Id: I2d0943792aea0092bee1e51d74b908348587e66b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(st-crypto): move flag control into source code

Remove the control from the include file to avoid compilation
issue. Add the check in the source code instead.

Signed-off-by: Lionel Debieve <lion

fix(st-crypto): move flag control into source code

Remove the control from the include file to avoid compilation
issue. Add the check in the source code instead.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I533f829607f76389399a3e8dbc3c6095278562ab

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chore(io): remove io_dummy driver

In accordance with [1], delete the io_dummy driver code in preparation
for the v2.9 release.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/release-i

chore(io): remove io_dummy driver

In accordance with [1], delete the io_dummy driver code in preparation
for the v2.9 release.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: If80573d6f889624ef06b099fd267ee85f3a6331e

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fix(ufs): poll UCRDY for all commands

Host must only set UICCMD if HCS.UCRDY is set to 1.
At present, SW polls for UCRDY only before sending DME_GET.
Generalise this behaviour for DME_SET, DME_LINKS

fix(ufs): poll UCRDY for all commands

Host must only set UICCMD if HCS.UCRDY is set to 1.
At present, SW polls for UCRDY only before sending DME_GET.
Generalise this behaviour for DME_SET, DME_LINKSTARTUP,
DME_HIBERNATE_EXIT by moving polling logic inside ufshc_send_uic_cmd.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: Iece777f803a660fdd144a073834c221e889371a6

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refactor(auth)!: unify REGISTER_CRYPTO_LIB

Have only one definition for REGISTER_CRYPTO_LIB macro, with all the
possible fields. Worst case adds 4 u64 to crypto_lib_desc.
While at it, correct some M

refactor(auth)!: unify REGISTER_CRYPTO_LIB

Have only one definition for REGISTER_CRYPTO_LIB macro, with all the
possible fields. Worst case adds 4 u64 to crypto_lib_desc.
While at it, correct some MISRA violations:
MC3R1.R12.1: (advisory) The precedence of operators within expressions
should be made explicit.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1342a20e6eef2354753182c2a81ff959e03e5c81

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refactor(auth): replace plat_convert_pk

Following discussions in the reviews of the patch that introduced
plat_convert_pk() function [1], it was decided to deprecate it to
avoid weak function declar

refactor(auth): replace plat_convert_pk

Following discussions in the reviews of the patch that introduced
plat_convert_pk() function [1], it was decided to deprecate it to
avoid weak function declaration.
A new optional function pointer convert_pk is added to crypto_lib_desc_t.
A new function crypto_mod_convert_pk() will either call
crypto_lib_desc.convert_pk() if it is defined, or do the same
as what was done by the weak function otherwise.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17174

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9358867f8bfd5e96b5ee238c066877da368e43c6

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