1/* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * --------------------------------------------------------------------- 36 */ 37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 38 mrs x0, sctlr_el3 39 orr x0, x0, x1 40 msr sctlr_el3, x0 41 isb 42 43#ifdef IMAGE_BL31 44 /* --------------------------------------------------------------------- 45 * Initialise the per-cpu cache pointer to the CPU. 46 * This is done early to enable crash reporting to have access to crash 47 * stack. Since crash reporting depends on cpu_data to report the 48 * unhandled exception, not doing so can lead to recursive exceptions 49 * due to a NULL TPIDR_EL3. 50 * --------------------------------------------------------------------- 51 */ 52 bl init_cpu_data_ptr 53#endif /* IMAGE_BL31 */ 54 55 /* --------------------------------------------------------------------- 56 * Initialise SCR_EL3, setting all fields rather than relying on hw. 57 * All fields are architecturally UNKNOWN on reset. The following fields 58 * do not change during the TF lifetime. The remaining fields are set to 59 * zero here but are updated ahead of transitioning to a lower EL in the 60 * function cm_init_context_common(). 61 * 62 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 63 * EL2, EL1 and EL0 are not trapped to EL3. 64 * 65 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 66 * EL2, EL1 and EL0 are not trapped to EL3. 67 * 68 * SCR_EL3.SIF: Set to one to disable instruction fetches from 69 * Non-secure memory. 70 * 71 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 72 * both Security states and both Execution states. 73 * 74 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 75 * to EL3 when executing at any EL. 76 * 77 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 78 * disable traps to EL3 when accessing key registers or using pointer 79 * authentication instructions from lower ELs. 80 * --------------------------------------------------------------------- 81 */ 82 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 83 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 84#if CTX_INCLUDE_PAUTH_REGS 85 /* 86 * If the pointer authentication registers are saved during world 87 * switches, enable pointer authentication everywhere, as it is safe to 88 * do so. 89 */ 90 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 91#endif 92#if ENABLE_RME 93 /* 94 * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers 95 * in context management. This will need to be refactored. 96 */ 97 orr x0, x0, #SCR_EEL2_BIT 98#endif 99 msr scr_el3, x0 100 101 /* --------------------------------------------------------------------- 102 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 103 * Some fields are architecturally UNKNOWN on reset. 104 * 105 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 106 * Debug exceptions, other than Breakpoint Instruction exceptions, are 107 * disabled from all ELs in Secure state. 108 * 109 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 110 * privileged debug from S-EL1. 111 * 112 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 113 * access to the powerdown debug registers do not trap to EL3. 114 * 115 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 116 * debug registers, other than those registers that are controlled by 117 * MDCR_EL3.TDOSA. 118 * 119 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 120 * accesses to all Performance Monitors registers do not trap to EL3. 121 * 122 * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer 123 * owning security state is Secure state. If FEAT_TRBE is implemented, 124 * accesses to Trace Buffer control registers at EL2 and EL1 in any 125 * security state generates trap exceptions to EL3. 126 * If FEAT_TRBE is not implemented, these bits are RES0. 127 * 128 * MDCR_EL3.TTRF: Set to one so that access to trace filter control 129 * registers in non-monitor mode generate EL3 trap exception, 130 * unless the access generates a higher priority exception when trace 131 * filter control(FEAT_TRF) is implemented. 132 * When FEAT_TRF is not implemented, this bit is RES0. 133 * --------------------------------------------------------------------- 134 */ 135 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 136 MDCR_SPD32(MDCR_SPD32_DISABLE)) & \ 137 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT | \ 138 MDCR_NSTB(MDCR_NSTB_EL1) | MDCR_NSTBE | MDCR_TTRF_BIT)) 139 140 mrs x1, id_aa64dfr0_el1 141 ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH 142 cbz x1, 1f 143 orr x0, x0, #MDCR_TTRF_BIT 1441: 145 msr mdcr_el3, x0 146 147 /* --------------------------------------------------------------------- 148 * Enable External Aborts and SError Interrupts now that the exception 149 * vectors have been setup. 150 * --------------------------------------------------------------------- 151 */ 152 msr daifclr, #DAIF_ABT_BIT 153 154 /* --------------------------------------------------------------------- 155 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 156 * All fields are architecturally UNKNOWN on reset. 157 * 158 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 159 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 160 * 161 * CPTR_EL3.TTA: Set to one so that accesses to the trace system 162 * registers trap to EL3 from all exception levels and security 163 * states when system register trace is implemented. 164 * When system register trace is not implemented, this bit is RES0 and 165 * hence set to zero. 166 * 167 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 168 * trace registers do not trap to EL3. 169 * 170 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 171 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 172 * do not trap to EL3. 173 * 174 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is 175 * trapped to EL3 by default. 176 * 177 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped 178 * to EL3 by default. 179 * 180 * CPTR_EL3.ESM: Set to zero so that all SME functionality is trapped 181 * to EL3 by default. 182 */ 183 184 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 185 mrs x1, id_aa64dfr0_el1 186 ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH 187 cbz x1, 1f 188 orr x0, x0, #TTA_BIT 1891: 190 msr cptr_el3, x0 191 192 /* 193 * If Data Independent Timing (DIT) functionality is implemented, 194 * always enable DIT in EL3. 195 * First assert that the FEAT_DIT build flag matches the feature id 196 * register value for DIT. 197 */ 198#if ENABLE_FEAT_DIT 199#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1 200 mrs x0, id_aa64pfr0_el1 201 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 202#if ENABLE_FEAT_DIT > 1 203 cbz x0, 1f 204#else 205 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 206 ASM_ASSERT(eq) 207#endif 208 209#endif /* ENABLE_ASSERTIONS */ 210 mov x0, #DIT_BIT 211 msr DIT, x0 2121: 213#endif 214 .endm 215 216/* ----------------------------------------------------------------------------- 217 * This is the super set of actions that need to be performed during a cold boot 218 * or a warm boot in EL3. This code is shared by BL1 and BL31. 219 * 220 * This macro will always perform reset handling, architectural initialisations 221 * and stack setup. The rest of the actions are optional because they might not 222 * be needed, depending on the context in which this macro is called. This is 223 * why this macro is parameterised ; each parameter allows to enable/disable 224 * some actions. 225 * 226 * _init_sctlr: 227 * Whether the macro needs to initialise SCTLR_EL3, including configuring 228 * the endianness of data accesses. 229 * 230 * _warm_boot_mailbox: 231 * Whether the macro needs to detect the type of boot (cold/warm). The 232 * detection is based on the platform entrypoint address : if it is zero 233 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 234 * this macro jumps on the platform entrypoint address. 235 * 236 * _secondary_cold_boot: 237 * Whether the macro needs to identify the CPU that is calling it: primary 238 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 239 * the platform initialisations, while the secondaries will be put in a 240 * platform-specific state in the meantime. 241 * 242 * If the caller knows this macro will only be called by the primary CPU 243 * then this parameter can be defined to 0 to skip this step. 244 * 245 * _init_memory: 246 * Whether the macro needs to initialise the memory. 247 * 248 * _init_c_runtime: 249 * Whether the macro needs to initialise the C runtime environment. 250 * 251 * _exception_vectors: 252 * Address of the exception vectors to program in the VBAR_EL3 register. 253 * 254 * _pie_fixup_size: 255 * Size of memory region to fixup Global Descriptor Table (GDT). 256 * 257 * A non-zero value is expected when firmware needs GDT to be fixed-up. 258 * 259 * ----------------------------------------------------------------------------- 260 */ 261 .macro el3_entrypoint_common \ 262 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 263 _init_memory, _init_c_runtime, _exception_vectors, \ 264 _pie_fixup_size 265 266 .if \_init_sctlr 267 /* ------------------------------------------------------------- 268 * This is the initialisation of SCTLR_EL3 and so must ensure 269 * that all fields are explicitly set rather than relying on hw. 270 * Some fields reset to an IMPLEMENTATION DEFINED value and 271 * others are architecturally UNKNOWN on reset. 272 * 273 * SCTLR.EE: Set the CPU endianness before doing anything that 274 * might involve memory reads or writes. Set to zero to select 275 * Little Endian. 276 * 277 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 278 * force all memory regions that are writeable to be treated as 279 * XN (Execute-never). Set to zero so that this control has no 280 * effect on memory access permissions. 281 * 282 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 283 * 284 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 285 * 286 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 287 * safe behaviour upon exception entry to EL3. 288 * ------------------------------------------------------------- 289 */ 290 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 291 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 292 msr sctlr_el3, x0 293 isb 294 .endif /* _init_sctlr */ 295 296 .if \_warm_boot_mailbox 297 /* ------------------------------------------------------------- 298 * This code will be executed for both warm and cold resets. 299 * Now is the time to distinguish between the two. 300 * Query the platform entrypoint address and if it is not zero 301 * then it means it is a warm boot so jump to this address. 302 * ------------------------------------------------------------- 303 */ 304 bl plat_get_my_entrypoint 305 cbz x0, do_cold_boot 306 br x0 307 308 do_cold_boot: 309 .endif /* _warm_boot_mailbox */ 310 311 .if \_pie_fixup_size 312#if ENABLE_PIE 313 /* 314 * ------------------------------------------------------------ 315 * If PIE is enabled fixup the Global descriptor Table only 316 * once during primary core cold boot path. 317 * 318 * Compile time base address, required for fixup, is calculated 319 * using "pie_fixup" label present within first page. 320 * ------------------------------------------------------------ 321 */ 322 pie_fixup: 323 ldr x0, =pie_fixup 324 and x0, x0, #~(PAGE_SIZE_MASK) 325 mov_imm x1, \_pie_fixup_size 326 add x1, x1, x0 327 bl fixup_gdt_reloc 328#endif /* ENABLE_PIE */ 329 .endif /* _pie_fixup_size */ 330 331 /* --------------------------------------------------------------------- 332 * Set the exception vectors. 333 * --------------------------------------------------------------------- 334 */ 335 adr x0, \_exception_vectors 336 msr vbar_el3, x0 337 isb 338 339#if !(defined(IMAGE_BL2) && ENABLE_RME) 340 /* --------------------------------------------------------------------- 341 * It is a cold boot. 342 * Perform any processor specific actions upon reset e.g. cache, TLB 343 * invalidations etc. 344 * --------------------------------------------------------------------- 345 */ 346 bl reset_handler 347#endif 348 349 el3_arch_init_common 350 351 .if \_secondary_cold_boot 352 /* ------------------------------------------------------------- 353 * Check if this is a primary or secondary CPU cold boot. 354 * The primary CPU will set up the platform while the 355 * secondaries are placed in a platform-specific state until the 356 * primary CPU performs the necessary actions to bring them out 357 * of that state and allows entry into the OS. 358 * ------------------------------------------------------------- 359 */ 360 bl plat_is_my_cpu_primary 361 cbnz w0, do_primary_cold_boot 362 363 /* This is a cold boot on a secondary CPU */ 364 bl plat_secondary_cold_boot_setup 365 /* plat_secondary_cold_boot_setup() is not supposed to return */ 366 bl el3_panic 367 368 do_primary_cold_boot: 369 .endif /* _secondary_cold_boot */ 370 371 /* --------------------------------------------------------------------- 372 * Initialize memory now. Secondary CPU initialization won't get to this 373 * point. 374 * --------------------------------------------------------------------- 375 */ 376 377 .if \_init_memory 378 bl platform_mem_init 379 .endif /* _init_memory */ 380 381 /* --------------------------------------------------------------------- 382 * Init C runtime environment: 383 * - Zero-initialise the NOBITS sections. There are 2 of them: 384 * - the .bss section; 385 * - the coherent memory section (if any). 386 * - Relocate the data section from ROM to RAM, if required. 387 * --------------------------------------------------------------------- 388 */ 389 .if \_init_c_runtime 390#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 391 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 392 /* ------------------------------------------------------------- 393 * Invalidate the RW memory used by the BL31 image. This 394 * includes the data and NOBITS sections. This is done to 395 * safeguard against possible corruption of this memory by 396 * dirty cache lines in a system cache as a result of use by 397 * an earlier boot loader stage. If PIE is enabled however, 398 * RO sections including the GOT may be modified during 399 * pie fixup. Therefore, to be on the safe side, invalidate 400 * the entire image region if PIE is enabled. 401 * ------------------------------------------------------------- 402 */ 403#if ENABLE_PIE 404#if SEPARATE_CODE_AND_RODATA 405 adrp x0, __TEXT_START__ 406 add x0, x0, :lo12:__TEXT_START__ 407#else 408 adrp x0, __RO_START__ 409 add x0, x0, :lo12:__RO_START__ 410#endif /* SEPARATE_CODE_AND_RODATA */ 411#else 412 adrp x0, __RW_START__ 413 add x0, x0, :lo12:__RW_START__ 414#endif /* ENABLE_PIE */ 415 adrp x1, __RW_END__ 416 add x1, x1, :lo12:__RW_END__ 417 sub x1, x1, x0 418 bl inv_dcache_range 419#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 420 adrp x0, __NOBITS_START__ 421 add x0, x0, :lo12:__NOBITS_START__ 422 adrp x1, __NOBITS_END__ 423 add x1, x1, :lo12:__NOBITS_END__ 424 sub x1, x1, x0 425 bl inv_dcache_range 426#endif 427#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 428 adrp x0, __BL2_NOLOAD_START__ 429 add x0, x0, :lo12:__BL2_NOLOAD_START__ 430 adrp x1, __BL2_NOLOAD_END__ 431 add x1, x1, :lo12:__BL2_NOLOAD_END__ 432 sub x1, x1, x0 433 bl inv_dcache_range 434#endif 435#endif 436 adrp x0, __BSS_START__ 437 add x0, x0, :lo12:__BSS_START__ 438 439 adrp x1, __BSS_END__ 440 add x1, x1, :lo12:__BSS_END__ 441 sub x1, x1, x0 442 bl zeromem 443 444#if USE_COHERENT_MEM 445 adrp x0, __COHERENT_RAM_START__ 446 add x0, x0, :lo12:__COHERENT_RAM_START__ 447 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 448 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 449 sub x1, x1, x0 450 bl zeromem 451#endif 452 453#if defined(IMAGE_BL1) || \ 454 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) 455 adrp x0, __DATA_RAM_START__ 456 add x0, x0, :lo12:__DATA_RAM_START__ 457 adrp x1, __DATA_ROM_START__ 458 add x1, x1, :lo12:__DATA_ROM_START__ 459 adrp x2, __DATA_RAM_END__ 460 add x2, x2, :lo12:__DATA_RAM_END__ 461 sub x2, x2, x0 462 bl memcpy16 463#endif 464 .endif /* _init_c_runtime */ 465 466 /* --------------------------------------------------------------------- 467 * Use SP_EL0 for the C runtime stack. 468 * --------------------------------------------------------------------- 469 */ 470 msr spsel, #0 471 472 /* --------------------------------------------------------------------- 473 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 474 * the MMU is enabled. There is no risk of reading stale stack memory 475 * after enabling the MMU as only the primary CPU is running at the 476 * moment. 477 * --------------------------------------------------------------------- 478 */ 479 bl plat_set_my_stack 480 481#if STACK_PROTECTOR_ENABLED 482 .if \_init_c_runtime 483 bl update_stack_protector_canary 484 .endif /* _init_c_runtime */ 485#endif 486 .endm 487 488 .macro apply_at_speculative_wa 489#if ERRATA_SPECULATIVE_AT 490 /* 491 * This function expects x30 has been saved. 492 * Also, save x29 which will be used in the called function. 493 */ 494 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 495 bl save_and_update_ptw_el1_sys_regs 496 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 497#endif 498 .endm 499 500 .macro restore_ptw_el1_sys_regs 501#if ERRATA_SPECULATIVE_AT 502 /* ----------------------------------------------------------- 503 * In case of ERRATA_SPECULATIVE_AT, must follow below order 504 * to ensure that page table walk is not enabled until 505 * restoration of all EL1 system registers. TCR_EL1 register 506 * should be updated at the end which restores previous page 507 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 508 * ensures that CPU does below steps in order. 509 * 510 * 1. Ensure all other system registers are written before 511 * updating SCTLR_EL1 using ISB. 512 * 2. Restore SCTLR_EL1 register. 513 * 3. Ensure SCTLR_EL1 written successfully using ISB. 514 * 4. Restore TCR_EL1 register. 515 * ----------------------------------------------------------- 516 */ 517 isb 518 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 519 msr sctlr_el1, x28 520 isb 521 msr tcr_el1, x29 522#endif 523 .endm 524 525#endif /* EL3_COMMON_MACROS_S */ 526