| 7839a050 | 24-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 4353bb20 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
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|
| ba0248b5 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family |
| ae551a13 | 18-Jul-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
cci: Wait before reading status register
The functions cci_enable_snoop_dvm_reqs and cci_disable_snoop_dvm_reqs write
in the SNOOP_CTRL_REGISTER of the slave interface and it polls the status
regist
cci: Wait before reading status register
The functions cci_enable_snoop_dvm_reqs and cci_disable_snoop_dvm_reqs write
in the SNOOP_CTRL_REGISTER of the slave interface and it polls the status
register to be sure that the operation is finished before leaving the
functions. If the write in SNOOP_CTRL_REGISTER is reordered after the first
read in the status register then these functions can finish before
enabling/disabling snoops and DVM messages.
The CCI500 TRM specifies:
Wait for the completion of the write to the Snoop Control Register
before testing the change_pending bit.
Change-Id: Idc7685963f412be1c16bcd3c6e3cca826e2fdf38
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 255f5c8f | 07-May-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
io: Allow image load to address zero
Remove assert on buffer address equal zero.
Marvell uses address 0x0 for loading BL33,
so this check is irrelevant and breaks the
debug builds on Marvell platfor
io: Allow image load to address zero
Remove assert on buffer address equal zero.
Marvell uses address 0x0 for loading BL33,
so this check is irrelevant and breaks the
debug builds on Marvell platforms.
Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/54589
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|
| f87e9449 | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add i2c driver
Add i2c driver for A8K SoC family.
Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Por
marvell: drivers: Add i2c driver
Add i2c driver for A8K SoC family.
Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| 0ade8cd8 | 24-Apr-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
mvebu: cp110: add COMPHY driver
Add COMPHY driver for usage in a runtime service.
Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off
mvebu: cp110: add COMPHY driver
Add COMPHY driver for usage in a runtime service.
Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| d5a6f86c | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Chang
marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| 152b0e47 | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-of
marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| 031542fc | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add MoChi drivers
Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 a
marvell: drivers: Add MoChi drivers
Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110
Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| c0474d58 | 26-Feb-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
marvell: drivers: Add address decoding units drivers
Add address decoding unit drivers for Marvell SoCs.
Address decoding flow and address translation units chart
are located at docs/marvell/misc/m
marvell: drivers: Add address decoding units drivers
Add address decoding unit drivers for Marvell SoCs.
Address decoding flow and address translation units chart
are located at docs/marvell/misc/mvebu-a8k-addr-map.txt
Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| b19269a6 | 12-Jul-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1432 from Yann-lms/mmc_framework
[RFC] Add MMC framework |
| ad71d45e | 03-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Add MMC framework
This change is largely based on existing eMMC framework by Haojian Zhuang
(@hzhuang1).
The MMC framework supports both eMMC and SD card devices. It was
written as a new framework
Add MMC framework
This change is largely based on existing eMMC framework by Haojian Zhuang
(@hzhuang1).
The MMC framework supports both eMMC and SD card devices. It was
written as a new framework since breaking few eMMC framework APIs.
At card probe and after the reset to idle command (CMD0), a Send
Interface Condition Command is sent (CMD8) to distinguish between
eMMC and SD card devices. eMMC devices go through the same
sequence as in the former eMMC framework. Else the framework
uses commands dedicated to SD-cards for init or frequency switch.
A structure is created to share info with the driver. It stores:
- the MMC type (eMMC, SD or SD HC)
- the device size
- the max frequency supported by the device
- the block size: 512 for eMMC and SD-HC and read from CSD
structure for older SD-cards
Restriction to align buffers on block size has been removed.
Cache maintenance was removed and is expected to be done in the platform
or device driver.
The MMC framework includes some MISRA compliance coding style
maybe not yet ported in the existing eMMC framework.
Fixes ARM-software/tf-issues#597
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| d4d598e9 | 27-Jun-2018 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
Extend FIP io driver to support multiple FIP devices
Platform can define MAX_NUM_FIP_DEVICES in platform_def.h
to define the number of FIP io devices.
The FIP driver doesn't support muliple open fi
Extend FIP io driver to support multiple FIP devices
Platform can define MAX_NUM_FIP_DEVICES in platform_def.h
to define the number of FIP io devices.
The FIP driver doesn't support muliple open file.
So only one single file can be open at a time across
multiple FIP devices.
For any FIP device, an image should be loaded
fully before moving on to the next image.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
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|
| ebce735d | 22-Jun-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1406 from robertovargas-arm/uuid
Make TF UUID RFC 4122 compliant |
| d25b527c | 07-Jun-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Move to mbedtls-2.10.0 tag
To build with the new release, we pick couple of more files from mbedTLS
library.
Change-Id: I77dfe5723284cb26d4e5c717fb0e6f6dd803cb6b
Signed-off-by: Jeenu Viswambharan <
Move to mbedtls-2.10.0 tag
To build with the new release, we pick couple of more files from mbedTLS
library.
Change-Id: I77dfe5723284cb26d4e5c717fb0e6f6dd803cb6b
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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|
| 03364865 | 26-Apr-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Make TF UUID RFC 4122 compliant
RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the f
Make TF UUID RFC 4122 compliant
RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the future UUIDs that are already generated, but we can store
all the bytes using arrays and modify fiptool to generate the UUIDs with
the correct byte order.
Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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|
| ed4cf490 | 13-Jun-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1402 from glneo/for-upstream-uart
drivers: ti: uart: Add TI specific 16550 initialization |
| 896a5902 | 04-May-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Fix MISRA Rule 5.3 Part 2
Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope sh
Fix MISRA Rule 5.3 Part 2
Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make LOG_LEVEL=50 PLAT=fvp
Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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| 87d3aacc | 01-May-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Fix MISRA Rule 5.1
Rule 5.1: External identifiers shall be distinct
Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens th
Fix MISRA Rule 5.1
Rule 5.1: External identifiers shall be distinct
Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.
Fixed for:
LOG_LEVEL=50 PLAT=fvp
Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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| 529b541e | 14-Oct-2016 |
Benjamin Fair <b-fair@ti.com> |
drivers: ti: uart: Add TI specific 16550 initialization
On TI platforms the UART is disabled by default and must be explicitly
enabled using the MDR1 register.
NOTE: The original definition of
http
drivers: ti: uart: Add TI specific 16550 initialization
On TI platforms the UART is disabled by default and must be explicitly
enabled using the MDR1 register.
NOTE: The original definition of
http://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but
many TI SoCs implementing 16550 do have a quirky MDR register
implemented. So, this should be enabled with TI_16550_MDR_QUIRK
NOTE: In such implementation, the CSR register does not exist.
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 0d018306 | 23-May-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1386 from soby-mathew/sm/dyn_bl31
Extend dynamic configuration |
| dcf0bdb6 | 21-May-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1359 from danielboulby-arm/db/match_flags_type
Ensure read and write of flags defined in the console struct are 32 bit |
| 17bc617e | 29-Mar-2018 |
Soby Mathew <soby.mathew@arm.com> |
Dynamic cfg: Enable support on CoT for other configs
This patch implements support for adding dynamic configurations for
BL31 (soc_fw_config), BL32 (tos_fw_config) and BL33 (nt_fw_config). The
neces
Dynamic cfg: Enable support on CoT for other configs
This patch implements support for adding dynamic configurations for
BL31 (soc_fw_config), BL32 (tos_fw_config) and BL33 (nt_fw_config). The
necessary cert tool support and changes to default chain of trust are made
for these configs.
Change-Id: I25f266277b5b5501a196d2f2f79639d838794518
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 8abcdf92 | 16-May-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Ensure read and write of flags are 32 bit
In 'console_set_scope' and when registering a console, field 'flags' of
'console_t' is assigned a 32-bit value. However, when it is actually
used, the funct
Ensure read and write of flags are 32 bit
In 'console_set_scope' and when registering a console, field 'flags' of
'console_t' is assigned a 32-bit value. However, when it is actually
used, the functions perform 64-bit reads to access its value. This patch
changes all 64-bit reads to 32-bit reads.
Change-Id: I181349371409e60065335f078857946fa3c32dc1
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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