| 61752898 | 15-Aug-2018 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
drivers: mmc: Add missing response type for some commands
Add missing response type for SWITCH command and STOP_TRANSMISSION
so that controller can be configured accordingly.
[bod: ported this chan
drivers: mmc: Add missing response type for some commands
Add missing response type for SWITCH command and STOP_TRANSMISSION
so that controller can be configured accordingly.
[bod: ported this change from Jun's eMMC patches to the MMC driver]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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|
| 94522ff7 | 15-Aug-2018 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
drivers: mmc: Fix R3 response type definition
The R3 response type definition should be (1 << 0). Make sure we define the
expected response code in the appropriate fashion.
Signed-off-by: Bryan O'D
drivers: mmc: Fix R3 response type definition
The R3 response type definition should be (1 << 0). Make sure we define the
expected response code in the appropriate fashion.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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|
| 2a82a9c9 | 28-Jun-2018 |
Jun Nie <jun.nie@linaro.org> |
drivers: emmc: dw_mmc: Add response flag into response ID definition
Add response flag into ID definition so that driver does not
need to handle it again.
Signed-off-by: Jun Nie <jun.nie@linaro.org
drivers: emmc: dw_mmc: Add response flag into response ID definition
Add response flag into ID definition so that driver does not
need to handle it again.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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|
| e67606cf | 04-Jul-2018 |
Jun Nie <jun.nie@linaro.org> |
drivers: imx: imx_gpt: Add general purpose timer API binding
Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.
[bod: changed name from imx_delay_ti
drivers: imx: imx_gpt: Add general purpose timer API binding
Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.
[bod: changed name from imx_delay_timer -> imx_gpt ]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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|
| 6d01a463 | 07-Jun-2018 |
John Tsichritzis <john.tsichritzis@arm.com> |
Prepare Mbed TLS drivers for shared heap
The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being acces
Prepare Mbed TLS drivers for shared heap
The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.
Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.
Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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|
| ebf417aa | 04-Sep-2018 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09
Marvell updates 18.09 |
| 349df242 | 30-Jul-2018 |
Marcin Wojtas <mw@semihalf.com> |
marvell: drivers: correct RTC init sequence
It turned out that resetting the RTC time register is not
necessary during initial configuration. Safely remove it
from the sequence.
Change-Id: Id2b9c7d
marvell: drivers: correct RTC init sequence
It turned out that resetting the RTC time register is not
necessary during initial configuration. Safely remove it
from the sequence.
Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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|
| 4acd900d | 21-Mar-2018 |
Marcin Wojtas <mw@semihalf.com> |
gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful t
gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.
Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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|
| 3c0024cc | 16-Jul-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
mvebu: cp110: fix spelling in register definition
Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).
Change-Id:
mvebu: cp110: fix spelling in register definition
Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).
Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
|
| f858e989 | 12-Jul-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
mvebu: cp110: align all comphy_index arguments type
The biggest comphy index can be equal to 6 so there is no need to use
uint64_t for storing it.
Change-Id: I14c2b68e51678a560815963c72aed0c37068f9
mvebu: cp110: align all comphy_index arguments type
The biggest comphy index can be equal to 6 so there is no need to use
uint64_t for storing it.
Change-Id: I14c2b68e51678a560815963c72aed0c37068f926
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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|
| 3a9f8eec | 13-Jun-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: mc_trustzone: add driver for mc trustzone
Add simple driver which allows to configure the memory controller trust
zones. It is responsible for opening mc trustzone window, with
app
drivers: marvell: mc_trustzone: add driver for mc trustzone
Add simple driver which allows to configure the memory controller trust
zones. It is responsible for opening mc trustzone window, with
appropriate base address, size and attributes.
Example of usage in upcoming commits.
Change-Id: I8bea17754d31451b305040ee7de331fb8db0c63f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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|
| 94d6dd67 | 29-Jul-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: rename common include file
Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marve
plat: marvell: rename common include file
Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.
Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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|
| 2ac50020 | 30-Aug-2018 |
Andrew F. Davis <afd@ti.com> |
GIC: Fix build error
Pointers should be comparied to NULL.
Fixes: 3fea9c8b8e8e ("gic: Fix types")
Signed-off-by: Andrew F. Davis <afd@ti.com> |
| 2f5307d6 | 25-May-2018 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
drivers: imx: crash-console: Add a mxc_crash_console driver
This patch does two main things
- It implements the crash console UART init in assembly, as a
hard-coded 115200 8N1 assumed from the 24
drivers: imx: crash-console: Add a mxc_crash_console driver
This patch does two main things
- It implements the crash console UART init in assembly, as a
hard-coded 115200 8N1 assumed from the 24 MHz clock.
If the clock setup code has not run yet, this code can't work but,
setting up clocks and clock-gates is way out of scope for this type of
recovery function.
- It adds code to write a character out of the NXP UART without using any
stack-based operations when doing so.
- Provides support for crash console in DCE or DTE mode.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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|
| 598cee48 | 25-May-2018 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
drivers: imx: uart: Add mxc_console
- Adds a simple register read/write abstraction to cut-down on the
amount of typing and text required to access UART registers in this driver.
- Adds a console
drivers: imx: uart: Add mxc_console
- Adds a simple register read/write abstraction to cut-down on the
amount of typing and text required to access UART registers in this driver.
- Adds a console getc() callback.
- Adds a console putc() callback, translating '\n' to '\r' + '\n'.
- Initializes the MXC UART, take a crude method of calculating the
BAUD rate generator. The UART clock-gates must have been enabled prior
to launching the UART init code.
Special care needs to be taken to ensure the UBIR is initialized before the
UBMR and we need to ensure that UCR2.SRST comes good before trying to
program other registers associated with the UART.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
show more ...
|
| dcf95e7e | 30-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1542 from antonio-nino-diaz-arm/an/bl31-misra
Some MISRA fixes in BL31, cci and smmu |
| 4213e9ba | 23-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
drivers: cci: Fix MISRA defects
Change-Id: Ifdb0ceec19d267b14d796b5d31f08f7342190484
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 6d5f0631 | 21-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
drivers: smmu: Fix MISRA defects
Change-Id: I2954a99d5b72069bcb7bac9d6926c6209d6ba881
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 0117d2ca | 21-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic v3: Fix width of types of helper functions
Change-Id: I08447b44fffb6e54f9fab957eee369ccbda4247a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 3fea9c8b | 21-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic: Fix types
Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 8782922c | 24-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic: Fix definitions
Change-Id: I945029ca26ea2e63f0d92c5f33019b882f23bd72
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| b9f68dfb | 13-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
gic v3: Turn macros into static inline functions
Change-Id: Ib587f12f36810fc7d4f4b8f575195554299b8ed4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 39b6cc66 | 16-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
libc: Use printf and snprintf across codebase
tf_printf and tf_snprintf are now called printf and snprintf, so the
code needs to be updated.
Change-Id: Iffeee97afcd6328c4c2d30830d4923b964682d71
Sig
libc: Use printf and snprintf across codebase
tf_printf and tf_snprintf are now called printf and snprintf, so the
code needs to be updated.
Change-Id: Iffeee97afcd6328c4c2d30830d4923b964682d71
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| b73b60e5 | 17-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1517 from satheesbalya-arm/sb1_2607_mcd_reg
Console: Use callee-saved registers |
| d35cc347 | 31-Jul-2018 |
Sathees Balya <sathees.balya@arm.com> |
Console: Use callee-saved registers
This allows the console drivers to be implemented in C
Change-Id: Ibac859c4bcef0e92a0dcacc6b58ac19bc69b8342
Signed-off-by: Sathees Balya <sathees.balya@arm.com> |