1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <debug.h> 9 #include <platform_def.h> 10 #include <xlat_tables_defs.h> 11 #include <xlat_tables_v2.h> 12 13 #include "xlat_tables_private.h" 14 15 /* 16 * MMU configuration register values for the active translation context. Used 17 * from the MMU assembly helpers. 18 */ 19 uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; 20 21 /* 22 * Allocate and initialise the default translation context for the BL image 23 * currently executing. 24 */ 25 REGISTER_XLAT_CONTEXT(tf, MAX_MMAP_REGIONS, MAX_XLAT_TABLES, 26 PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE); 27 28 void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, size_t size, 29 unsigned int attr) 30 { 31 mmap_region_t mm = MAP_REGION(base_pa, base_va, size, attr); 32 33 mmap_add_region_ctx(&tf_xlat_ctx, &mm); 34 } 35 36 void mmap_add(const mmap_region_t *mm) 37 { 38 mmap_add_ctx(&tf_xlat_ctx, mm); 39 } 40 41 #if PLAT_XLAT_TABLES_DYNAMIC 42 43 int mmap_add_dynamic_region(unsigned long long base_pa, uintptr_t base_va, 44 size_t size, unsigned int attr) 45 { 46 mmap_region_t mm = MAP_REGION(base_pa, base_va, size, attr); 47 48 return mmap_add_dynamic_region_ctx(&tf_xlat_ctx, &mm); 49 } 50 51 int mmap_remove_dynamic_region(uintptr_t base_va, size_t size) 52 { 53 return mmap_remove_dynamic_region_ctx(&tf_xlat_ctx, 54 base_va, size); 55 } 56 57 #endif /* PLAT_XLAT_TABLES_DYNAMIC */ 58 59 void init_xlat_tables(void) 60 { 61 assert(tf_xlat_ctx.xlat_regime == EL_REGIME_INVALID); 62 63 unsigned int current_el = xlat_arch_current_el(); 64 65 if (current_el == 1U) { 66 tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME; 67 } else if (current_el == 2U) { 68 tf_xlat_ctx.xlat_regime = EL2_REGIME; 69 } else { 70 assert(current_el == 3U); 71 tf_xlat_ctx.xlat_regime = EL3_REGIME; 72 } 73 74 init_xlat_tables_ctx(&tf_xlat_ctx); 75 } 76 77 int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr) 78 { 79 return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr); 80 } 81 82 int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr) 83 { 84 return xlat_change_mem_attributes_ctx(&tf_xlat_ctx, base_va, size, attr); 85 } 86 87 /* 88 * If dynamic allocation of new regions is disabled then by the time we call the 89 * function enabling the MMU, we'll have registered all the memory regions to 90 * map for the system's lifetime. Therefore, at this point we know the maximum 91 * physical address that will ever be mapped. 92 * 93 * If dynamic allocation is enabled then we can't make any such assumption 94 * because the maximum physical address could get pushed while adding a new 95 * region. Therefore, in this case we have to assume that the whole address 96 * space size might be mapped. 97 */ 98 #ifdef PLAT_XLAT_TABLES_DYNAMIC 99 #define MAX_PHYS_ADDR tf_xlat_ctx.pa_max_address 100 #else 101 #define MAX_PHYS_ADDR tf_xlat_ctx.max_pa 102 #endif 103 104 #ifdef AARCH32 105 106 void enable_mmu_svc_mon(unsigned int flags) 107 { 108 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, 109 tf_xlat_ctx.base_table, MAX_PHYS_ADDR, 110 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); 111 enable_mmu_direct_svc_mon(flags); 112 } 113 114 void enable_mmu_hyp(unsigned int flags) 115 { 116 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, 117 tf_xlat_ctx.base_table, MAX_PHYS_ADDR, 118 tf_xlat_ctx.va_max_address, EL2_REGIME); 119 enable_mmu_direct_hyp(flags); 120 } 121 122 #else 123 124 void enable_mmu_el1(unsigned int flags) 125 { 126 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, 127 tf_xlat_ctx.base_table, MAX_PHYS_ADDR, 128 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); 129 enable_mmu_direct_el1(flags); 130 } 131 132 void enable_mmu_el2(unsigned int flags) 133 { 134 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, 135 tf_xlat_ctx.base_table, MAX_PHYS_ADDR, 136 tf_xlat_ctx.va_max_address, EL2_REGIME); 137 enable_mmu_direct_el2(flags); 138 } 139 140 void enable_mmu_el3(unsigned int flags) 141 { 142 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags, 143 tf_xlat_ctx.base_table, MAX_PHYS_ADDR, 144 tf_xlat_ctx.va_max_address, EL3_REGIME); 145 enable_mmu_direct_el3(flags); 146 } 147 148 #endif /* AARCH32 */ 149