| d8e666a3 | 11-Mar-2019 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
rcar_gen3: drivers: qos: change subslot cycle
Subslot cycle from 132 to 126 as default setting.
Subslot cycle from 264 to 252.
[IPL/QoS]
- Update H3 Ver.2.0 QoS setting rev.0.21.
- Update H3 Ver
rcar_gen3: drivers: qos: change subslot cycle
Subslot cycle from 132 to 126 as default setting.
Subslot cycle from 264 to 252.
[IPL/QoS]
- Update H3 Ver.2.0 QoS setting rev.0.21.
- Update H3 Ver.3.0 QoS setting rev.0.11.
- Update M3 Ver.1.1 QoS setting rev.0.19.
- Update M3 Ver.3.0 QoS setting rev.0.02.
- Update M3N Ver.1.1 QoS setting rev.0.09.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
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|
| 8c715587 | 11-Mar-2019 |
Yusuke Goda <yusuke.goda.sx@renesas.com> |
rcar_gen3: drivers: board: Add new board revision for H3ULCB
Board Revision[2:0]
3'b000 Rev1.0 OB
3'b001 Rev1.0 CE
3'b010 Rev2.0 [New]
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cha
rcar_gen3: drivers: board: Add new board revision for H3ULCB
Board Revision[2:0]
3'b000 Rev1.0 OB
3'b001 Rev1.0 CE
3'b010 Rev2.0 [New]
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
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|
| 7a246d64 | 09-Apr-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Checkpatch: Style fix
Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> |
| 30070427 | 11-Mar-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
cot-desc: optimise memory further
This changes the auth_img_desc_t struct to have pointers to struct
arrays instead of struct arrays. This saves memory as many of these
were never used, and can be N
cot-desc: optimise memory further
This changes the auth_img_desc_t struct to have pointers to struct
arrays instead of struct arrays. This saves memory as many of these
were never used, and can be NULL pointers. Note the memory savings are
only when these arrays are not initialised, as it is assumed these
arrays are fixed length. A possible future optimisation could allow for
variable length.
memory diff:
bl1: bl2:
text text
-12 -12
bss bss
-1463 0
data data
-56 -48
rodata rodata
-5688 -2592
total total
-7419 -2652
Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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|
| 0b6377d1 | 20-Feb-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Reduce memory needed for CoT description
When Trusted Board Boot is enabled, we need to specify the Chain of
Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array
of image descriptors. T
Reduce memory needed for CoT description
When Trusted Board Boot is enabled, we need to specify the Chain of
Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array
of image descriptors. The authentication module assumes that each
image descriptor in this array is indexed by its unique image
identifier. For example, the Trusted Boot Firmware Certificate has to
be at index [TRUSTED_BOOT_FW_CERT_ID].
Unique image identifiers may not necessarily be consecutive. Also,
a given BL image might not use all image descriptors. For example, BL1
does not need any of the descriptors related to BL31. As a result, the
CoT array might contain holes, which unnecessarily takes up space in
the BL binary.
Using pointers to auth_img_desc_t structs (rather than structs
themselves) means these unused elements only use 1 pointer worth of
space, rather than one struct worth of space. This patch also changes
the code which accesses this array to reflect the change to pointers.
Image descriptors not needed in BL1 or BL2 respectively are also
ifdef'd out in this patch. For example, verifying the BL31 image is
the responsibility of BL2 so BL1 does not need any of the data
structures describing BL31.
memory diff:
bl1: bl2:
text text
-20 -20
bss bss
-1463 0
data data
-256 -48
rodata rodata
-5240 -1952
total total
-6979 -2020
Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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|
| 6e756f6d | 28-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Makefile: remove extra include paths in INCLUDES
Now it is needed to use the full path of the common header files.
Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
informatio
Makefile: remove extra include paths in INCLUDES
Now it is needed to use the full path of the common header files.
Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
information.
Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| cc69cfd2 | 27-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
tzc: remove deprecated types
Types tzc_action_t and tzc_region_attributes_t are deprecated.
Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773
Signed-off-by: Ambroise Vincent <ambroise.vincent@ar
tzc: remove deprecated types
Types tzc_action_t and tzc_region_attributes_t are deprecated.
Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| be3991c0 | 27-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Console: remove deprecated finish_console_register
The old version of the macro is deprecated.
Commit cc5859ca19ff ("Multi-console: Deprecate the
`finish_console_register` macro") provides more det
Console: remove deprecated finish_console_register
The old version of the macro is deprecated.
Commit cc5859ca19ff ("Multi-console: Deprecate the
`finish_console_register` macro") provides more details.
Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| 682c307d | 03-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1917 from marex/arm/master/v3meagle-v2.0.1
rcar_gen3: plat: Add R-Car V3M support |
| b99f9224 | 28-Mar-2019 |
Remi Pommarel <repk@triplefau.lt> |
meson/gxl: Add support for SHA256 DMA engine
In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility th
meson/gxl: Add support for SHA256 DMA engine
In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility that could be used to offload SHA-256
computations. This adds basic support of this hardware SHA-256
engine.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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|
| b709fe9c | 29-Oct-2018 |
Valentine Barshak <valentine.barshak@cogentembedded.com> |
rcar_gen3: plat: Add R-Car V3M support
Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barino
rcar_gen3: plat: Add R-Car V3M support
Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---
Marek: Update on top of mainline ATF/master
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|
| 15652ec3 | 14-Jun-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: Add D3 QoS tables
Add QoS tables for R-Car D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
| b645d22b | 14-Jun-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: pfc: Add D3 PFC tables
Add PFC tables for R-Car D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
| b60b9b5a | 14-Jun-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: ddr_a: Add D3 DDR init
Add R-Car D3 DDR initialization code. The code is in staging and needs
cleanup, and possibly can even be merged with the E3 init code.
Signed-off-by: Mare
rcar_gen3: drivers: ddr_a: Add D3 DDR init
Add R-Car D3 DDR initialization code. The code is in staging and needs
cleanup, and possibly can even be merged with the E3 init code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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|
| cdea546d | 05-Jan-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: swdt: Add D3 support
Add WTCNT register configuration for the D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
| ada66133 | 05-Jan-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: scif: Add D3 support
Add SCIF configuration specifics for the D3 SoC, that is detection
of the D3 SoC and SCBRR configuration.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gm
rcar_gen3: drivers: scif: Add D3 support
Add SCIF configuration specifics for the D3 SoC, that is detection
of the D3 SoC and SCBRR configuration.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
show more ...
|
| 5c1d5357 | 05-Jan-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: pwrc: Add D3 support
The D3 SoC has one CPU core, just return 1 as a CPU number.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
| 90ff8ba6 | 05-Jan-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: rom: Mark NEW table as D3 compatible
Add comment into the ROM driver that the new table is also D3 compatible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
| bfbf5df4 | 05-Jan-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: plat: Add initial D3 support
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code
will be added separately.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
| bde2836f | 14-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn in
Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed.
Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| 609e053c | 13-Feb-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which
Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed without heavy
structural changes.
Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
show more ...
|
| 2baa7270 | 22-Mar-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
driver: synosys: Fix SD MMC not initializing correctly
dw_params.mmc_dev_type should be assigned before mmc_init, otherwise SDMMC
initialization will fail as the initialization treats the device as
driver: synosys: Fix SD MMC not initializing correctly
dw_params.mmc_dev_type should be assigned before mmc_init, otherwise SDMMC
initialization will fail as the initialization treats the device as EMMC
instead of SD.
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
show more ...
|
| b79239db | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1879 from pbeesley-arm/pb/todo-removal
Pb/todo removal |
| c61a807a | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1874 from hadi-asyrafi/qspi_boot
intel: QSPI boot enablement |
| 77913d44 | 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1858 from thloh85-intel/dwmmc_fixes
drivers: synopsys: Fix synopsys MMC driver |