1/* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <neoverse_e1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24func neoverse_e1_cpu_pwr_dwn 25 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 26 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 27 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 28 isb 29 ret 30endfunc neoverse_e1_cpu_pwr_dwn 31 32#if REPORT_ERRATA 33/* 34 * Errata printing function for Neoverse N1. Must follow AAPCS. 35 */ 36func neoverse_e1_errata_report 37 ret 38endfunc neoverse_e1_errata_report 39#endif 40 41 42.section .rodata.neoverse_e1_regs, "aS" 43neoverse_e1_regs: /* The ascii list of register names to be reported */ 44 .asciz "cpuectlr_el1", "" 45 46func neoverse_e1_cpu_reg_dump 47 adr x6, neoverse_e1_regs 48 mrs x8, NEOVERSE_E1_ECTLR_EL1 49 ret 50endfunc neoverse_e1_cpu_reg_dump 51 52declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 53 CPU_NO_RESET_FUNC, \ 54 neoverse_e1_cpu_pwr_dwn 55