1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Porting Trusted Firmware-A (TF-A) to a new platform involves making some 16mandatory and optional modifications for both the cold and warm boot paths. 17Modifications consist of: 18 19- Implementing a platform-specific function or variable, 20- Setting up the execution context in a certain way, or 21- Defining certain constants (for example #defines). 22 23The platform-specific functions and variables are declared in 24`include/plat/common/platform.h`_. The firmware provides a default implementation 25of variables and functions to fulfill the optional requirements. These 26implementations are all weakly defined; they are provided to ease the porting 27effort. Each platform port can override them with its own implementation if the 28default implementation is inadequate. 29 30Some modifications are common to all Boot Loader (BL) stages. Section 2 31discusses these in detail. The subsequent sections discuss the remaining 32modifications for each BL stage in detail. 33 34This document should be read in conjunction with the TF-A `User Guide`_. 35 36Please refer to the `Platform compatibility policy`_ for the policy regarding 37compatibility and deprecation of these porting interfaces. 38 39Only Arm development platforms (such as FVP and Juno) may use the 40functions/definitions in ``include/plat/arm/common/`` and the corresponding 41source files in ``plat/arm/common/``. This is done so that there are no 42dependencies between platforms maintained by different people/companies. If you 43want to use any of the functionality present in ``plat/arm`` files, please 44create a pull request that moves the code to ``plat/common`` so that it can be 45discussed. 46 47Common modifications 48-------------------- 49 50This section covers the modifications that should be made by the platform for 51each BL stage to correctly port the firmware stack. They are categorized as 52either mandatory or optional. 53 54Common mandatory modifications 55------------------------------ 56 57A platform port must enable the Memory Management Unit (MMU) as well as the 58instruction and data caches for each BL stage. Setting up the translation 59tables is the responsibility of the platform port because memory maps differ 60across platforms. A memory translation library (see ``lib/xlat_tables/``) is 61provided to help in this setup. 62 63Note that although this library supports non-identity mappings, this is intended 64only for re-mapping peripheral physical addresses and allows platforms with high 65I/O addresses to reduce their virtual address space. All other addresses 66corresponding to code and data must currently use an identity mapping. 67 68Also, the only translation granule size supported in TF-A is 4KB, as various 69parts of the code assume that is the case. It is not possible to switch to 7016 KB or 64 KB granule sizes at the moment. 71 72In Arm standard platforms, each BL stage configures the MMU in the 73platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 74an identity mapping for all addresses. 75 76If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 77block of identity mapped secure memory with Device-nGnRE attributes aligned to 78page boundary (4K) for each BL stage. All sections which allocate coherent 79memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 80section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 81possible for the firmware to place variables in it using the following C code 82directive: 83 84:: 85 86 __section("bakery_lock") 87 88Or alternatively the following assembler code directive: 89 90:: 91 92 .section bakery_lock 93 94The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 95used to allocate any data structures that are accessed both when a CPU is 96executing with its MMU and caches enabled, and when it's running with its MMU 97and caches disabled. Examples are given below. 98 99The following variables, functions and constants must be defined by the platform 100for the firmware to work correctly. 101 102File : platform_def.h [mandatory] 103~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 104 105Each platform must ensure that a header file of this name is in the system 106include path with the following constants defined. This will require updating 107the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 108 109Platform ports may optionally use the file `include/plat/common/common_def.h`_, 110which provides typical values for some of the constants below. These values are 111likely to be suitable for all platform ports. 112 113- **#define : PLATFORM_LINKER_FORMAT** 114 115 Defines the linker format used by the platform, for example 116 ``elf64-littleaarch64``. 117 118- **#define : PLATFORM_LINKER_ARCH** 119 120 Defines the processor architecture for the linker by the platform, for 121 example ``aarch64``. 122 123- **#define : PLATFORM_STACK_SIZE** 124 125 Defines the normal stack memory available to each CPU. This constant is used 126 by `plat/common/aarch64/platform_mp_stack.S`_ and 127 `plat/common/aarch64/platform_up_stack.S`_. 128 129- **define : CACHE_WRITEBACK_GRANULE** 130 131 Defines the size in bits of the largest cache line across all the cache 132 levels in the platform. 133 134- **#define : FIRMWARE_WELCOME_STR** 135 136 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 137 function. 138 139- **#define : PLATFORM_CORE_COUNT** 140 141 Defines the total number of CPUs implemented by the platform across all 142 clusters in the system. 143 144- **#define : PLAT_NUM_PWR_DOMAINS** 145 146 Defines the total number of nodes in the power domain topology 147 tree at all the power domain levels used by the platform. 148 This macro is used by the PSCI implementation to allocate 149 data structures to represent power domain topology. 150 151- **#define : PLAT_MAX_PWR_LVL** 152 153 Defines the maximum power domain level that the power management operations 154 should apply to. More often, but not always, the power domain level 155 corresponds to affinity level. This macro allows the PSCI implementation 156 to know the highest power domain level that it should consider for power 157 management operations in the system that the platform implements. For 158 example, the Base AEM FVP implements two clusters with a configurable 159 number of CPUs and it reports the maximum power domain level as 1. 160 161- **#define : PLAT_MAX_OFF_STATE** 162 163 Defines the local power state corresponding to the deepest power down 164 possible at every power domain level in the platform. The local power 165 states for each level may be sparsely allocated between 0 and this value 166 with 0 being reserved for the RUN state. The PSCI implementation uses this 167 value to initialize the local power states of the power domain nodes and 168 to specify the requested power state for a PSCI_CPU_OFF call. 169 170- **#define : PLAT_MAX_RET_STATE** 171 172 Defines the local power state corresponding to the deepest retention state 173 possible at every power domain level in the platform. This macro should be 174 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 175 PSCI implementation to distinguish between retention and power down local 176 power states within PSCI_CPU_SUSPEND call. 177 178- **#define : PLAT_MAX_PWR_LVL_STATES** 179 180 Defines the maximum number of local power states per power domain level 181 that the platform supports. The default value of this macro is 2 since 182 most platforms just support a maximum of two local power states at each 183 power domain level (power-down and retention). If the platform needs to 184 account for more local power states, then it must redefine this macro. 185 186 Currently, this macro is used by the Generic PSCI implementation to size 187 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 188 189- **#define : BL1_RO_BASE** 190 191 Defines the base address in secure ROM where BL1 originally lives. Must be 192 aligned on a page-size boundary. 193 194- **#define : BL1_RO_LIMIT** 195 196 Defines the maximum address in secure ROM that BL1's actual content (i.e. 197 excluding any data section allocated at runtime) can occupy. 198 199- **#define : BL1_RW_BASE** 200 201 Defines the base address in secure RAM where BL1's read-write data will live 202 at runtime. Must be aligned on a page-size boundary. 203 204- **#define : BL1_RW_LIMIT** 205 206 Defines the maximum address in secure RAM that BL1's read-write data can 207 occupy at runtime. 208 209- **#define : BL2_BASE** 210 211 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 212 Must be aligned on a page-size boundary. This constant is not applicable 213 when BL2_IN_XIP_MEM is set to '1'. 214 215- **#define : BL2_LIMIT** 216 217 Defines the maximum address in secure RAM that the BL2 image can occupy. 218 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 219 220- **#define : BL2_RO_BASE** 221 222 Defines the base address in secure XIP memory where BL2 RO section originally 223 lives. Must be aligned on a page-size boundary. This constant is only needed 224 when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_LIMIT** 227 228 Defines the maximum address in secure XIP memory that BL2's actual content 229 (i.e. excluding any data section allocated at runtime) can occupy. This 230 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RW_BASE** 233 234 Defines the base address in secure RAM where BL2's read-write data will live 235 at runtime. Must be aligned on a page-size boundary. This constant is only 236 needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_LIMIT** 239 240 Defines the maximum address in secure RAM that BL2's read-write data can 241 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 242 to '1'. 243 244- **#define : BL31_BASE** 245 246 Defines the base address in secure RAM where BL2 loads the BL31 binary 247 image. Must be aligned on a page-size boundary. 248 249- **#define : BL31_LIMIT** 250 251 Defines the maximum address in secure RAM that the BL31 image can occupy. 252 253For every image, the platform must define individual identifiers that will be 254used by BL1 or BL2 to load the corresponding image into memory from non-volatile 255storage. For the sake of performance, integer numbers will be used as 256identifiers. The platform will use those identifiers to return the relevant 257information about the image to be loaded (file handler, load address, 258authentication information, etc.). The following image identifiers are 259mandatory: 260 261- **#define : BL2_IMAGE_ID** 262 263 BL2 image identifier, used by BL1 to load BL2. 264 265- **#define : BL31_IMAGE_ID** 266 267 BL31 image identifier, used by BL2 to load BL31. 268 269- **#define : BL33_IMAGE_ID** 270 271 BL33 image identifier, used by BL2 to load BL33. 272 273If Trusted Board Boot is enabled, the following certificate identifiers must 274also be defined: 275 276- **#define : TRUSTED_BOOT_FW_CERT_ID** 277 278 BL2 content certificate identifier, used by BL1 to load the BL2 content 279 certificate. 280 281- **#define : TRUSTED_KEY_CERT_ID** 282 283 Trusted key certificate identifier, used by BL2 to load the trusted key 284 certificate. 285 286- **#define : SOC_FW_KEY_CERT_ID** 287 288 BL31 key certificate identifier, used by BL2 to load the BL31 key 289 certificate. 290 291- **#define : SOC_FW_CONTENT_CERT_ID** 292 293 BL31 content certificate identifier, used by BL2 to load the BL31 content 294 certificate. 295 296- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 297 298 BL33 key certificate identifier, used by BL2 to load the BL33 key 299 certificate. 300 301- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 302 303 BL33 content certificate identifier, used by BL2 to load the BL33 content 304 certificate. 305 306- **#define : FWU_CERT_ID** 307 308 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 309 FWU content certificate. 310 311- **#define : PLAT_CRYPTOCELL_BASE** 312 313 This defines the base address of Arm® TrustZone® CryptoCell and must be 314 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 315 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 316 set. 317 318If the AP Firmware Updater Configuration image, BL2U is used, the following 319must also be defined: 320 321- **#define : BL2U_BASE** 322 323 Defines the base address in secure memory where BL1 copies the BL2U binary 324 image. Must be aligned on a page-size boundary. 325 326- **#define : BL2U_LIMIT** 327 328 Defines the maximum address in secure memory that the BL2U image can occupy. 329 330- **#define : BL2U_IMAGE_ID** 331 332 BL2U image identifier, used by BL1 to fetch an image descriptor 333 corresponding to BL2U. 334 335If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 336must also be defined: 337 338- **#define : SCP_BL2U_IMAGE_ID** 339 340 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 341 corresponding to SCP_BL2U. 342 NOTE: TF-A does not provide source code for this image. 343 344If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 345also be defined: 346 347- **#define : NS_BL1U_BASE** 348 349 Defines the base address in non-secure ROM where NS_BL1U executes. 350 Must be aligned on a page-size boundary. 351 NOTE: TF-A does not provide source code for this image. 352 353- **#define : NS_BL1U_IMAGE_ID** 354 355 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 356 corresponding to NS_BL1U. 357 358If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 359be defined: 360 361- **#define : NS_BL2U_BASE** 362 363 Defines the base address in non-secure memory where NS_BL2U executes. 364 Must be aligned on a page-size boundary. 365 NOTE: TF-A does not provide source code for this image. 366 367- **#define : NS_BL2U_IMAGE_ID** 368 369 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 370 corresponding to NS_BL2U. 371 372For the the Firmware update capability of TRUSTED BOARD BOOT, the following 373macros may also be defined: 374 375- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 376 377 Total number of images that can be loaded simultaneously. If the platform 378 doesn't specify any value, it defaults to 10. 379 380If a SCP_BL2 image is supported by the platform, the following constants must 381also be defined: 382 383- **#define : SCP_BL2_IMAGE_ID** 384 385 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 386 from platform storage before being transferred to the SCP. 387 388- **#define : SCP_FW_KEY_CERT_ID** 389 390 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 391 certificate (mandatory when Trusted Board Boot is enabled). 392 393- **#define : SCP_FW_CONTENT_CERT_ID** 394 395 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 396 content certificate (mandatory when Trusted Board Boot is enabled). 397 398If a BL32 image is supported by the platform, the following constants must 399also be defined: 400 401- **#define : BL32_IMAGE_ID** 402 403 BL32 image identifier, used by BL2 to load BL32. 404 405- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 406 407 BL32 key certificate identifier, used by BL2 to load the BL32 key 408 certificate (mandatory when Trusted Board Boot is enabled). 409 410- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 411 412 BL32 content certificate identifier, used by BL2 to load the BL32 content 413 certificate (mandatory when Trusted Board Boot is enabled). 414 415- **#define : BL32_BASE** 416 417 Defines the base address in secure memory where BL2 loads the BL32 binary 418 image. Must be aligned on a page-size boundary. 419 420- **#define : BL32_LIMIT** 421 422 Defines the maximum address that the BL32 image can occupy. 423 424If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 425platform, the following constants must also be defined: 426 427- **#define : TSP_SEC_MEM_BASE** 428 429 Defines the base address of the secure memory used by the TSP image on the 430 platform. This must be at the same address or below ``BL32_BASE``. 431 432- **#define : TSP_SEC_MEM_SIZE** 433 434 Defines the size of the secure memory used by the BL32 image on the 435 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 436 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 437 and ``BL32_LIMIT``. 438 439- **#define : TSP_IRQ_SEC_PHY_TIMER** 440 441 Defines the ID of the secure physical generic timer interrupt used by the 442 TSP's interrupt handling code. 443 444If the platform port uses the translation table library code, the following 445constants must also be defined: 446 447- **#define : PLAT_XLAT_TABLES_DYNAMIC** 448 449 Optional flag that can be set per-image to enable the dynamic allocation of 450 regions even when the MMU is enabled. If not defined, only static 451 functionality will be available, if defined and set to 1 it will also 452 include the dynamic functionality. 453 454- **#define : MAX_XLAT_TABLES** 455 456 Defines the maximum number of translation tables that are allocated by the 457 translation table library code. To minimize the amount of runtime memory 458 used, choose the smallest value needed to map the required virtual addresses 459 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 460 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 461 as well. 462 463- **#define : MAX_MMAP_REGIONS** 464 465 Defines the maximum number of regions that are allocated by the translation 466 table library code. A region consists of physical base address, virtual base 467 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 468 defined in the ``mmap_region_t`` structure. The platform defines the regions 469 that should be mapped. Then, the translation table library will create the 470 corresponding tables and descriptors at runtime. To minimize the amount of 471 runtime memory used, choose the smallest value needed to register the 472 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 473 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 474 the dynamic regions as well. 475 476- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 477 478 Defines the total size of the virtual address space in bytes. For example, 479 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 480 481- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 482 483 Defines the total size of the physical address space in bytes. For example, 484 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 485 486If the platform port uses the IO storage framework, the following constants 487must also be defined: 488 489- **#define : MAX_IO_DEVICES** 490 491 Defines the maximum number of registered IO devices. Attempting to register 492 more devices than this value using ``io_register_device()`` will fail with 493 -ENOMEM. 494 495- **#define : MAX_IO_HANDLES** 496 497 Defines the maximum number of open IO handles. Attempting to open more IO 498 entities than this value using ``io_open()`` will fail with -ENOMEM. 499 500- **#define : MAX_IO_BLOCK_DEVICES** 501 502 Defines the maximum number of registered IO block devices. Attempting to 503 register more devices this value using ``io_dev_open()`` will fail 504 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 505 With this macro, multiple block devices could be supported at the same 506 time. 507 508If the platform needs to allocate data within the per-cpu data framework in 509BL31, it should define the following macro. Currently this is only required if 510the platform decides not to use the coherent memory section by undefining the 511``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 512required memory within the the per-cpu data to minimize wastage. 513 514- **#define : PLAT_PCPU_DATA_SIZE** 515 516 Defines the memory (in bytes) to be reserved within the per-cpu data 517 structure for use by the platform layer. 518 519The following constants are optional. They should be defined when the platform 520memory layout implies some image overlaying like in Arm standard platforms. 521 522- **#define : BL31_PROGBITS_LIMIT** 523 524 Defines the maximum address in secure RAM that the BL31's progbits sections 525 can occupy. 526 527- **#define : TSP_PROGBITS_LIMIT** 528 529 Defines the maximum address that the TSP's progbits sections can occupy. 530 531If the platform port uses the PL061 GPIO driver, the following constant may 532optionally be defined: 533 534- **PLAT_PL061_MAX_GPIOS** 535 Maximum number of GPIOs required by the platform. This allows control how 536 much memory is allocated for PL061 GPIO controllers. The default value is 537 538 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 539 540If the platform port uses the partition driver, the following constant may 541optionally be defined: 542 543- **PLAT_PARTITION_MAX_ENTRIES** 544 Maximum number of partition entries required by the platform. This allows 545 control how much memory is allocated for partition entries. The default 546 value is 128. 547 `For example, define the build flag in platform.mk`_: 548 PLAT_PARTITION_MAX_ENTRIES := 12 549 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 550 551The following constant is optional. It should be defined to override the default 552behaviour of the ``assert()`` function (for example, to save memory). 553 554- **PLAT_LOG_LEVEL_ASSERT** 555 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 556 ``assert()`` prints the name of the file, the line number and the asserted 557 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 558 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 559 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 560 defined, it defaults to ``LOG_LEVEL``. 561 562If the platform port uses the Activity Monitor Unit, the following constants 563may be defined: 564 565- **PLAT_AMU_GROUP1_COUNTERS_MASK** 566 This mask reflects the set of group counters that should be enabled. The 567 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 568 can be at most 0xffff. If the platform does not define this mask, no group 1 569 counters are enabled. If the platform defines this mask, the following 570 constant needs to also be defined. 571 572- **PLAT_AMU_GROUP1_NR_COUNTERS** 573 This value is used to allocate an array to save and restore the counters 574 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 575 This value should be equal to the highest bit position set in the 576 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 577 578File : plat_macros.S [mandatory] 579~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 580 581Each platform must ensure a file of this name is in the system include path with 582the following macro defined. In the Arm development platforms, this file is 583found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 584 585- **Macro : plat_crash_print_regs** 586 587 This macro allows the crash reporting routine to print relevant platform 588 registers in case of an unhandled exception in BL31. This aids in debugging 589 and this macro can be defined to be empty in case register reporting is not 590 desired. 591 592 For instance, GIC or interconnect registers may be helpful for 593 troubleshooting. 594 595Handling Reset 596-------------- 597 598BL1 by default implements the reset vector where execution starts from a cold 599or warm boot. BL31 can be optionally set as a reset vector using the 600``RESET_TO_BL31`` make variable. 601 602For each CPU, the reset vector code is responsible for the following tasks: 603 604#. Distinguishing between a cold boot and a warm boot. 605 606#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 607 the CPU is placed in a platform-specific state until the primary CPU 608 performs the necessary steps to remove it from this state. 609 610#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 611 specific address in the BL31 image in the same processor mode as it was 612 when released from reset. 613 614The following functions need to be implemented by the platform port to enable 615reset vector code to perform the above tasks. 616 617Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 618~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 619 620:: 621 622 Argument : void 623 Return : uintptr_t 624 625This function is called with the MMU and caches disabled 626(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 627distinguishing between a warm and cold reset for the current CPU using 628platform-specific means. If it's a warm reset, then it returns the warm 629reset entrypoint point provided to ``plat_setup_psci_ops()`` during 630BL31 initialization. If it's a cold reset then this function must return zero. 631 632This function does not follow the Procedure Call Standard used by the 633Application Binary Interface for the Arm 64-bit architecture. The caller should 634not assume that callee saved registers are preserved across a call to this 635function. 636 637This function fulfills requirement 1 and 3 listed above. 638 639Note that for platforms that support programming the reset address, it is 640expected that a CPU will start executing code directly at the right address, 641both on a cold and warm reset. In this case, there is no need to identify the 642type of reset nor to query the warm reset entrypoint. Therefore, implementing 643this function is not required on such platforms. 644 645Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 646~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 647 648:: 649 650 Argument : void 651 652This function is called with the MMU and data caches disabled. It is responsible 653for placing the executing secondary CPU in a platform-specific state until the 654primary CPU performs the necessary actions to bring it out of that state and 655allow entry into the OS. This function must not return. 656 657In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 658itself off. The primary CPU is responsible for powering up the secondary CPUs 659when normal world software requires them. When booting an EL3 payload instead, 660they stay powered on and are put in a holding pen until their mailbox gets 661populated. 662 663This function fulfills requirement 2 above. 664 665Note that for platforms that can't release secondary CPUs out of reset, only the 666primary CPU will execute the cold boot code. Therefore, implementing this 667function is not required on such platforms. 668 669Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 670~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 671 672:: 673 674 Argument : void 675 Return : unsigned int 676 677This function identifies whether the current CPU is the primary CPU or a 678secondary CPU. A return value of zero indicates that the CPU is not the 679primary CPU, while a non-zero return value indicates that the CPU is the 680primary CPU. 681 682Note that for platforms that can't release secondary CPUs out of reset, only the 683primary CPU will execute the cold boot code. Therefore, there is no need to 684distinguish between primary and secondary CPUs and implementing this function is 685not required. 686 687Function : platform_mem_init() [mandatory] 688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 689 690:: 691 692 Argument : void 693 Return : void 694 695This function is called before any access to data is made by the firmware, in 696order to carry out any essential memory initialization. 697 698Function: plat_get_rotpk_info() 699~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 700 701:: 702 703 Argument : void *, void **, unsigned int *, unsigned int * 704 Return : int 705 706This function is mandatory when Trusted Board Boot is enabled. It returns a 707pointer to the ROTPK stored in the platform (or a hash of it) and its length. 708The ROTPK must be encoded in DER format according to the following ASN.1 709structure: 710 711:: 712 713 AlgorithmIdentifier ::= SEQUENCE { 714 algorithm OBJECT IDENTIFIER, 715 parameters ANY DEFINED BY algorithm OPTIONAL 716 } 717 718 SubjectPublicKeyInfo ::= SEQUENCE { 719 algorithm AlgorithmIdentifier, 720 subjectPublicKey BIT STRING 721 } 722 723In case the function returns a hash of the key: 724 725:: 726 727 DigestInfo ::= SEQUENCE { 728 digestAlgorithm AlgorithmIdentifier, 729 digest OCTET STRING 730 } 731 732The function returns 0 on success. Any other value is treated as error by the 733Trusted Board Boot. The function also reports extra information related 734to the ROTPK in the flags parameter: 735 736:: 737 738 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 739 hash. 740 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 741 verification while the platform ROTPK is not deployed. 742 When this flag is set, the function does not need to 743 return a platform ROTPK, and the authentication 744 framework uses the ROTPK in the certificate without 745 verifying it against the platform value. This flag 746 must not be used in a deployed production environment. 747 748Function: plat_get_nv_ctr() 749~~~~~~~~~~~~~~~~~~~~~~~~~~~ 750 751:: 752 753 Argument : void *, unsigned int * 754 Return : int 755 756This function is mandatory when Trusted Board Boot is enabled. It returns the 757non-volatile counter value stored in the platform in the second argument. The 758cookie in the first argument may be used to select the counter in case the 759platform provides more than one (for example, on platforms that use the default 760TBBR CoT, the cookie will correspond to the OID values defined in 761TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 762 763The function returns 0 on success. Any other value means the counter value could 764not be retrieved from the platform. 765 766Function: plat_set_nv_ctr() 767~~~~~~~~~~~~~~~~~~~~~~~~~~~ 768 769:: 770 771 Argument : void *, unsigned int 772 Return : int 773 774This function is mandatory when Trusted Board Boot is enabled. It sets a new 775counter value in the platform. The cookie in the first argument may be used to 776select the counter (as explained in plat_get_nv_ctr()). The second argument is 777the updated counter value to be written to the NV counter. 778 779The function returns 0 on success. Any other value means the counter value could 780not be updated. 781 782Function: plat_set_nv_ctr2() 783~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 784 785:: 786 787 Argument : void *, const auth_img_desc_t *, unsigned int 788 Return : int 789 790This function is optional when Trusted Board Boot is enabled. If this 791interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 792first argument passed is a cookie and is typically used to 793differentiate between a Non Trusted NV Counter and a Trusted NV 794Counter. The second argument is a pointer to an authentication image 795descriptor and may be used to decide if the counter is allowed to be 796updated or not. The third argument is the updated counter value to 797be written to the NV counter. 798 799The function returns 0 on success. Any other value means the counter value 800either could not be updated or the authentication image descriptor indicates 801that it is not allowed to be updated. 802 803Common mandatory function modifications 804--------------------------------------- 805 806The following functions are mandatory functions which need to be implemented 807by the platform port. 808 809Function : plat_my_core_pos() 810~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 811 812:: 813 814 Argument : void 815 Return : unsigned int 816 817This function returns the index of the calling CPU which is used as a 818CPU-specific linear index into blocks of memory (for example while allocating 819per-CPU stacks). This function will be invoked very early in the 820initialization sequence which mandates that this function should be 821implemented in assembly and should not rely on the availability of a C 822runtime environment. This function can clobber x0 - x8 and must preserve 823x9 - x29. 824 825This function plays a crucial role in the power domain topology framework in 826PSCI and details of this can be found in `Power Domain Topology Design`_. 827 828Function : plat_core_pos_by_mpidr() 829~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 830 831:: 832 833 Argument : u_register_t 834 Return : int 835 836This function validates the ``MPIDR`` of a CPU and converts it to an index, 837which can be used as a CPU-specific linear index into blocks of memory. In 838case the ``MPIDR`` is invalid, this function returns -1. This function will only 839be invoked by BL31 after the power domain topology is initialized and can 840utilize the C runtime environment. For further details about how TF-A 841represents the power domain topology and how this relates to the linear CPU 842index, please refer `Power Domain Topology Design`_. 843 844Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 845~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 846 847:: 848 849 Arguments : void **heap_addr, size_t *heap_size 850 Return : int 851 852This function is invoked during Mbed TLS library initialisation to get a heap, 853by means of a starting address and a size. This heap will then be used 854internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 855must be able to provide a heap to it. 856 857A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 858which a heap is statically reserved during compile time inside every image 859(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 860the function simply returns the address and size of this "pre-allocated" heap. 861For a platform to use this default implementation, only a call to the helper 862from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 863 864However, by writting their own implementation, platforms have the potential to 865optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 866shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 867twice. 868 869On success the function should return 0 and a negative error code otherwise. 870 871Common optional modifications 872----------------------------- 873 874The following are helper functions implemented by the firmware that perform 875common platform-specific tasks. A platform may choose to override these 876definitions. 877 878Function : plat_set_my_stack() 879~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 880 881:: 882 883 Argument : void 884 Return : void 885 886This function sets the current stack pointer to the normal memory stack that 887has been allocated for the current CPU. For BL images that only require a 888stack for the primary CPU, the UP version of the function is used. The size 889of the stack allocated to each CPU is specified by the platform defined 890constant ``PLATFORM_STACK_SIZE``. 891 892Common implementations of this function for the UP and MP BL images are 893provided in `plat/common/aarch64/platform_up_stack.S`_ and 894`plat/common/aarch64/platform_mp_stack.S`_ 895 896Function : plat_get_my_stack() 897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 898 899:: 900 901 Argument : void 902 Return : uintptr_t 903 904This function returns the base address of the normal memory stack that 905has been allocated for the current CPU. For BL images that only require a 906stack for the primary CPU, the UP version of the function is used. The size 907of the stack allocated to each CPU is specified by the platform defined 908constant ``PLATFORM_STACK_SIZE``. 909 910Common implementations of this function for the UP and MP BL images are 911provided in `plat/common/aarch64/platform_up_stack.S`_ and 912`plat/common/aarch64/platform_mp_stack.S`_ 913 914Function : plat_report_exception() 915~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 916 917:: 918 919 Argument : unsigned int 920 Return : void 921 922A platform may need to report various information about its status when an 923exception is taken, for example the current exception level, the CPU security 924state (secure/non-secure), the exception type, and so on. This function is 925called in the following circumstances: 926 927- In BL1, whenever an exception is taken. 928- In BL2, whenever an exception is taken. 929 930The default implementation doesn't do anything, to avoid making assumptions 931about the way the platform displays its status information. 932 933For AArch64, this function receives the exception type as its argument. 934Possible values for exceptions types are listed in the 935`include/common/bl_common.h`_ header file. Note that these constants are not 936related to any architectural exception code; they are just a TF-A convention. 937 938For AArch32, this function receives the exception mode as its argument. 939Possible values for exception modes are listed in the 940`include/lib/aarch32/arch.h`_ header file. 941 942Function : plat_reset_handler() 943~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 944 945:: 946 947 Argument : void 948 Return : void 949 950A platform may need to do additional initialization after reset. This function 951allows the platform to do the platform specific intializations. Platform 952specific errata workarounds could also be implemented here. The API should 953preserve the values of callee saved registers x19 to x29. 954 955The default implementation doesn't do anything. If a platform needs to override 956the default implementation, refer to the `Firmware Design`_ for general 957guidelines. 958 959Function : plat_disable_acp() 960~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 961 962:: 963 964 Argument : void 965 Return : void 966 967This API allows a platform to disable the Accelerator Coherency Port (if 968present) during a cluster power down sequence. The default weak implementation 969doesn't do anything. Since this API is called during the power down sequence, 970it has restrictions for stack usage and it can use the registers x0 - x17 as 971scratch registers. It should preserve the value in x18 register as it is used 972by the caller to store the return address. 973 974Function : plat_error_handler() 975~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 976 977:: 978 979 Argument : int 980 Return : void 981 982This API is called when the generic code encounters an error situation from 983which it cannot continue. It allows the platform to perform error reporting or 984recovery actions (for example, reset the system). This function must not return. 985 986The parameter indicates the type of error using standard codes from ``errno.h``. 987Possible errors reported by the generic code are: 988 989- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 990 Board Boot is enabled) 991- ``-ENOENT``: the requested image or certificate could not be found or an IO 992 error was detected 993- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 994 error is usually an indication of an incorrect array size 995 996The default implementation simply spins. 997 998Function : plat_panic_handler() 999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1000 1001:: 1002 1003 Argument : void 1004 Return : void 1005 1006This API is called when the generic code encounters an unexpected error 1007situation from which it cannot recover. This function must not return, 1008and must be implemented in assembly because it may be called before the C 1009environment is initialized. 1010 1011Note: The address from where it was called is stored in x30 (Link Register). 1012The default implementation simply spins. 1013 1014Function : plat_get_bl_image_load_info() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : bl_load_info_t * 1021 1022This function returns pointer to the list of images that the platform has 1023populated to load. This function is invoked in BL2 to load the 1024BL3xx images. 1025 1026Function : plat_get_next_bl_params() 1027~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1028 1029:: 1030 1031 Argument : void 1032 Return : bl_params_t * 1033 1034This function returns a pointer to the shared memory that the platform has 1035kept aside to pass TF-A related information that next BL image needs. This 1036function is invoked in BL2 to pass this information to the next BL 1037image. 1038 1039Function : plat_get_stack_protector_canary() 1040~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1041 1042:: 1043 1044 Argument : void 1045 Return : u_register_t 1046 1047This function returns a random value that is used to initialize the canary used 1048when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1049value will weaken the protection as the attacker could easily write the right 1050value as part of the attack most of the time. Therefore, it should return a 1051true random number. 1052 1053Note: For the protection to be effective, the global data need to be placed at 1054a lower address than the stack bases. Failure to do so would allow an attacker 1055to overwrite the canary as part of the stack buffer overflow attack. 1056 1057Function : plat_flush_next_bl_params() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Argument : void 1063 Return : void 1064 1065This function flushes to main memory all the image params that are passed to 1066next image. This function is invoked in BL2 to flush this information 1067to the next BL image. 1068 1069Function : plat_log_get_prefix() 1070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1071 1072:: 1073 1074 Argument : unsigned int 1075 Return : const char * 1076 1077This function defines the prefix string corresponding to the `log_level` to be 1078prepended to all the log output from TF-A. The `log_level` (argument) will 1079correspond to one of the standard log levels defined in debug.h. The platform 1080can override the common implementation to define a different prefix string for 1081the log output. The implementation should be robust to future changes that 1082increase the number of log levels. 1083 1084Modifications specific to a Boot Loader stage 1085--------------------------------------------- 1086 1087Boot Loader Stage 1 (BL1) 1088------------------------- 1089 1090BL1 implements the reset vector where execution starts from after a cold or 1091warm boot. For each CPU, BL1 is responsible for the following tasks: 1092 1093#. Handling the reset as described in section 2.2 1094 1095#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1096 only this CPU executes the remaining BL1 code, including loading and passing 1097 control to the BL2 stage. 1098 1099#. Identifying and starting the Firmware Update process (if required). 1100 1101#. Loading the BL2 image from non-volatile storage into secure memory at the 1102 address specified by the platform defined constant ``BL2_BASE``. 1103 1104#. Populating a ``meminfo`` structure with the following information in memory, 1105 accessible by BL2 immediately upon entry. 1106 1107 :: 1108 1109 meminfo.total_base = Base address of secure RAM visible to BL2 1110 meminfo.total_size = Size of secure RAM visible to BL2 1111 1112 By default, BL1 places this ``meminfo`` structure at the end of secure 1113 memory visible to BL2. 1114 1115 It is possible for the platform to decide where it wants to place the 1116 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1117 BL2 by overriding the weak default implementation of 1118 ``bl1_plat_handle_post_image_load`` API. 1119 1120The following functions need to be implemented by the platform port to enable 1121BL1 to perform the above tasks. 1122 1123Function : bl1_early_platform_setup() [mandatory] 1124~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1125 1126:: 1127 1128 Argument : void 1129 Return : void 1130 1131This function executes with the MMU and data caches disabled. It is only called 1132by the primary CPU. 1133 1134On Arm standard platforms, this function: 1135 1136- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1137 1138- Initializes a UART (PL011 console), which enables access to the ``printf`` 1139 family of functions in BL1. 1140 1141- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1142 the CCI slave interface corresponding to the cluster that includes the 1143 primary CPU. 1144 1145Function : bl1_plat_arch_setup() [mandatory] 1146~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1147 1148:: 1149 1150 Argument : void 1151 Return : void 1152 1153This function performs any platform-specific and architectural setup that the 1154platform requires. Platform-specific setup might include configuration of 1155memory controllers and the interconnect. 1156 1157In Arm standard platforms, this function enables the MMU. 1158 1159This function helps fulfill requirement 2 above. 1160 1161Function : bl1_platform_setup() [mandatory] 1162~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1163 1164:: 1165 1166 Argument : void 1167 Return : void 1168 1169This function executes with the MMU and data caches enabled. It is responsible 1170for performing any remaining platform-specific setup that can occur after the 1171MMU and data cache have been enabled. 1172 1173if support for multiple boot sources is required, it initializes the boot 1174sequence used by plat_try_next_boot_source(). 1175 1176In Arm standard platforms, this function initializes the storage abstraction 1177layer used to load the next bootloader image. 1178 1179This function helps fulfill requirement 4 above. 1180 1181Function : bl1_plat_sec_mem_layout() [mandatory] 1182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1183 1184:: 1185 1186 Argument : void 1187 Return : meminfo * 1188 1189This function should only be called on the cold boot path. It executes with the 1190MMU and data caches enabled. The pointer returned by this function must point to 1191a ``meminfo`` structure containing the extents and availability of secure RAM for 1192the BL1 stage. 1193 1194:: 1195 1196 meminfo.total_base = Base address of secure RAM visible to BL1 1197 meminfo.total_size = Size of secure RAM visible to BL1 1198 1199This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1200populates a similar structure to tell BL2 the extents of memory available for 1201its own use. 1202 1203This function helps fulfill requirements 4 and 5 above. 1204 1205Function : bl1_plat_prepare_exit() [optional] 1206~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1207 1208:: 1209 1210 Argument : entry_point_info_t * 1211 Return : void 1212 1213This function is called prior to exiting BL1 in response to the 1214``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1215platform specific clean up or bookkeeping operations before transferring 1216control to the next image. It receives the address of the ``entry_point_info_t`` 1217structure passed from BL2. This function runs with MMU disabled. 1218 1219Function : bl1_plat_set_ep_info() [optional] 1220~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1221 1222:: 1223 1224 Argument : unsigned int image_id, entry_point_info_t *ep_info 1225 Return : void 1226 1227This function allows platforms to override ``ep_info`` for the given ``image_id``. 1228 1229The default implementation just returns. 1230 1231Function : bl1_plat_get_next_image_id() [optional] 1232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1233 1234:: 1235 1236 Argument : void 1237 Return : unsigned int 1238 1239This and the following function must be overridden to enable the FWU feature. 1240 1241BL1 calls this function after platform setup to identify the next image to be 1242loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1243with the normal boot sequence, which loads and executes BL2. If the platform 1244returns a different image id, BL1 assumes that Firmware Update is required. 1245 1246The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1247platforms override this function to detect if firmware update is required, and 1248if so, return the first image in the firmware update process. 1249 1250Function : bl1_plat_get_image_desc() [optional] 1251~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1252 1253:: 1254 1255 Argument : unsigned int image_id 1256 Return : image_desc_t * 1257 1258BL1 calls this function to get the image descriptor information ``image_desc_t`` 1259for the provided ``image_id`` from the platform. 1260 1261The default implementation always returns a common BL2 image descriptor. Arm 1262standard platforms return an image descriptor corresponding to BL2 or one of 1263the firmware update images defined in the Trusted Board Boot Requirements 1264specification. 1265 1266Function : bl1_plat_handle_pre_image_load() [optional] 1267~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1268 1269:: 1270 1271 Argument : unsigned int image_id 1272 Return : int 1273 1274This function can be used by the platforms to update/use image information 1275corresponding to ``image_id``. This function is invoked in BL1, both in cold 1276boot and FWU code path, before loading the image. 1277 1278Function : bl1_plat_handle_post_image_load() [optional] 1279~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1280 1281:: 1282 1283 Argument : unsigned int image_id 1284 Return : int 1285 1286This function can be used by the platforms to update/use image information 1287corresponding to ``image_id``. This function is invoked in BL1, both in cold 1288boot and FWU code path, after loading and authenticating the image. 1289 1290The default weak implementation of this function calculates the amount of 1291Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1292structure at the beginning of this free memory and populates it. The address 1293of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1294information to BL2. 1295 1296Function : bl1_plat_fwu_done() [optional] 1297~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1298 1299:: 1300 1301 Argument : unsigned int image_id, uintptr_t image_src, 1302 unsigned int image_size 1303 Return : void 1304 1305BL1 calls this function when the FWU process is complete. It must not return. 1306The platform may override this function to take platform specific action, for 1307example to initiate the normal boot flow. 1308 1309The default implementation spins forever. 1310 1311Function : bl1_plat_mem_check() [mandatory] 1312~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1313 1314:: 1315 1316 Argument : uintptr_t mem_base, unsigned int mem_size, 1317 unsigned int flags 1318 Return : int 1319 1320BL1 calls this function while handling FWU related SMCs, more specifically when 1321copying or authenticating an image. Its responsibility is to ensure that the 1322region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1323that this memory corresponds to either a secure or non-secure memory region as 1324indicated by the security state of the ``flags`` argument. 1325 1326This function can safely assume that the value resulting from the addition of 1327``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1328overflow. 1329 1330This function must return 0 on success, a non-null error code otherwise. 1331 1332The default implementation of this function asserts therefore platforms must 1333override it when using the FWU feature. 1334 1335Boot Loader Stage 2 (BL2) 1336------------------------- 1337 1338The BL2 stage is executed only by the primary CPU, which is determined in BL1 1339using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1340``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1341``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1342non-volatile storage to secure/non-secure RAM. After all the images are loaded 1343then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1344images to be passed to the next BL image. 1345 1346The following functions must be implemented by the platform port to enable BL2 1347to perform the above tasks. 1348 1349Function : bl2_early_platform_setup2() [mandatory] 1350~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1351 1352:: 1353 1354 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1355 Return : void 1356 1357This function executes with the MMU and data caches disabled. It is only called 1358by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1359are platform specific. 1360 1361On Arm standard platforms, the arguments received are : 1362 1363 arg0 - Points to load address of HW_CONFIG if present 1364 1365 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1366 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1367 1368On Arm standard platforms, this function also: 1369 1370- Initializes a UART (PL011 console), which enables access to the ``printf`` 1371 family of functions in BL2. 1372 1373- Initializes the storage abstraction layer used to load further bootloader 1374 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1375 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1376 1377Function : bl2_plat_arch_setup() [mandatory] 1378~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1379 1380:: 1381 1382 Argument : void 1383 Return : void 1384 1385This function executes with the MMU and data caches disabled. It is only called 1386by the primary CPU. 1387 1388The purpose of this function is to perform any architectural initialization 1389that varies across platforms. 1390 1391On Arm standard platforms, this function enables the MMU. 1392 1393Function : bl2_platform_setup() [mandatory] 1394~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1395 1396:: 1397 1398 Argument : void 1399 Return : void 1400 1401This function may execute with the MMU and data caches enabled if the platform 1402port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1403called by the primary CPU. 1404 1405The purpose of this function is to perform any platform initialization 1406specific to BL2. 1407 1408In Arm standard platforms, this function performs security setup, including 1409configuration of the TrustZone controller to allow non-secure masters access 1410to most of DRAM. Part of DRAM is reserved for secure world use. 1411 1412Function : bl2_plat_handle_pre_image_load() [optional] 1413~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1414 1415:: 1416 1417 Argument : unsigned int 1418 Return : int 1419 1420This function can be used by the platforms to update/use image information 1421for given ``image_id``. This function is currently invoked in BL2 before 1422loading each image. 1423 1424Function : bl2_plat_handle_post_image_load() [optional] 1425~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1426 1427:: 1428 1429 Argument : unsigned int 1430 Return : int 1431 1432This function can be used by the platforms to update/use image information 1433for given ``image_id``. This function is currently invoked in BL2 after 1434loading each image. 1435 1436Function : bl2_plat_preload_setup [optional] 1437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1438 1439:: 1440 1441 Argument : void 1442 Return : void 1443 1444This optional function performs any BL2 platform initialization 1445required before image loading, that is not done later in 1446bl2_platform_setup(). Specifically, if support for multiple 1447boot sources is required, it initializes the boot sequence used by 1448plat_try_next_boot_source(). 1449 1450Function : plat_try_next_boot_source() [optional] 1451~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1452 1453:: 1454 1455 Argument : void 1456 Return : int 1457 1458This optional function passes to the next boot source in the redundancy 1459sequence. 1460 1461This function moves the current boot redundancy source to the next 1462element in the boot sequence. If there are no more boot sources then it 1463must return 0, otherwise it must return 1. The default implementation 1464of this always returns 0. 1465 1466Boot Loader Stage 2 (BL2) at EL3 1467-------------------------------- 1468 1469When the platform has a non-TF-A Boot ROM it is desirable to jump 1470directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1471execute at EL3 instead of executing at EL1. Refer to the `Firmware 1472Design`_ for more information. 1473 1474All mandatory functions of BL2 must be implemented, except the functions 1475bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1476their work is done now by bl2_el3_early_platform_setup and 1477bl2_el3_plat_arch_setup. These functions should generally implement 1478the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1479 1480 1481Function : bl2_el3_early_platform_setup() [mandatory] 1482~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1483 1484:: 1485 1486 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1487 Return : void 1488 1489This function executes with the MMU and data caches disabled. It is only called 1490by the primary CPU. This function receives four parameters which can be used 1491by the platform to pass any needed information from the Boot ROM to BL2. 1492 1493On Arm standard platforms, this function does the following: 1494 1495- Initializes a UART (PL011 console), which enables access to the ``printf`` 1496 family of functions in BL2. 1497 1498- Initializes the storage abstraction layer used to load further bootloader 1499 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1500 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1501 1502- Initializes the private variables that define the memory layout used. 1503 1504Function : bl2_el3_plat_arch_setup() [mandatory] 1505~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1506 1507:: 1508 1509 Argument : void 1510 Return : void 1511 1512This function executes with the MMU and data caches disabled. It is only called 1513by the primary CPU. 1514 1515The purpose of this function is to perform any architectural initialization 1516that varies across platforms. 1517 1518On Arm standard platforms, this function enables the MMU. 1519 1520Function : bl2_el3_plat_prepare_exit() [optional] 1521~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1522 1523:: 1524 1525 Argument : void 1526 Return : void 1527 1528This function is called prior to exiting BL2 and run the next image. 1529It should be used to perform platform specific clean up or bookkeeping 1530operations before transferring control to the next image. This function 1531runs with MMU disabled. 1532 1533FWU Boot Loader Stage 2 (BL2U) 1534------------------------------ 1535 1536The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1537process and is executed only by the primary CPU. BL1 passes control to BL2U at 1538``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1539 1540#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 1541 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 1542 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 1543 should be copied from. Subsequent handling of the SCP_BL2U image is 1544 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1545 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1546 1547#. Any platform specific setup required to perform the FWU process. For 1548 example, Arm standard platforms initialize the TZC controller so that the 1549 normal world can access DDR memory. 1550 1551The following functions must be implemented by the platform port to enable 1552BL2U to perform the tasks mentioned above. 1553 1554Function : bl2u_early_platform_setup() [mandatory] 1555~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1556 1557:: 1558 1559 Argument : meminfo *mem_info, void *plat_info 1560 Return : void 1561 1562This function executes with the MMU and data caches disabled. It is only 1563called by the primary CPU. The arguments to this function is the address 1564of the ``meminfo`` structure and platform specific info provided by BL1. 1565 1566The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1567private storage as the original memory may be subsequently overwritten by BL2U. 1568 1569On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1570to extract SCP_BL2U image information, which is then copied into a private 1571variable. 1572 1573Function : bl2u_plat_arch_setup() [mandatory] 1574~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1575 1576:: 1577 1578 Argument : void 1579 Return : void 1580 1581This function executes with the MMU and data caches disabled. It is only 1582called by the primary CPU. 1583 1584The purpose of this function is to perform any architectural initialization 1585that varies across platforms, for example enabling the MMU (since the memory 1586map differs across platforms). 1587 1588Function : bl2u_platform_setup() [mandatory] 1589~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1590 1591:: 1592 1593 Argument : void 1594 Return : void 1595 1596This function may execute with the MMU and data caches enabled if the platform 1597port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1598called by the primary CPU. 1599 1600The purpose of this function is to perform any platform initialization 1601specific to BL2U. 1602 1603In Arm standard platforms, this function performs security setup, including 1604configuration of the TrustZone controller to allow non-secure masters access 1605to most of DRAM. Part of DRAM is reserved for secure world use. 1606 1607Function : bl2u_plat_handle_scp_bl2u() [optional] 1608~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1609 1610:: 1611 1612 Argument : void 1613 Return : int 1614 1615This function is used to perform any platform-specific actions required to 1616handle the SCP firmware. Typically it transfers the image into SCP memory using 1617a platform-specific protocol and waits until SCP executes it and signals to the 1618Application Processor (AP) for BL2U execution to continue. 1619 1620This function returns 0 on success, a negative error code otherwise. 1621This function is included if SCP_BL2U_BASE is defined. 1622 1623Boot Loader Stage 3-1 (BL31) 1624---------------------------- 1625 1626During cold boot, the BL31 stage is executed only by the primary CPU. This is 1627determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1628control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1629CPUs. BL31 executes at EL3 and is responsible for: 1630 1631#. Re-initializing all architectural and platform state. Although BL1 performs 1632 some of this initialization, BL31 remains resident in EL3 and must ensure 1633 that EL3 architectural and platform state is completely initialized. It 1634 should make no assumptions about the system state when it receives control. 1635 1636#. Passing control to a normal world BL image, pre-loaded at a platform- 1637 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 1638 populated by BL2 in memory to do this. 1639 1640#. Providing runtime firmware services. Currently, BL31 only implements a 1641 subset of the Power State Coordination Interface (PSCI) API as a runtime 1642 service. See Section 3.3 below for details of porting the PSCI 1643 implementation. 1644 1645#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1646 specific address by BL2. BL31 exports a set of APIs that allow runtime 1647 services to specify the security state in which the next image should be 1648 executed and run the corresponding image. On ARM platforms, BL31 uses the 1649 ``bl_params`` list populated by BL2 in memory to do this. 1650 1651If BL31 is a reset vector, It also needs to handle the reset as specified in 1652section 2.2 before the tasks described above. 1653 1654The following functions must be implemented by the platform port to enable BL31 1655to perform the above tasks. 1656 1657Function : bl31_early_platform_setup2() [mandatory] 1658~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1659 1660:: 1661 1662 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1663 Return : void 1664 1665This function executes with the MMU and data caches disabled. It is only called 1666by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 1667platform specific. 1668 1669In Arm standard platforms, the arguments received are : 1670 1671 arg0 - The pointer to the head of `bl_params_t` list 1672 which is list of executable images following BL31, 1673 1674 arg1 - Points to load address of SOC_FW_CONFIG if present 1675 1676 arg2 - Points to load address of HW_CONFIG if present 1677 1678 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 1679 used in release builds. 1680 1681The function runs through the `bl_param_t` list and extracts the entry point 1682information for BL32 and BL33. It also performs the following: 1683 1684- Initialize a UART (PL011 console), which enables access to the ``printf`` 1685 family of functions in BL31. 1686 1687- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1688 CCI slave interface corresponding to the cluster that includes the primary 1689 CPU. 1690 1691Function : bl31_plat_arch_setup() [mandatory] 1692~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1693 1694:: 1695 1696 Argument : void 1697 Return : void 1698 1699This function executes with the MMU and data caches disabled. It is only called 1700by the primary CPU. 1701 1702The purpose of this function is to perform any architectural initialization 1703that varies across platforms. 1704 1705On Arm standard platforms, this function enables the MMU. 1706 1707Function : bl31_platform_setup() [mandatory] 1708~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1709 1710:: 1711 1712 Argument : void 1713 Return : void 1714 1715This function may execute with the MMU and data caches enabled if the platform 1716port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1717called by the primary CPU. 1718 1719The purpose of this function is to complete platform initialization so that both 1720BL31 runtime services and normal world software can function correctly. 1721 1722On Arm standard platforms, this function does the following: 1723 1724- Initialize the generic interrupt controller. 1725 1726 Depending on the GIC driver selected by the platform, the appropriate GICv2 1727 or GICv3 initialization will be done, which mainly consists of: 1728 1729 - Enable secure interrupts in the GIC CPU interface. 1730 - Disable the legacy interrupt bypass mechanism. 1731 - Configure the priority mask register to allow interrupts of all priorities 1732 to be signaled to the CPU interface. 1733 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1734 - Target all secure SPIs to CPU0. 1735 - Enable these secure interrupts in the GIC distributor. 1736 - Configure all other interrupts as non-secure. 1737 - Enable signaling of secure interrupts in the GIC distributor. 1738 1739- Enable system-level implementation of the generic timer counter through the 1740 memory mapped interface. 1741 1742- Grant access to the system counter timer module 1743 1744- Initialize the power controller device. 1745 1746 In particular, initialise the locks that prevent concurrent accesses to the 1747 power controller device. 1748 1749Function : bl31_plat_runtime_setup() [optional] 1750~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1751 1752:: 1753 1754 Argument : void 1755 Return : void 1756 1757The purpose of this function is allow the platform to perform any BL31 runtime 1758setup just prior to BL31 exit during cold boot. The default weak 1759implementation of this function will invoke ``console_switch_state()`` to switch 1760console output to consoles marked for use in the ``runtime`` state. 1761 1762Function : bl31_plat_get_next_image_ep_info() [mandatory] 1763~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1764 1765:: 1766 1767 Argument : uint32_t 1768 Return : entry_point_info * 1769 1770This function may execute with the MMU and data caches enabled if the platform 1771port does the necessary initializations in ``bl31_plat_arch_setup()``. 1772 1773This function is called by ``bl31_main()`` to retrieve information provided by 1774BL2 for the next image in the security state specified by the argument. BL31 1775uses this information to pass control to that image in the specified security 1776state. This function must return a pointer to the ``entry_point_info`` structure 1777(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1778should return NULL otherwise. 1779 1780Function : bl31_plat_enable_mmu [optional] 1781~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1782 1783:: 1784 1785 Argument : uint32_t 1786 Return : void 1787 1788This function enables the MMU. The boot code calls this function with MMU and 1789caches disabled. This function should program necessary registers to enable 1790translation, and upon return, the MMU on the calling PE must be enabled. 1791 1792The function must honor flags passed in the first argument. These flags are 1793defined by the translation library, and can be found in the file 1794``include/lib/xlat_tables/xlat_mmu_helpers.h``. 1795 1796On DynamIQ systems, this function must not use stack while enabling MMU, which 1797is how the function in xlat table library version 2 is implemented. 1798 1799Function : plat_init_apiakey [optional] 1800~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1801 1802:: 1803 1804 Argument : void 1805 Return : uint64_t * 1806 1807This function populates the ``plat_apiakey`` array that contains the values used 1808to set the ``APIAKey{Hi,Lo}_EL1`` registers. It returns a pointer to this array. 1809 1810The value should be obtained from a reliable source of randomness. 1811 1812This function is only needed if ARMv8.3 pointer authentication is used in the 1813Trusted Firmware by building with ``ENABLE_PAUTH=1``. 1814 1815Function : plat_get_syscnt_freq2() [mandatory] 1816~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1817 1818:: 1819 1820 Argument : void 1821 Return : unsigned int 1822 1823This function is used by the architecture setup code to retrieve the counter 1824frequency for the CPU's generic timer. This value will be programmed into the 1825``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 1826of the system counter, which is retrieved from the first entry in the frequency 1827modes table. 1828 1829#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 1830~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1831 1832When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1833bytes) aligned to the cache line boundary that should be allocated per-cpu to 1834accommodate all the bakery locks. 1835 1836If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1837calculates the size of the ``bakery_lock`` input section, aligns it to the 1838nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1839and stores the result in a linker symbol. This constant prevents a platform 1840from relying on the linker and provide a more efficient mechanism for 1841accessing per-cpu bakery lock information. 1842 1843If this constant is defined and its value is not equal to the value 1844calculated by the linker then a link time assertion is raised. A compile time 1845assertion is raised if the value of the constant is not aligned to the cache 1846line boundary. 1847 1848SDEI porting requirements 1849~~~~~~~~~~~~~~~~~~~~~~~~~ 1850 1851The SDEI dispatcher requires the platform to provide the following macros 1852and functions, of which some are optional, and some others mandatory. 1853 1854Macros 1855...... 1856 1857Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 1858^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1859 1860This macro must be defined to the EL3 exception priority level associated with 1861Normal SDEI events on the platform. This must have a higher value (therefore of 1862lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 1863 1864Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 1865^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1866 1867This macro must be defined to the EL3 exception priority level associated with 1868Critical SDEI events on the platform. This must have a lower value (therefore of 1869higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 1870 1871**Note**: SDEI exception priorities must be the lowest among Secure priorities. 1872Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 1873SDEI priority. 1874 1875Functions 1876......... 1877 1878Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 1879^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1880 1881:: 1882 1883 Argument: uintptr_t 1884 Return: int 1885 1886This function validates the address of client entry points provided for both 1887event registration and *Complete and Resume* SDEI calls. The function takes one 1888argument, which is the address of the handler the SDEI client requested to 1889register. The function must return ``0`` for successful validation, or ``-1`` 1890upon failure. 1891 1892The default implementation always returns ``0``. On Arm platforms, this function 1893is implemented to translate the entry point to physical address, and further to 1894ensure that the address is located in Non-secure DRAM. 1895 1896Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 1897^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1898 1899:: 1900 1901 Argument: uint64_t 1902 Argument: unsigned int 1903 Return: void 1904 1905SDEI specification requires that a PE comes out of reset with the events masked. 1906The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 1907the PE. No SDEI events can be dispatched until such time. 1908 1909Should a PE receive an interrupt that was bound to an SDEI event while the 1910events are masked on the PE, the dispatcher implementation invokes the function 1911``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 1912interrupt and the interrupt ID are passed as parameters. 1913 1914The default implementation only prints out a warning message. 1915 1916Power State Coordination Interface (in BL31) 1917-------------------------------------------- 1918 1919The TF-A implementation of the PSCI API is based around the concept of a 1920*power domain*. A *power domain* is a CPU or a logical group of CPUs which 1921share some state on which power management operations can be performed as 1922specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 1923a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 1924*power domains* are arranged in a hierarchical tree structure and each 1925*power domain* can be identified in a system by the cpu index of any CPU that 1926is part of that domain and a *power domain level*. A processing element (for 1927example, a CPU) is at level 0. If the *power domain* node above a CPU is a 1928logical grouping of CPUs that share some state, then level 1 is that group of 1929CPUs (for example, a cluster), and level 2 is a group of clusters (for 1930example, the system). More details on the power domain topology and its 1931organization can be found in `Power Domain Topology Design`_. 1932 1933BL31's platform initialization code exports a pointer to the platform-specific 1934power management operations required for the PSCI implementation to function 1935correctly. This information is populated in the ``plat_psci_ops`` structure. The 1936PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 1937power management operations on the power domains. For example, the target 1938CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 1939handler (if present) is called for the CPU power domain. 1940 1941The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 1942describe composite power states specific to a platform. The PSCI implementation 1943defines a generic representation of the power-state parameter, which is an 1944array of local power states where each index corresponds to a power domain 1945level. Each entry contains the local power state the power domain at that power 1946level could enter. It depends on the ``validate_power_state()`` handler to 1947convert the power-state parameter (possibly encoding a composite power state) 1948passed in a PSCI ``CPU_SUSPEND`` call to this representation. 1949 1950The following functions form part of platform port of PSCI functionality. 1951 1952Function : plat_psci_stat_accounting_start() [optional] 1953~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1954 1955:: 1956 1957 Argument : const psci_power_state_t * 1958 Return : void 1959 1960This is an optional hook that platforms can implement for residency statistics 1961accounting before entering a low power state. The ``pwr_domain_state`` field of 1962``state_info`` (first argument) can be inspected if stat accounting is done 1963differently at CPU level versus higher levels. As an example, if the element at 1964index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1965state, special hardware logic may be programmed in order to keep track of the 1966residency statistics. For higher levels (array indices > 0), the residency 1967statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1968default implementation will use PMF to capture timestamps. 1969 1970Function : plat_psci_stat_accounting_stop() [optional] 1971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1972 1973:: 1974 1975 Argument : const psci_power_state_t * 1976 Return : void 1977 1978This is an optional hook that platforms can implement for residency statistics 1979accounting after exiting from a low power state. The ``pwr_domain_state`` field 1980of ``state_info`` (first argument) can be inspected if stat accounting is done 1981differently at CPU level versus higher levels. As an example, if the element at 1982index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1983state, special hardware logic may be programmed in order to keep track of the 1984residency statistics. For higher levels (array indices > 0), the residency 1985statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1986default implementation will use PMF to capture timestamps. 1987 1988Function : plat_psci_stat_get_residency() [optional] 1989~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1990 1991:: 1992 1993 Argument : unsigned int, const psci_power_state_t *, int 1994 Return : u_register_t 1995 1996This is an optional interface that is is invoked after resuming from a low power 1997state and provides the time spent resident in that low power state by the power 1998domain at a particular power domain level. When a CPU wakes up from suspend, 1999all its parent power domain levels are also woken up. The generic PSCI code 2000invokes this function for each parent power domain that is resumed and it 2001identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2002argument) describes the low power state that the power domain has resumed from. 2003The current CPU is the first CPU in the power domain to resume from the low 2004power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2005CPU in the power domain to suspend and may be needed to calculate the residency 2006for that power domain. 2007 2008Function : plat_get_target_pwr_state() [optional] 2009~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2010 2011:: 2012 2013 Argument : unsigned int, const plat_local_state_t *, unsigned int 2014 Return : plat_local_state_t 2015 2016The PSCI generic code uses this function to let the platform participate in 2017state coordination during a power management operation. The function is passed 2018a pointer to an array of platform specific local power state ``states`` (second 2019argument) which contains the requested power state for each CPU at a particular 2020power domain level ``lvl`` (first argument) within the power domain. The function 2021is expected to traverse this array of upto ``ncpus`` (third argument) and return 2022a coordinated target power state by the comparing all the requested power 2023states. The target power state should not be deeper than any of the requested 2024power states. 2025 2026A weak definition of this API is provided by default wherein it assumes 2027that the platform assigns a local state value in order of increasing depth 2028of the power state i.e. for two power states X & Y, if X < Y 2029then X represents a shallower power state than Y. As a result, the 2030coordinated target local power state for a power domain will be the minimum 2031of the requested local power state values. 2032 2033Function : plat_get_power_domain_tree_desc() [mandatory] 2034~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2035 2036:: 2037 2038 Argument : void 2039 Return : const unsigned char * 2040 2041This function returns a pointer to the byte array containing the power domain 2042topology tree description. The format and method to construct this array are 2043described in `Power Domain Topology Design`_. The BL31 PSCI initialization code 2044requires this array to be described by the platform, either statically or 2045dynamically, to initialize the power domain topology tree. In case the array 2046is populated dynamically, then plat_core_pos_by_mpidr() and 2047plat_my_core_pos() should also be implemented suitably so that the topology 2048tree description matches the CPU indices returned by these APIs. These APIs 2049together form the platform interface for the PSCI topology framework. 2050 2051Function : plat_setup_psci_ops() [mandatory] 2052~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2053 2054:: 2055 2056 Argument : uintptr_t, const plat_psci_ops ** 2057 Return : int 2058 2059This function may execute with the MMU and data caches enabled if the platform 2060port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2061called by the primary CPU. 2062 2063This function is called by PSCI initialization code. Its purpose is to let 2064the platform layer know about the warm boot entrypoint through the 2065``sec_entrypoint`` (first argument) and to export handler routines for 2066platform-specific psci power management actions by populating the passed 2067pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2068 2069A description of each member of this structure is given below. Please refer to 2070the Arm FVP specific implementation of these handlers in 2071`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the 2072platform wants to support, the associated operation or operations in this 2073structure must be provided and implemented (Refer section 4 of 2074`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2075function in a platform port, the operation should be removed from this 2076structure instead of providing an empty implementation. 2077 2078plat_psci_ops.cpu_standby() 2079........................... 2080 2081Perform the platform-specific actions to enter the standby state for a cpu 2082indicated by the passed argument. This provides a fast path for CPU standby 2083wherein overheads of PSCI state management and lock acquisition is avoided. 2084For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2085the suspend state type specified in the ``power-state`` parameter should be 2086STANDBY and the target power domain level specified should be the CPU. The 2087handler should put the CPU into a low power retention state (usually by 2088issuing a wfi instruction) and ensure that it can be woken up from that 2089state by a normal interrupt. The generic code expects the handler to succeed. 2090 2091plat_psci_ops.pwr_domain_on() 2092............................. 2093 2094Perform the platform specific actions to power on a CPU, specified 2095by the ``MPIDR`` (first argument). The generic code expects the platform to 2096return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2097 2098plat_psci_ops.pwr_domain_off() 2099.............................. 2100 2101Perform the platform specific actions to prepare to power off the calling CPU 2102and its higher parent power domain levels as indicated by the ``target_state`` 2103(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2104 2105The ``target_state`` encodes the platform coordinated target local power states 2106for the CPU power domain and its parent power domain levels. The handler 2107needs to perform power management operation corresponding to the local state 2108at each power level. 2109 2110For this handler, the local power state for the CPU power domain will be a 2111power down state where as it could be either power down, retention or run state 2112for the higher power domain levels depending on the result of state 2113coordination. The generic code expects the handler to succeed. 2114 2115plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2116........................................................... 2117 2118This optional function may be used as a performance optimization to replace 2119or complement pwr_domain_suspend() on some platforms. Its calling semantics 2120are identical to pwr_domain_suspend(), except the PSCI implementation only 2121calls this function when suspending to a power down state, and it guarantees 2122that data caches are enabled. 2123 2124When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2125before calling pwr_domain_suspend(). If the target_state corresponds to a 2126power down state and it is safe to perform some or all of the platform 2127specific actions in that function with data caches enabled, it may be more 2128efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2129= 1, data caches remain enabled throughout, and so there is no advantage to 2130moving platform specific actions to this function. 2131 2132plat_psci_ops.pwr_domain_suspend() 2133.................................. 2134 2135Perform the platform specific actions to prepare to suspend the calling 2136CPU and its higher parent power domain levels as indicated by the 2137``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2138API implementation. 2139 2140The ``target_state`` has a similar meaning as described in 2141the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2142target local power states for the CPU power domain and its parent 2143power domain levels. The handler needs to perform power management operation 2144corresponding to the local state at each power level. The generic code 2145expects the handler to succeed. 2146 2147The difference between turning a power domain off versus suspending it is that 2148in the former case, the power domain is expected to re-initialize its state 2149when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2150case, the power domain is expected to save enough state so that it can resume 2151execution by restoring this state when its powered on (see 2152``pwr_domain_suspend_finish()``). 2153 2154When suspending a core, the platform can also choose to power off the GICv3 2155Redistributor and ITS through an implementation-defined sequence. To achieve 2156this safely, the ITS context must be saved first. The architectural part is 2157implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2158sequence is implementation defined and it is therefore the responsibility of 2159the platform code to implement the necessary sequence. Then the GIC 2160Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2161Powering off the Redistributor requires the implementation to support it and it 2162is the responsibility of the platform code to execute the right implementation 2163defined sequence. 2164 2165When a system suspend is requested, the platform can also make use of the 2166``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2167it has saved the context of the Redistributors and ITS of all the cores in the 2168system. The context of the Distributor can be large and may require it to be 2169allocated in a special area if it cannot fit in the platform's global static 2170data, for example in DRAM. The Distributor can then be powered down using an 2171implementation-defined sequence. 2172 2173plat_psci_ops.pwr_domain_pwr_down_wfi() 2174....................................... 2175 2176This is an optional function and, if implemented, is expected to perform 2177platform specific actions including the ``wfi`` invocation which allows the 2178CPU to powerdown. Since this function is invoked outside the PSCI locks, 2179the actions performed in this hook must be local to the CPU or the platform 2180must ensure that races between multiple CPUs cannot occur. 2181 2182The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2183operation and it encodes the platform coordinated target local power states for 2184the CPU power domain and its parent power domain levels. This function must 2185not return back to the caller. 2186 2187If this function is not implemented by the platform, PSCI generic 2188implementation invokes ``psci_power_down_wfi()`` for power down. 2189 2190plat_psci_ops.pwr_domain_on_finish() 2191.................................... 2192 2193This function is called by the PSCI implementation after the calling CPU is 2194powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2195It performs the platform-specific setup required to initialize enough state for 2196this CPU to enter the normal world and also provide secure runtime firmware 2197services. 2198 2199The ``target_state`` (first argument) is the prior state of the power domains 2200immediately before the CPU was turned on. It indicates which power domains 2201above the CPU might require initialization due to having previously been in 2202low power states. The generic code expects the handler to succeed. 2203 2204plat_psci_ops.pwr_domain_suspend_finish() 2205......................................... 2206 2207This function is called by the PSCI implementation after the calling CPU is 2208powered on and released from reset in response to an asynchronous wakeup 2209event, for example a timer interrupt that was programmed by the CPU during the 2210``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2211setup required to restore the saved state for this CPU to resume execution 2212in the normal world and also provide secure runtime firmware services. 2213 2214The ``target_state`` (first argument) has a similar meaning as described in 2215the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2216to succeed. 2217 2218If the Distributor, Redistributors or ITS have been powered off as part of a 2219suspend, their context must be restored in this function in the reverse order 2220to how they were saved during suspend sequence. 2221 2222plat_psci_ops.system_off() 2223.......................... 2224 2225This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2226call. It performs the platform-specific system poweroff sequence after 2227notifying the Secure Payload Dispatcher. 2228 2229plat_psci_ops.system_reset() 2230............................ 2231 2232This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2233call. It performs the platform-specific system reset sequence after 2234notifying the Secure Payload Dispatcher. 2235 2236plat_psci_ops.validate_power_state() 2237.................................... 2238 2239This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2240call to validate the ``power_state`` parameter of the PSCI API and if valid, 2241populate it in ``req_state`` (second argument) array as power domain level 2242specific local states. If the ``power_state`` is invalid, the platform must 2243return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2244normal world PSCI client. 2245 2246plat_psci_ops.validate_ns_entrypoint() 2247...................................... 2248 2249This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2250``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2251parameter passed by the normal world. If the ``entry_point`` is invalid, 2252the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2253propagated back to the normal world PSCI client. 2254 2255plat_psci_ops.get_sys_suspend_power_state() 2256........................................... 2257 2258This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2259call to get the ``req_state`` parameter from platform which encodes the power 2260domain level specific local states to suspend to system affinity level. The 2261``req_state`` will be utilized to do the PSCI state coordination and 2262``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2263enter system suspend. 2264 2265plat_psci_ops.get_pwr_lvl_state_idx() 2266..................................... 2267 2268This is an optional function and, if implemented, is invoked by the PSCI 2269implementation to convert the ``local_state`` (first argument) at a specified 2270``pwr_lvl`` (second argument) to an index between 0 and 2271``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2272supports more than two local power states at each power domain level, that is 2273``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2274local power states. 2275 2276plat_psci_ops.translate_power_state_by_mpidr() 2277.............................................. 2278 2279This is an optional function and, if implemented, verifies the ``power_state`` 2280(second argument) parameter of the PSCI API corresponding to a target power 2281domain. The target power domain is identified by using both ``MPIDR`` (first 2282argument) and the power domain level encoded in ``power_state``. The power domain 2283level specific local states are to be extracted from ``power_state`` and be 2284populated in the ``output_state`` (third argument) array. The functionality 2285is similar to the ``validate_power_state`` function described above and is 2286envisaged to be used in case the validity of ``power_state`` depend on the 2287targeted power domain. If the ``power_state`` is invalid for the targeted power 2288domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 2289function is not implemented, then the generic implementation relies on 2290``validate_power_state`` function to translate the ``power_state``. 2291 2292This function can also be used in case the platform wants to support local 2293power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 2294APIs as described in Section 5.18 of `PSCI`_. 2295 2296plat_psci_ops.get_node_hw_state() 2297................................. 2298 2299This is an optional function. If implemented this function is intended to return 2300the power state of a node (identified by the first parameter, the ``MPIDR``) in 2301the power domain topology (identified by the second parameter, ``power_level``), 2302as retrieved from a power controller or equivalent component on the platform. 2303Upon successful completion, the implementation must map and return the final 2304status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2305must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2306appropriate. 2307 2308Implementations are not expected to handle ``power_levels`` greater than 2309``PLAT_MAX_PWR_LVL``. 2310 2311plat_psci_ops.system_reset2() 2312............................. 2313 2314This is an optional function. If implemented this function is 2315called during the ``SYSTEM_RESET2`` call to perform a reset 2316based on the first parameter ``reset_type`` as specified in 2317`PSCI`_. The parameter ``cookie`` can be used to pass additional 2318reset information. If the ``reset_type`` is not supported, the 2319function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2320resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2321and vendor reset can return other PSCI error codes as defined 2322in `PSCI`_. On success this function will not return. 2323 2324plat_psci_ops.write_mem_protect() 2325................................. 2326 2327This is an optional function. If implemented it enables or disables the 2328``MEM_PROTECT`` functionality based on the value of ``val``. 2329A non-zero value enables ``MEM_PROTECT`` and a value of zero 2330disables it. Upon encountering failures it must return a negative value 2331and on success it must return 0. 2332 2333plat_psci_ops.read_mem_protect() 2334................................ 2335 2336This is an optional function. If implemented it returns the current 2337state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2338failures it must return a negative value and on success it must 2339return 0. 2340 2341plat_psci_ops.mem_protect_chk() 2342............................... 2343 2344This is an optional function. If implemented it checks if a memory 2345region defined by a base address ``base`` and with a size of ``length`` 2346bytes is protected by ``MEM_PROTECT``. If the region is protected 2347then it must return 0, otherwise it must return a negative number. 2348 2349Interrupt Management framework (in BL31) 2350---------------------------------------- 2351 2352BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2353generated in either security state and targeted to EL1 or EL2 in the non-secure 2354state or EL3/S-EL1 in the secure state. The design of this framework is 2355described in the `IMF Design Guide`_ 2356 2357A platform should export the following APIs to support the IMF. The following 2358text briefly describes each API and its implementation in Arm standard 2359platforms. The API implementation depends upon the type of interrupt controller 2360present in the platform. Arm standard platform layer supports both 2361`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2362and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2363FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2364``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2365`User Guide`_ for more details). 2366 2367See also: `Interrupt Controller Abstraction APIs`__. 2368 2369.. __: platform-interrupt-controller-API.rst 2370 2371Function : plat_interrupt_type_to_line() [mandatory] 2372~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2373 2374:: 2375 2376 Argument : uint32_t, uint32_t 2377 Return : uint32_t 2378 2379The Arm processor signals an interrupt exception either through the IRQ or FIQ 2380interrupt line. The specific line that is signaled depends on how the interrupt 2381controller (IC) reports different interrupt types from an execution context in 2382either security state. The IMF uses this API to determine which interrupt line 2383the platform IC uses to signal each type of interrupt supported by the framework 2384from a given security state. This API must be invoked at EL3. 2385 2386The first parameter will be one of the ``INTR_TYPE_*`` values (see 2387`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2388security state of the originating execution context. The return result is the 2389bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2390FIQ=2. 2391 2392In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2393configured as FIQs and Non-secure interrupts as IRQs from either security 2394state. 2395 2396In the case of Arm standard platforms using GICv3, the interrupt line to be 2397configured depends on the security state of the execution context when the 2398interrupt is signalled and are as follows: 2399 2400- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2401 NS-EL0/1/2 context. 2402- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2403 in the NS-EL0/1/2 context. 2404- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2405 context. 2406 2407Function : plat_ic_get_pending_interrupt_type() [mandatory] 2408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2409 2410:: 2411 2412 Argument : void 2413 Return : uint32_t 2414 2415This API returns the type of the highest priority pending interrupt at the 2416platform IC. The IMF uses the interrupt type to retrieve the corresponding 2417handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2418pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2419``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2420 2421In the case of Arm standard platforms using GICv2, the *Highest Priority 2422Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2423the pending interrupt. The type of interrupt depends upon the id value as 2424follows. 2425 2426#. id < 1022 is reported as a S-EL1 interrupt 2427#. id = 1022 is reported as a Non-secure interrupt. 2428#. id = 1023 is reported as an invalid interrupt type. 2429 2430In the case of Arm standard platforms using GICv3, the system register 2431``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2432is read to determine the id of the pending interrupt. The type of interrupt 2433depends upon the id value as follows. 2434 2435#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2436#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2437#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2438#. All other interrupt id's are reported as EL3 interrupt. 2439 2440Function : plat_ic_get_pending_interrupt_id() [mandatory] 2441~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2442 2443:: 2444 2445 Argument : void 2446 Return : uint32_t 2447 2448This API returns the id of the highest priority pending interrupt at the 2449platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2450pending. 2451 2452In the case of Arm standard platforms using GICv2, the *Highest Priority 2453Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2454pending interrupt. The id that is returned by API depends upon the value of 2455the id read from the interrupt controller as follows. 2456 2457#. id < 1022. id is returned as is. 2458#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2459 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2460 This id is returned by the API. 2461#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2462 2463In the case of Arm standard platforms using GICv3, if the API is invoked from 2464EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2465group 0 Register*, is read to determine the id of the pending interrupt. The id 2466that is returned by API depends upon the value of the id read from the 2467interrupt controller as follows. 2468 2469#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2470#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2471 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2472 Register* is read to determine the id of the group 1 interrupt. This id 2473 is returned by the API as long as it is a valid interrupt id 2474#. If the id is any of the special interrupt identifiers, 2475 ``INTR_ID_UNAVAILABLE`` is returned. 2476 2477When the API invoked from S-EL1 for GICv3 systems, the id read from system 2478register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2479Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 2480``INTR_ID_UNAVAILABLE`` is returned. 2481 2482Function : plat_ic_acknowledge_interrupt() [mandatory] 2483~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2484 2485:: 2486 2487 Argument : void 2488 Return : uint32_t 2489 2490This API is used by the CPU to indicate to the platform IC that processing of 2491the highest pending interrupt has begun. It should return the raw, unmodified 2492value obtained from the interrupt controller when acknowledging an interrupt. 2493The actual interrupt number shall be extracted from this raw value using the API 2494`plat_ic_get_interrupt_id()`__. 2495 2496.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2497 2498This function in Arm standard platforms using GICv2, reads the *Interrupt 2499Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2500priority pending interrupt from pending to active in the interrupt controller. 2501It returns the value read from the ``GICC_IAR``, unmodified. 2502 2503In the case of Arm standard platforms using GICv3, if the API is invoked 2504from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2505Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2506reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2507group 1*. The read changes the state of the highest pending interrupt from 2508pending to active in the interrupt controller. The value read is returned 2509unmodified. 2510 2511The TSP uses this API to start processing of the secure physical timer 2512interrupt. 2513 2514Function : plat_ic_end_of_interrupt() [mandatory] 2515~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2516 2517:: 2518 2519 Argument : uint32_t 2520 Return : void 2521 2522This API is used by the CPU to indicate to the platform IC that processing of 2523the interrupt corresponding to the id (passed as the parameter) has 2524finished. The id should be the same as the id returned by the 2525``plat_ic_acknowledge_interrupt()`` API. 2526 2527Arm standard platforms write the id to the *End of Interrupt Register* 2528(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2529system register in case of GICv3 depending on where the API is invoked from, 2530EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2531controller. 2532 2533The TSP uses this API to finish processing of the secure physical timer 2534interrupt. 2535 2536Function : plat_ic_get_interrupt_type() [mandatory] 2537~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2538 2539:: 2540 2541 Argument : uint32_t 2542 Return : uint32_t 2543 2544This API returns the type of the interrupt id passed as the parameter. 2545``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2546interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2547returned depending upon how the interrupt has been configured by the platform 2548IC. This API must be invoked at EL3. 2549 2550Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2551and Non-secure interrupts as Group1 interrupts. It reads the group value 2552corresponding to the interrupt id from the relevant *Interrupt Group Register* 2553(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2554 2555In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2556Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2557(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2558as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2559 2560Crash Reporting mechanism (in BL31) 2561----------------------------------- 2562 2563BL31 implements a crash reporting mechanism which prints the various registers 2564of the CPU to enable quick crash analysis and debugging. This mechanism relies 2565on the platform implementing ``plat_crash_console_init``, 2566``plat_crash_console_putc`` and ``plat_crash_console_flush``. 2567 2568The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 2569implementation of all of them. Platforms may include this file to their 2570makefiles in order to benefit from them. By default, they will cause the crash 2571output to be routed over the normal console infrastructure and get printed on 2572consoles configured to output in crash state. ``console_set_scope()`` can be 2573used to control whether a console is used for crash output. 2574NOTE: Platforms are responsible for making sure that they only mark consoles for 2575use in the crash scope that are able to support this, i.e. that are written in 2576assembly and conform with the register clobber rules for putc() (x0-x2, x16-x17) 2577and flush() (x0-x3, x16-x17) crash callbacks. 2578 2579In some cases (such as debugging very early crashes that happen before the 2580normal boot console can be set up), platforms may want to control crash output 2581more explicitly. These platforms may instead provide custom implementations for 2582these. They are executed outside of a C environment and without a stack. Many 2583console drivers provide functions named ``console_xxx_core_init/putc/flush`` 2584that are designed to be used by these functions. See Arm platforms (like juno) 2585for an example of this. 2586 2587Function : plat_crash_console_init [mandatory] 2588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2589 2590:: 2591 2592 Argument : void 2593 Return : int 2594 2595This API is used by the crash reporting mechanism to initialize the crash 2596console. It must only use the general purpose registers x0 through x7 to do the 2597initialization and returns 1 on success. 2598 2599Function : plat_crash_console_putc [mandatory] 2600~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2601 2602:: 2603 2604 Argument : int 2605 Return : int 2606 2607This API is used by the crash reporting mechanism to print a character on the 2608designated crash console. It must only use general purpose registers x1 and 2609x2 to do its work. The parameter and the return value are in general purpose 2610register x0. 2611 2612Function : plat_crash_console_flush [mandatory] 2613~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2614 2615:: 2616 2617 Argument : void 2618 Return : int 2619 2620This API is used by the crash reporting mechanism to force write of all buffered 2621data on the designated crash console. It should only use general purpose 2622registers x0 through x5 to do its work. The return value is 0 on successful 2623completion; otherwise the return value is -1. 2624 2625External Abort handling and RAS Support 2626--------------------------------------- 2627 2628Function : plat_ea_handler 2629~~~~~~~~~~~~~~~~~~~~~~~~~~ 2630 2631:: 2632 2633 Argument : int 2634 Argument : uint64_t 2635 Argument : void * 2636 Argument : void * 2637 Argument : uint64_t 2638 Return : void 2639 2640This function is invoked by the RAS framework for the platform to handle an 2641External Abort received at EL3. The intention of the function is to attempt to 2642resolve the cause of External Abort and return; if that's not possible, to 2643initiate orderly shutdown of the system. 2644 2645The first parameter (``int ea_reason``) indicates the reason for External Abort. 2646Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2647 2648The second parameter (``uint64_t syndrome``) is the respective syndrome 2649presented to EL3 after having received the External Abort. Depending on the 2650nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2651can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2652 2653The third parameter (``void *cookie``) is unused for now. The fourth parameter 2654(``void *handle``) is a pointer to the preempted context. The fifth parameter 2655(``uint64_t flags``) indicates the preempted security state. These parameters 2656are received from the top-level exception handler. 2657 2658If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2659function iterates through RAS handlers registered by the platform. If any of the 2660RAS handlers resolve the External Abort, no further action is taken. 2661 2662If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2663could resolve the External Abort, the default implementation prints an error 2664message, and panics. 2665 2666Function : plat_handle_uncontainable_ea 2667~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2668 2669:: 2670 2671 Argument : int 2672 Argument : uint64_t 2673 Return : void 2674 2675This function is invoked by the RAS framework when an External Abort of 2676Uncontainable type is received at EL3. Due to the critical nature of 2677Uncontainable errors, the intention of this function is to initiate orderly 2678shutdown of the system, and is not expected to return. 2679 2680This function must be implemented in assembly. 2681 2682The first and second parameters are the same as that of ``plat_ea_handler``. 2683 2684The default implementation of this function calls 2685``report_unhandled_exception``. 2686 2687Function : plat_handle_double_fault 2688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2689 2690:: 2691 2692 Argument : int 2693 Argument : uint64_t 2694 Return : void 2695 2696This function is invoked by the RAS framework when another External Abort is 2697received at EL3 while one is already being handled. I.e., a call to 2698``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2699this function is to initiate orderly shutdown of the system, and is not expected 2700recover or return. 2701 2702This function must be implemented in assembly. 2703 2704The first and second parameters are the same as that of ``plat_ea_handler``. 2705 2706The default implementation of this function calls 2707``report_unhandled_exception``. 2708 2709Function : plat_handle_el3_ea 2710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2711 2712:: 2713 2714 Return : void 2715 2716This function is invoked when an External Abort is received while executing in 2717EL3. Due to its critical nature, the intention of this function is to initiate 2718orderly shutdown of the system, and is not expected recover or return. 2719 2720This function must be implemented in assembly. 2721 2722The default implementation of this function calls 2723``report_unhandled_exception``. 2724 2725Build flags 2726----------- 2727 2728There are some build flags which can be defined by the platform to control 2729inclusion or exclusion of certain BL stages from the FIP image. These flags 2730need to be defined in the platform makefile which will get included by the 2731build system. 2732 2733- **NEED_BL33** 2734 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2735 build option should be supplied as a build option. The platform has the 2736 option of excluding the BL33 image in the ``fip`` image by defining this flag 2737 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2738 are used, this flag will be set to ``no`` automatically. 2739 2740C Library 2741--------- 2742 2743To avoid subtle toolchain behavioral dependencies, the header files provided 2744by the compiler are not used. The software is built with the ``-nostdinc`` flag 2745to ensure no headers are included from the toolchain inadvertently. Instead the 2746required headers are included in the TF-A source tree. The library only 2747contains those C library definitions required by the local implementation. If 2748more functionality is required, the needed library functions will need to be 2749added to the local implementation. 2750 2751Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 2752been written specifically for TF-A. Fome implementation files have been obtained 2753from `FreeBSD`_, others have been written specifically for TF-A as well. The 2754files can be found in ``include/lib/libc`` and ``lib/libc``. 2755 2756SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 2757can be obtained from http://github.com/freebsd/freebsd. 2758 2759Storage abstraction layer 2760------------------------- 2761 2762In order to improve platform independence and portability an storage abstraction 2763layer is used to load data from non-volatile platform storage. 2764 2765Each platform should register devices and their drivers via the Storage layer. 2766These drivers then need to be initialized by bootloader phases as 2767required in their respective ``blx_platform_setup()`` functions. Currently 2768storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2769function uses the storage layer to access non-volatile platform storage. 2770 2771It is mandatory to implement at least one storage driver. For the Arm 2772development platforms the Firmware Image Package (FIP) driver is provided as 2773the default means to load data from storage (see the "Firmware Image Package" 2774section in the `User Guide`_). The storage layer is described in the header file 2775``include/drivers/io/io_storage.h``. The implementation of the common library 2776is in ``drivers/io/io_storage.c`` and the driver files are located in 2777``drivers/io/``. 2778 2779Each IO driver must provide ``io_dev_*`` structures, as described in 2780``drivers/io/io_driver.h``. These are returned via a mandatory registration 2781function that is called on platform initialization. The semi-hosting driver 2782implementation in ``io_semihosting.c`` can be used as an example. 2783 2784The Storage layer provides mechanisms to initialize storage devices before 2785IO operations are called. The basic operations supported by the layer 2786include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2787Drivers do not have to implement all operations, but each platform must 2788provide at least one driver for a device capable of supporting generic 2789operations such as loading a bootloader image. 2790 2791The current implementation only allows for known images to be loaded by the 2792firmware. These images are specified by using their identifiers, as defined in 2793``include/plat/common/common_def.h`` (or a separate header file included from 2794there). The platform layer (``plat_get_image_source()``) then returns a reference 2795to a device and a driver-specific ``spec`` which will be understood by the driver 2796to allow access to the image data. 2797 2798The layer is designed in such a way that is it possible to chain drivers with 2799other drivers. For example, file-system drivers may be implemented on top of 2800physical block devices, both represented by IO devices with corresponding 2801drivers. In such a case, the file-system "binding" with the block device may 2802be deferred until the file-system device is initialised. 2803 2804The abstraction currently depends on structures being statically allocated 2805by the drivers and callers, as the system does not yet provide a means of 2806dynamically allocating memory. This may also have the affect of limiting the 2807amount of open resources per driver. 2808 2809-------------- 2810 2811*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* 2812 2813.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2814.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2815.. _User Guide: user-guide.rst 2816.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h 2817.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h 2818.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2819.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S 2820.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2821.. _Power Domain Topology Design: psci-pd-tree.rst 2822.. _include/common/bl_common.h: ../include/common/bl_common.h 2823.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2824.. _Firmware Design: firmware-design.rst 2825.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2826.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2827.. _Platform compatibility policy: ./platform-compatibility-policy.rst 2828.. _IMF Design Guide: interrupt-framework-design.rst 2829.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2830.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2831.. _FreeBSD: https://www.freebsd.org 2832.. _SCC: http://www.simple-cc.org/ 2833