| e1abd560 | 17-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
arch: add some defines for generic timer registers
Those defines are used in STM32MP1 clock driver.
It is better to put them altogether with already defined registers.
Change-Id: I6f8ad8c2477b947af
arch: add some defines for generic timer registers
Those defines are used in STM32MP1 clock driver.
It is better to put them altogether with already defined registers.
Change-Id: I6f8ad8c2477b947af6f76283a4ef5c40212d0027
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| fbcdc4eb | 14-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Fix checkpatch issues
Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I60
rcar_gen3: drivers: qos: H3: Fix checkpatch issues
Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I605109b5e41219473a4cbc4a1929b84377ba0b67
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|
| 7479a33f | 13-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Drop MD pin check
The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the
rcar_gen3: drivers: qos: H3: Drop MD pin check
The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4d8926eb3c44c61ec777c05c581ce8247f13daa6
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|
| 1a9eb1ed | 13-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Drop useless comments
Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9e3d025567ff
rcar_gen3: drivers: qos: H3: Drop useless comments
Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9e3d025567ff4e10e2b4448e8a518b4eee13f6c5
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|
| 606dfb2c | 13-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Drop extra level of nesting
The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Chang
rcar_gen3: drivers: qos: H3: Drop extra level of nesting
The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7b55a6fa53145ff0427e05656234917f486031df
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|
| fcc9d57c | 13-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t
Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
l
rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t
Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
loop can operate over incrementing sequence of addresses just fine.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I379a1a5dfe2095d9477b364393ab120c4d8e1ba4
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|
| 4318b580 | 13-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file
Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file
Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia92abe11c425220a065d707c350644c955efef92
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|
| 60d78ca4 | 13-Jun-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: qos: H3: Use common register definition
Use common qos_regs.h instead of a local copy in the H3 QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-o
rcar_gen3: drivers: qos: H3: Use common register definition
Use common qos_regs.h instead of a local copy in the H3 QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0b5ceab71be07e270885bdff403e5292e3373787
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|
| 018358fc | 18-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: console: Convert to multi-console API
Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Chang
rcar_gen3: console: Convert to multi-console API
Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I18556973937d150b60453f9150d54ee612571e35
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|
| 2efb7ddc | 07-Jun-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Fix type of cot_desc_ptr
The chain of trust description and the pointer pointing to its first
element were incompatible, thus requiring an explicit type cast for
the assignment.
- cot_desc was an a
Fix type of cot_desc_ptr
The chain of trust description and the pointer pointing to its first
element were incompatible, thus requiring an explicit type cast for
the assignment.
- cot_desc was an array of
const pointers to const image descriptors.
- cot_desc_ptr was a const pointer to
(non-constant) pointers to const image descriptors.
Thus, trying to assign cot_desc to cot_desc_ptr (with no cast) would
generate the following compiler warning:
drivers/auth/tbbr/tbbr_cot.c:826:14: warning: initialization discards
‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
REGISTER_COT(cot_desc);
^~~~~~~~
Change-Id: Iae62dd1bdb43fe379e3843d96461d47cc2f68a06
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| acc29852 | 31-May-2019 |
James kung <kong1191@gmail.com> |
Prevent pending G1S interrupt become G0 interrupt
According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:
Prevent pending G1S interrupt become G0 interrupt
According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:
- The PE does not implement EL3.
- ICC_SRE_EL1(S).SRE == 0
When a cpu enter suspend or deep idle, it might be
powered off. When the cpu resume, according to
the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and
9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if
write is allowed) and G0/G1S/G1NS interrupt of the
GIC cpu interface are all disabled.
If a G1S SPI interrupt occurred and the target cpu
of the SPI is assigned to a specific cpu which is
in suspend and is powered off, when the cpu resume
and start to initial the GIC cpu interface, the
initial sequence might affect the interrupt group
type of the pending interrupt on the cpu interface.
Current initial sequence on the cpu interface is:
1. Enable G0 interrupt
2. Enable G1S interrupt
3. Enable ICC_SRE_EL1(S).SRE
It is possible to treat the pending G1S interrupt
as G0 interrupt on the cpu interface if the G1S
SPI interrupt occurred between step2 and step3.
To prevent the above situation happend, the initial
sequence should be changed as follows:
1. Enable ICC_SRE_EL1(S).SRE
2. Enable G0 interrupt
3. Enable G1S interrupt
Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0
Signed-off-by: James Kung <kong1191@gmail.com>
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|
| 292bc551 | 23-May-2019 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
drivers: scmi: scmi_sq: Modify wrong payload length
Payload length of the get dram mapping information message is 0.
The mbx_mem->len parameter should be 4, it only contains
message header.
Fixes:
drivers: scmi: scmi_sq: Modify wrong payload length
Payload length of the get dram mapping information message is 0.
The mbx_mem->len parameter should be 4, it only contains
message header.
Fixes: b67d202 ("plat/synquacer: enable SCMI support")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: If1cd4c855da2dc5dc4b6da3bea152b8441971de7
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|
| 197822e2 | 12-Apr-2019 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
rcar_gen3: drivers: qos: update QoS setting
Update M3 Ver.3.0 QoS setting rev.0.03.
Change-Id: I892521d456c606ac3d30f2b2ac6b4e16faa5fc48
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas
rcar_gen3: drivers: qos: update QoS setting
Update M3 Ver.3.0 QoS setting rev.0.03.
Change-Id: I892521d456c606ac3d30f2b2ac6b4e16faa5fc48
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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|
| 519a7db2 | 15-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "drivers: ufs: Extend the delay after reset to wait for some slower chips" into integration |
| cbebadf5 | 13-May-2019 |
John Stultz <john.stultz@linaro.org> |
drivers: ufs: Extend the delay after reset to wait for some slower chips
We've seen issues with some THG based UFS chips, where
after reset the LUNs don't always enumerate properly.
After some debu
drivers: ufs: Extend the delay after reset to wait for some slower chips
We've seen issues with some THG based UFS chips, where
after reset the LUNs don't always enumerate properly.
After some debugging, we found that extending the mdelay
here seems to resolve the issue by giving the chips enough
time to complete reset.
Change-Id: I848f810b2438ed6ad3d33db614c61d2cef9ac400
Signed-off-by: John Stultz <john.stultz@linaro.org>
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|
| 1461ad9f | 09-May-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
SMMUv3: Abort DMA transactions
For security DMA should be blocked at the SMMU by default
unless explicitly enabled for a device. SMMU is disabled
after reset with all streams bypassing the SMMU, and
SMMUv3: Abort DMA transactions
For security DMA should be blocked at the SMMU by default
unless explicitly enabled for a device. SMMU is disabled
after reset with all streams bypassing the SMMU, and
abortion of all incoming transactions implements a default
deny policy on reset.
This patch also moves "bl1_platform_setup()" function from
arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and
fvp_ve_bl1_setup.c files.
Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| ccd4d475 | 26-Apr-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
SMMUv3: refactor the driver code
This patch is a preparation for the subsequent changes in
SMMUv3 driver. It introduces a new "smmuv3_poll" function
and replaces inline functions for accessing SMMU
SMMUv3: refactor the driver code
This patch is a preparation for the subsequent changes in
SMMUv3 driver. It introduces a new "smmuv3_poll" function
and replaces inline functions for accessing SMMU registers
with mmio read/write operations. Also the infinite loop
for the poll has been replaced with a counter based timeout.
Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 6f78eb5c | 07-Mar-2019 |
Heiko Stuebner <heiko@sntech.de> |
drivers: ti: uart: add a aarch32 variant
Rockchip re-uses the ti uart console driver and for aarch32 needs a
specific variant, so add it.
There are also aarch32 ti socs, so it may be useful for them
drivers: ti: uart: add a aarch32 variant
Rockchip re-uses the ti uart console driver and for aarch32 needs a
specific variant, so add it.
There are also aarch32 ti socs, so it may be useful for them as well
at some point.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I31ede7cc7b10347b3691cff051db2b985fd59e17
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|
| 71892ca3 | 18-Apr-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Console: Allow to register multiple times
It removes the need to unregister the console on system suspend.
Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce
Signed-off-by: Ambroise Vincent <ambr
Console: Allow to register multiple times
It removes the need to unregister the console on system suspend.
Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| f79abf5e | 16-Apr-2019 |
Aditya Angadi <aditya.angadi@arm.com> |
drivers/sbsa: add sbsa watchdog driver
Add a driver for configuring the SBSA Generic Watchdog which aids in
the detection of errant system behaviour.
Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339
drivers/sbsa: add sbsa watchdog driver
Add a driver for configuring the SBSA Generic Watchdog which aids in
the detection of errant system behaviour.
Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| 72db70ca | 12-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge changes from topic "av/tls-heap" into integration
* changes:
Mbed TLS: Remove weak heap implementation
sgm: Fix bl2 sources |
| 2374ab17 | 10-Apr-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Mbed TLS: Remove weak heap implementation
The implementation of the heap function plat_get_mbedtls_heap() becomes
mandatory for platforms supporting TRUSTED_BOARD_BOOT.
The shared Mbed TLS heap def
Mbed TLS: Remove weak heap implementation
The implementation of the heap function plat_get_mbedtls_heap() becomes
mandatory for platforms supporting TRUSTED_BOARD_BOOT.
The shared Mbed TLS heap default weak function implementation is
converted to a helper function get_mbedtls_heap_helper() which can be
used by the platforms for their own function implementation.
Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| 7704ff91 | 22-Mar-2019 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
rcar_gen3: drivers: Change to restore timer counter value at resume
Changed to save and restore cntpct_el0 using memory mapped
register for generic timer when System Suspend and Resume.
Reported by
rcar_gen3: drivers: Change to restore timer counter value at resume
Changed to save and restore cntpct_el0 using memory mapped
register for generic timer when System Suspend and Resume.
Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
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|
| 4983f8b6 | 15-Mar-2019 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
Very rarely, LPDDR4 power consumption may not decrease
In self-refresh mode.
This patch fixes the DBSC4 self-refresh mode sequen
rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
Very rarely, LPDDR4 power consumption may not decrease
In self-refresh mode.
This patch fixes the DBSC4 self-refresh mode sequence.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com>
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
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|
| 4988c4c1 | 01-Mar-2019 |
Chiaki Fujii <chiaki.fujii.wj@renesas.com> |
rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
[IPL/DDR]
- Update DDR setting rev.0.35.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I2b936ca8621ca320cc97353f99240da5f
rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
[IPL/DDR]
- Update DDR setting rev.0.35.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
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|