xref: /rk3399_ARM-atf/fdts/stm32mp157a-dk1.dts (revision f33b2433f5a6ae0a89ec7c1234deb7ac64362367)
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com>.
5 */
6
7/dts-v1/;
8
9#include "stm32mp157c.dtsi"
10#include "stm32mp157cac-pinctrl.dtsi"
11
12/ {
13	model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
14	compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
15
16	aliases {
17		serial0 = &uart4;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24};
25
26&clk_hse {
27	st,digbypass;
28};
29
30&i2c4 {
31	pinctrl-names = "default";
32	pinctrl-0 = <&i2c4_pins_a>;
33	i2c-scl-rising-time-ns = <185>;
34	i2c-scl-falling-time-ns = <20>;
35	status = "okay";
36
37	pmic: stpmic@33 {
38		compatible = "st,stpmic1";
39		reg = <0x33>;
40		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
41		interrupt-controller;
42		#interrupt-cells = <2>;
43		status = "okay";
44
45		st,main-control-register = <0x04>;
46		st,vin-control-register = <0xc0>;
47		st,usb-control-register = <0x20>;
48
49		regulators {
50			compatible = "st,stpmic1-regulators";
51
52			ldo1-supply = <&v3v3>;
53			ldo3-supply = <&vdd_ddr>;
54			ldo6-supply = <&v3v3>;
55
56			vddcore: buck1 {
57				regulator-name = "vddcore";
58				regulator-min-microvolt = <1200000>;
59				regulator-max-microvolt = <1350000>;
60				regulator-always-on;
61				regulator-initial-mode = <0>;
62				regulator-over-current-protection;
63			};
64
65			vdd_ddr: buck2 {
66				regulator-name = "vdd_ddr";
67				regulator-min-microvolt = <1350000>;
68				regulator-max-microvolt = <1350000>;
69				regulator-always-on;
70				regulator-initial-mode = <0>;
71				regulator-over-current-protection;
72			};
73
74			vdd: buck3 {
75				regulator-name = "vdd";
76				regulator-min-microvolt = <3300000>;
77				regulator-max-microvolt = <3300000>;
78				regulator-always-on;
79				st,mask-reset;
80				regulator-initial-mode = <0>;
81				regulator-over-current-protection;
82			};
83
84			v3v3: buck4 {
85				regulator-name = "v3v3";
86				regulator-min-microvolt = <3300000>;
87				regulator-max-microvolt = <3300000>;
88				regulator-always-on;
89				regulator-over-current-protection;
90				regulator-initial-mode = <0>;
91			};
92
93			v1v8_audio: ldo1 {
94				regulator-name = "v1v8_audio";
95				regulator-min-microvolt = <1800000>;
96				regulator-max-microvolt = <1800000>;
97				regulator-always-on;
98			};
99
100			v3v3_hdmi: ldo2 {
101				regulator-name = "v3v3_hdmi";
102				regulator-min-microvolt = <3300000>;
103				regulator-max-microvolt = <3300000>;
104				regulator-always-on;
105			};
106
107			vtt_ddr: ldo3 {
108				regulator-name = "vtt_ddr";
109				regulator-min-microvolt = <500000>;
110				regulator-max-microvolt = <750000>;
111				regulator-always-on;
112				regulator-over-current-protection;
113			};
114
115			vdd_usb: ldo4 {
116				regulator-name = "vdd_usb";
117				regulator-min-microvolt = <3300000>;
118				regulator-max-microvolt = <3300000>;
119			};
120
121			vdda: ldo5 {
122				regulator-name = "vdda";
123				regulator-min-microvolt = <2900000>;
124				regulator-max-microvolt = <2900000>;
125				regulator-boot-on;
126			};
127
128			v1v2_hdmi: ldo6 {
129				regulator-name = "v1v2_hdmi";
130				regulator-min-microvolt = <1200000>;
131				regulator-max-microvolt = <1200000>;
132				regulator-always-on;
133			};
134
135			vref_ddr: vref_ddr {
136				regulator-name = "vref_ddr";
137				regulator-always-on;
138				regulator-over-current-protection;
139			};
140		};
141	};
142};
143
144&iwdg2 {
145	timeout-sec = <32>;
146	status = "okay";
147};
148
149&pwr {
150	pwr-regulators {
151		vdd-supply = <&vdd>;
152	};
153};
154
155&rng1 {
156	status = "okay";
157};
158
159&rtc {
160	status = "okay";
161};
162
163&sdmmc1 {
164	pinctrl-names = "default";
165	pinctrl-0 = <&sdmmc1_b4_pins_a>;
166	broken-cd;
167	st,neg-edge;
168	bus-width = <4>;
169	vmmc-supply = <&v3v3>;
170	status = "okay";
171};
172
173&uart4 {
174	pinctrl-names = "default";
175	pinctrl-0 = <&uart4_pins_a>;
176	status = "okay";
177};
178
179/* ATF Specific */
180#include <dt-bindings/clock/stm32mp1-clksrc.h>
181#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
182#include "stm32mp157c-security.dtsi"
183
184/ {
185	aliases {
186		gpio0 = &gpioa;
187		gpio1 = &gpiob;
188		gpio2 = &gpioc;
189		gpio3 = &gpiod;
190		gpio4 = &gpioe;
191		gpio5 = &gpiof;
192		gpio6 = &gpiog;
193		gpio7 = &gpioh;
194		gpio8 = &gpioi;
195		gpio25 = &gpioz;
196		i2c3 = &i2c4;
197	};
198};
199
200/* CLOCK init */
201&rcc {
202	secure-status = "disabled";
203	st,clksrc = <
204		CLK_MPU_PLL1P
205		CLK_AXI_PLL2P
206		CLK_MCU_PLL3P
207		CLK_PLL12_HSE
208		CLK_PLL3_HSE
209		CLK_PLL4_HSE
210		CLK_RTC_LSE
211		CLK_MCO1_DISABLED
212		CLK_MCO2_DISABLED
213	>;
214
215	st,clkdiv = <
216		1 /*MPU*/
217		0 /*AXI*/
218		0 /*MCU*/
219		1 /*APB1*/
220		1 /*APB2*/
221		1 /*APB3*/
222		1 /*APB4*/
223		2 /*APB5*/
224		23 /*RTC*/
225		0 /*MCO1*/
226		0 /*MCO2*/
227	>;
228
229	st,pkcs = <
230		CLK_CKPER_HSE
231		CLK_FMC_ACLK
232		CLK_QSPI_ACLK
233		CLK_ETH_DISABLED
234		CLK_SDMMC12_PLL4P
235		CLK_DSI_DSIPLL
236		CLK_STGEN_HSE
237		CLK_USBPHY_HSE
238		CLK_SPI2S1_PLL3Q
239		CLK_SPI2S23_PLL3Q
240		CLK_SPI45_HSI
241		CLK_SPI6_HSI
242		CLK_I2C46_HSI
243		CLK_SDMMC3_PLL4P
244		CLK_USBO_USBPHY
245		CLK_ADC_CKPER
246		CLK_CEC_LSE
247		CLK_I2C12_HSI
248		CLK_I2C35_HSI
249		CLK_UART1_HSI
250		CLK_UART24_HSI
251		CLK_UART35_HSI
252		CLK_UART6_HSI
253		CLK_UART78_HSI
254		CLK_SPDIF_PLL4P
255		CLK_FDCAN_PLL4Q
256		CLK_SAI1_PLL3Q
257		CLK_SAI2_PLL3Q
258		CLK_SAI3_PLL3Q
259		CLK_SAI4_PLL3Q
260		CLK_RNG1_LSI
261		CLK_RNG2_LSI
262		CLK_LPTIM1_PCLK1
263		CLK_LPTIM23_PCLK3
264		CLK_LPTIM45_LSE
265	>;
266
267	/* VCO = 1300.0 MHz => P = 650 (CPU) */
268	pll1: st,pll@0 {
269		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
270		frac = < 0x800 >;
271	};
272
273	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
274	pll2: st,pll@1 {
275		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
276		frac = < 0x1400 >;
277	};
278
279	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
280	pll3: st,pll@2 {
281		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
282		frac = < 0x1a04 >;
283	};
284
285	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
286	pll4: st,pll@3 {
287		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
288	};
289};
290