1 /* 2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <drivers/delay_timer.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/st/stm32mp_clkfunc.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_rcc.h> 24 #include <dt-bindings/clock/stm32mp1-clksrc.h> 25 #include <lib/mmio.h> 26 #include <lib/spinlock.h> 27 #include <lib/utils_def.h> 28 #include <plat/common/platform.h> 29 30 #define MAX_HSI_HZ 64000000 31 #define USB_PHY_48_MHZ 48000000 32 33 #define TIMEOUT_US_200MS U(200000) 34 #define TIMEOUT_US_1S U(1000000) 35 36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 41 42 const char *stm32mp_osc_node_label[NB_OSC] = { 43 [_LSI] = "clk-lsi", 44 [_LSE] = "clk-lse", 45 [_HSI] = "clk-hsi", 46 [_HSE] = "clk-hse", 47 [_CSI] = "clk-csi", 48 [_I2S_CKIN] = "i2s_ckin", 49 }; 50 51 enum stm32mp1_parent_id { 52 /* Oscillators are defined in enum stm32mp_osc_id */ 53 54 /* Other parent source */ 55 _HSI_KER = NB_OSC, 56 _HSE_KER, 57 _HSE_KER_DIV2, 58 _CSI_KER, 59 _PLL1_P, 60 _PLL1_Q, 61 _PLL1_R, 62 _PLL2_P, 63 _PLL2_Q, 64 _PLL2_R, 65 _PLL3_P, 66 _PLL3_Q, 67 _PLL3_R, 68 _PLL4_P, 69 _PLL4_Q, 70 _PLL4_R, 71 _ACLK, 72 _PCLK1, 73 _PCLK2, 74 _PCLK3, 75 _PCLK4, 76 _PCLK5, 77 _HCLK6, 78 _HCLK2, 79 _CK_PER, 80 _CK_MPU, 81 _CK_MCU, 82 _USB_PHY_48, 83 _PARENT_NB, 84 _UNKNOWN_ID = 0xff, 85 }; 86 87 /* Lists only the parent clock we are interested in */ 88 enum stm32mp1_parent_sel { 89 _I2C12_SEL, 90 _I2C35_SEL, 91 _STGEN_SEL, 92 _I2C46_SEL, 93 _SPI6_SEL, 94 _UART1_SEL, 95 _RNG1_SEL, 96 _UART6_SEL, 97 _UART24_SEL, 98 _UART35_SEL, 99 _UART78_SEL, 100 _SDMMC12_SEL, 101 _SDMMC3_SEL, 102 _QSPI_SEL, 103 _FMC_SEL, 104 _AXIS_SEL, 105 _MCUS_SEL, 106 _USBPHY_SEL, 107 _USBO_SEL, 108 _PARENT_SEL_NB, 109 _UNKNOWN_SEL = 0xff, 110 }; 111 112 enum stm32mp1_pll_id { 113 _PLL1, 114 _PLL2, 115 _PLL3, 116 _PLL4, 117 _PLL_NB 118 }; 119 120 enum stm32mp1_div_id { 121 _DIV_P, 122 _DIV_Q, 123 _DIV_R, 124 _DIV_NB, 125 }; 126 127 enum stm32mp1_clksrc_id { 128 CLKSRC_MPU, 129 CLKSRC_AXI, 130 CLKSRC_MCU, 131 CLKSRC_PLL12, 132 CLKSRC_PLL3, 133 CLKSRC_PLL4, 134 CLKSRC_RTC, 135 CLKSRC_MCO1, 136 CLKSRC_MCO2, 137 CLKSRC_NB 138 }; 139 140 enum stm32mp1_clkdiv_id { 141 CLKDIV_MPU, 142 CLKDIV_AXI, 143 CLKDIV_MCU, 144 CLKDIV_APB1, 145 CLKDIV_APB2, 146 CLKDIV_APB3, 147 CLKDIV_APB4, 148 CLKDIV_APB5, 149 CLKDIV_RTC, 150 CLKDIV_MCO1, 151 CLKDIV_MCO2, 152 CLKDIV_NB 153 }; 154 155 enum stm32mp1_pllcfg { 156 PLLCFG_M, 157 PLLCFG_N, 158 PLLCFG_P, 159 PLLCFG_Q, 160 PLLCFG_R, 161 PLLCFG_O, 162 PLLCFG_NB 163 }; 164 165 enum stm32mp1_pllcsg { 166 PLLCSG_MOD_PER, 167 PLLCSG_INC_STEP, 168 PLLCSG_SSCG_MODE, 169 PLLCSG_NB 170 }; 171 172 enum stm32mp1_plltype { 173 PLL_800, 174 PLL_1600, 175 PLL_TYPE_NB 176 }; 177 178 struct stm32mp1_pll { 179 uint8_t refclk_min; 180 uint8_t refclk_max; 181 uint8_t divn_max; 182 }; 183 184 struct stm32mp1_clk_gate { 185 uint16_t offset; 186 uint8_t bit; 187 uint8_t index; 188 uint8_t set_clr; 189 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 190 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 191 }; 192 193 struct stm32mp1_clk_sel { 194 uint16_t offset; 195 uint8_t src; 196 uint8_t msk; 197 uint8_t nb_parent; 198 const uint8_t *parent; 199 }; 200 201 #define REFCLK_SIZE 4 202 struct stm32mp1_clk_pll { 203 enum stm32mp1_plltype plltype; 204 uint16_t rckxselr; 205 uint16_t pllxcfgr1; 206 uint16_t pllxcfgr2; 207 uint16_t pllxfracr; 208 uint16_t pllxcr; 209 uint16_t pllxcsgr; 210 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 211 }; 212 213 /* Clocks with selectable source and non set/clr register access */ 214 #define _CLK_SELEC(off, b, idx, s) \ 215 { \ 216 .offset = (off), \ 217 .bit = (b), \ 218 .index = (idx), \ 219 .set_clr = 0, \ 220 .sel = (s), \ 221 .fixed = _UNKNOWN_ID, \ 222 } 223 224 /* Clocks with fixed source and non set/clr register access */ 225 #define _CLK_FIXED(off, b, idx, f) \ 226 { \ 227 .offset = (off), \ 228 .bit = (b), \ 229 .index = (idx), \ 230 .set_clr = 0, \ 231 .sel = _UNKNOWN_SEL, \ 232 .fixed = (f), \ 233 } 234 235 /* Clocks with selectable source and set/clr register access */ 236 #define _CLK_SC_SELEC(off, b, idx, s) \ 237 { \ 238 .offset = (off), \ 239 .bit = (b), \ 240 .index = (idx), \ 241 .set_clr = 1, \ 242 .sel = (s), \ 243 .fixed = _UNKNOWN_ID, \ 244 } 245 246 /* Clocks with fixed source and set/clr register access */ 247 #define _CLK_SC_FIXED(off, b, idx, f) \ 248 { \ 249 .offset = (off), \ 250 .bit = (b), \ 251 .index = (idx), \ 252 .set_clr = 1, \ 253 .sel = _UNKNOWN_SEL, \ 254 .fixed = (f), \ 255 } 256 257 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 258 [_ ## _label ## _SEL] = { \ 259 .offset = _rcc_selr, \ 260 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 261 .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \ 262 .parent = (_parents), \ 263 .nb_parent = ARRAY_SIZE(_parents) \ 264 } 265 266 #define _CLK_PLL(idx, type, off1, off2, off3, \ 267 off4, off5, off6, \ 268 p1, p2, p3, p4) \ 269 [(idx)] = { \ 270 .plltype = (type), \ 271 .rckxselr = (off1), \ 272 .pllxcfgr1 = (off2), \ 273 .pllxcfgr2 = (off3), \ 274 .pllxfracr = (off4), \ 275 .pllxcr = (off5), \ 276 .pllxcsgr = (off6), \ 277 .refclk[0] = (p1), \ 278 .refclk[1] = (p2), \ 279 .refclk[2] = (p3), \ 280 .refclk[3] = (p4), \ 281 } 282 283 static const uint8_t stm32mp1_clks[][2] = { 284 { CK_PER, _CK_PER }, 285 { CK_MPU, _CK_MPU }, 286 { CK_AXI, _ACLK }, 287 { CK_MCU, _CK_MCU }, 288 { CK_HSE, _HSE }, 289 { CK_CSI, _CSI }, 290 { CK_LSI, _LSI }, 291 { CK_LSE, _LSE }, 292 { CK_HSI, _HSI }, 293 { CK_HSE_DIV2, _HSE_KER_DIV2 }, 294 }; 295 296 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 297 298 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 299 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 300 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 301 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 302 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 303 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 304 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 305 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 306 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 307 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 308 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 309 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 310 311 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 312 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 313 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 314 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 315 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 316 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 317 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 318 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 319 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 320 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 321 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 322 323 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 324 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 325 326 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 327 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 328 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 329 330 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 331 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 332 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 333 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 334 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 335 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 336 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 337 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 338 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 339 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 340 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 341 342 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 343 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 344 345 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 346 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 347 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 348 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 349 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 350 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 351 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 352 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 353 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 354 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 355 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 356 357 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 358 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 359 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 360 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 361 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 362 363 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 364 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 365 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 366 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 367 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 368 369 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 370 }; 371 372 static const uint8_t i2c12_parents[] = { 373 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 374 }; 375 376 static const uint8_t i2c35_parents[] = { 377 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 378 }; 379 380 static const uint8_t stgen_parents[] = { 381 _HSI_KER, _HSE_KER 382 }; 383 384 static const uint8_t i2c46_parents[] = { 385 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 386 }; 387 388 static const uint8_t spi6_parents[] = { 389 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 390 }; 391 392 static const uint8_t usart1_parents[] = { 393 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 394 }; 395 396 static const uint8_t rng1_parents[] = { 397 _CSI, _PLL4_R, _LSE, _LSI 398 }; 399 400 static const uint8_t uart6_parents[] = { 401 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 402 }; 403 404 static const uint8_t uart234578_parents[] = { 405 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 406 }; 407 408 static const uint8_t sdmmc12_parents[] = { 409 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 410 }; 411 412 static const uint8_t sdmmc3_parents[] = { 413 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 414 }; 415 416 static const uint8_t qspi_parents[] = { 417 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 418 }; 419 420 static const uint8_t fmc_parents[] = { 421 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 422 }; 423 424 static const uint8_t ass_parents[] = { 425 _HSI, _HSE, _PLL2 426 }; 427 428 static const uint8_t mss_parents[] = { 429 _HSI, _HSE, _CSI, _PLL3 430 }; 431 432 static const uint8_t usbphy_parents[] = { 433 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 434 }; 435 436 static const uint8_t usbo_parents[] = { 437 _PLL4_R, _USB_PHY_48 438 }; 439 440 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 441 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 442 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 443 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 444 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 445 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 446 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 447 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 448 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 449 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 450 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 451 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 452 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 453 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 454 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 455 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 456 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), 457 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), 458 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 459 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 460 }; 461 462 /* Define characteristic of PLL according type */ 463 #define DIVN_MIN 24 464 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 465 [PLL_800] = { 466 .refclk_min = 4, 467 .refclk_max = 16, 468 .divn_max = 99, 469 }, 470 [PLL_1600] = { 471 .refclk_min = 8, 472 .refclk_max = 16, 473 .divn_max = 199, 474 }, 475 }; 476 477 /* PLLNCFGR2 register divider by output */ 478 static const uint8_t pllncfgr2[_DIV_NB] = { 479 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 480 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 481 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 482 }; 483 484 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 485 _CLK_PLL(_PLL1, PLL_1600, 486 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 487 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 488 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 489 _CLK_PLL(_PLL2, PLL_1600, 490 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 491 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 492 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 493 _CLK_PLL(_PLL3, PLL_800, 494 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 495 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 496 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 497 _CLK_PLL(_PLL4, PLL_800, 498 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 499 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 500 _HSI, _HSE, _CSI, _I2S_CKIN), 501 }; 502 503 /* Prescaler table lookups for clock computation */ 504 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 505 static const uint8_t stm32mp1_mcu_div[16] = { 506 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 507 }; 508 509 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 510 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 511 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 512 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 513 0, 1, 2, 3, 4, 4, 4, 4 514 }; 515 516 /* div = /1 /2 /3 /4 */ 517 static const uint8_t stm32mp1_axi_div[8] = { 518 1, 2, 3, 4, 4, 4, 4, 4 519 }; 520 521 /* RCC clock device driver private */ 522 static unsigned long stm32mp1_osc[NB_OSC]; 523 static struct spinlock reg_lock; 524 static unsigned int gate_refcounts[NB_GATES]; 525 static struct spinlock refcount_lock; 526 527 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 528 { 529 return &stm32mp1_clk_gate[idx]; 530 } 531 532 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 533 { 534 return &stm32mp1_clk_sel[idx]; 535 } 536 537 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 538 { 539 return &stm32mp1_clk_pll[idx]; 540 } 541 542 static int stm32mp1_lock_available(void) 543 { 544 /* The spinlocks are used only when MMU is enabled */ 545 return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT); 546 } 547 548 static void stm32mp1_clk_lock(struct spinlock *lock) 549 { 550 if (stm32mp1_lock_available() == 0U) { 551 return; 552 } 553 554 /* Assume interrupts are masked */ 555 spin_lock(lock); 556 } 557 558 static void stm32mp1_clk_unlock(struct spinlock *lock) 559 { 560 if (stm32mp1_lock_available() == 0U) { 561 return; 562 } 563 564 spin_unlock(lock); 565 } 566 567 bool stm32mp1_rcc_is_secure(void) 568 { 569 uintptr_t rcc_base = stm32mp_rcc_base(); 570 571 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; 572 } 573 574 bool stm32mp1_rcc_is_mckprot(void) 575 { 576 uintptr_t rcc_base = stm32mp_rcc_base(); 577 578 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; 579 } 580 581 void stm32mp1_clk_rcc_regs_lock(void) 582 { 583 stm32mp1_clk_lock(®_lock); 584 } 585 586 void stm32mp1_clk_rcc_regs_unlock(void) 587 { 588 stm32mp1_clk_unlock(®_lock); 589 } 590 591 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 592 { 593 if (idx >= NB_OSC) { 594 return 0; 595 } 596 597 return stm32mp1_osc[idx]; 598 } 599 600 static int stm32mp1_clk_get_gated_id(unsigned long id) 601 { 602 unsigned int i; 603 604 for (i = 0U; i < NB_GATES; i++) { 605 if (gate_ref(i)->index == id) { 606 return i; 607 } 608 } 609 610 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 611 612 return -EINVAL; 613 } 614 615 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 616 { 617 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 618 } 619 620 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 621 { 622 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 623 } 624 625 static int stm32mp1_clk_get_parent(unsigned long id) 626 { 627 const struct stm32mp1_clk_sel *sel; 628 uint32_t j, p_sel; 629 int i; 630 enum stm32mp1_parent_id p; 631 enum stm32mp1_parent_sel s; 632 uintptr_t rcc_base = stm32mp_rcc_base(); 633 634 for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) { 635 if (stm32mp1_clks[j][0] == id) { 636 return (int)stm32mp1_clks[j][1]; 637 } 638 } 639 640 i = stm32mp1_clk_get_gated_id(id); 641 if (i < 0) { 642 panic(); 643 } 644 645 p = stm32mp1_clk_get_fixed_parent(i); 646 if (p < _PARENT_NB) { 647 return (int)p; 648 } 649 650 s = stm32mp1_clk_get_sel(i); 651 if (s == _UNKNOWN_SEL) { 652 return -EINVAL; 653 } 654 if (s >= _PARENT_SEL_NB) { 655 panic(); 656 } 657 658 sel = clk_sel_ref(s); 659 p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src; 660 if (p_sel < sel->nb_parent) { 661 return (int)sel->parent[p_sel]; 662 } 663 664 return -EINVAL; 665 } 666 667 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 668 { 669 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 670 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 671 672 return stm32mp1_clk_get_fixed(pll->refclk[src]); 673 } 674 675 /* 676 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 677 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 678 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 679 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 680 */ 681 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 682 { 683 unsigned long refclk, fvco; 684 uint32_t cfgr1, fracr, divm, divn; 685 uintptr_t rcc_base = stm32mp_rcc_base(); 686 687 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 688 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 689 690 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 691 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 692 693 refclk = stm32mp1_pll_get_fref(pll); 694 695 /* 696 * With FRACV : 697 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 698 * Without FRACV 699 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 700 */ 701 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 702 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 703 RCC_PLLNFRACR_FRACV_SHIFT; 704 unsigned long long numerator, denominator; 705 706 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 707 numerator = refclk * numerator; 708 denominator = ((unsigned long long)divm + 1U) << 13; 709 fvco = (unsigned long)(numerator / denominator); 710 } else { 711 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 712 } 713 714 return fvco; 715 } 716 717 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 718 enum stm32mp1_div_id div_id) 719 { 720 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 721 unsigned long dfout; 722 uint32_t cfgr2, divy; 723 724 if (div_id >= _DIV_NB) { 725 return 0; 726 } 727 728 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 729 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 730 731 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 732 733 return dfout; 734 } 735 736 static unsigned long get_clock_rate(int p) 737 { 738 uint32_t reg, clkdiv; 739 unsigned long clock = 0; 740 uintptr_t rcc_base = stm32mp_rcc_base(); 741 742 switch (p) { 743 case _CK_MPU: 744 /* MPU sub system */ 745 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 746 switch (reg & RCC_SELR_SRC_MASK) { 747 case RCC_MPCKSELR_HSI: 748 clock = stm32mp1_clk_get_fixed(_HSI); 749 break; 750 case RCC_MPCKSELR_HSE: 751 clock = stm32mp1_clk_get_fixed(_HSE); 752 break; 753 case RCC_MPCKSELR_PLL: 754 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 755 break; 756 case RCC_MPCKSELR_PLL_MPUDIV: 757 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 758 759 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 760 clkdiv = reg & RCC_MPUDIV_MASK; 761 if (clkdiv != 0U) { 762 clock /= stm32mp1_mpu_div[clkdiv]; 763 } 764 break; 765 default: 766 break; 767 } 768 break; 769 /* AXI sub system */ 770 case _ACLK: 771 case _HCLK2: 772 case _HCLK6: 773 case _PCLK4: 774 case _PCLK5: 775 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 776 switch (reg & RCC_SELR_SRC_MASK) { 777 case RCC_ASSCKSELR_HSI: 778 clock = stm32mp1_clk_get_fixed(_HSI); 779 break; 780 case RCC_ASSCKSELR_HSE: 781 clock = stm32mp1_clk_get_fixed(_HSE); 782 break; 783 case RCC_ASSCKSELR_PLL: 784 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 785 break; 786 default: 787 break; 788 } 789 790 /* System clock divider */ 791 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 792 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 793 794 switch (p) { 795 case _PCLK4: 796 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 797 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 798 break; 799 case _PCLK5: 800 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 801 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 802 break; 803 default: 804 break; 805 } 806 break; 807 /* MCU sub system */ 808 case _CK_MCU: 809 case _PCLK1: 810 case _PCLK2: 811 case _PCLK3: 812 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 813 switch (reg & RCC_SELR_SRC_MASK) { 814 case RCC_MSSCKSELR_HSI: 815 clock = stm32mp1_clk_get_fixed(_HSI); 816 break; 817 case RCC_MSSCKSELR_HSE: 818 clock = stm32mp1_clk_get_fixed(_HSE); 819 break; 820 case RCC_MSSCKSELR_CSI: 821 clock = stm32mp1_clk_get_fixed(_CSI); 822 break; 823 case RCC_MSSCKSELR_PLL: 824 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 825 break; 826 default: 827 break; 828 } 829 830 /* MCU clock divider */ 831 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 832 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 833 834 switch (p) { 835 case _PCLK1: 836 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 837 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 838 break; 839 case _PCLK2: 840 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 841 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 842 break; 843 case _PCLK3: 844 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 845 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 846 break; 847 case _CK_MCU: 848 default: 849 break; 850 } 851 break; 852 case _CK_PER: 853 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 854 switch (reg & RCC_SELR_SRC_MASK) { 855 case RCC_CPERCKSELR_HSI: 856 clock = stm32mp1_clk_get_fixed(_HSI); 857 break; 858 case RCC_CPERCKSELR_HSE: 859 clock = stm32mp1_clk_get_fixed(_HSE); 860 break; 861 case RCC_CPERCKSELR_CSI: 862 clock = stm32mp1_clk_get_fixed(_CSI); 863 break; 864 default: 865 break; 866 } 867 break; 868 case _HSI: 869 case _HSI_KER: 870 clock = stm32mp1_clk_get_fixed(_HSI); 871 break; 872 case _CSI: 873 case _CSI_KER: 874 clock = stm32mp1_clk_get_fixed(_CSI); 875 break; 876 case _HSE: 877 case _HSE_KER: 878 clock = stm32mp1_clk_get_fixed(_HSE); 879 break; 880 case _HSE_KER_DIV2: 881 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 882 break; 883 case _LSI: 884 clock = stm32mp1_clk_get_fixed(_LSI); 885 break; 886 case _LSE: 887 clock = stm32mp1_clk_get_fixed(_LSE); 888 break; 889 /* PLL */ 890 case _PLL1_P: 891 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 892 break; 893 case _PLL1_Q: 894 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 895 break; 896 case _PLL1_R: 897 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 898 break; 899 case _PLL2_P: 900 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 901 break; 902 case _PLL2_Q: 903 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 904 break; 905 case _PLL2_R: 906 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 907 break; 908 case _PLL3_P: 909 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 910 break; 911 case _PLL3_Q: 912 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 913 break; 914 case _PLL3_R: 915 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 916 break; 917 case _PLL4_P: 918 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 919 break; 920 case _PLL4_Q: 921 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 922 break; 923 case _PLL4_R: 924 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 925 break; 926 /* Other */ 927 case _USB_PHY_48: 928 clock = USB_PHY_48_MHZ; 929 break; 930 default: 931 break; 932 } 933 934 return clock; 935 } 936 937 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 938 { 939 uintptr_t rcc_base = stm32mp_rcc_base(); 940 941 if (gate->set_clr != 0U) { 942 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 943 } else { 944 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 945 } 946 947 VERBOSE("Clock %d has been enabled", gate->index); 948 } 949 950 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 951 { 952 uintptr_t rcc_base = stm32mp_rcc_base(); 953 954 if (gate->set_clr != 0U) { 955 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 956 BIT(gate->bit)); 957 } else { 958 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 959 } 960 961 VERBOSE("Clock %d has been disabled", gate->index); 962 } 963 964 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 965 { 966 uintptr_t rcc_base = stm32mp_rcc_base(); 967 968 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 969 } 970 971 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 972 { 973 int i = stm32mp1_clk_get_gated_id(id); 974 975 if (i < 0) { 976 panic(); 977 } 978 979 return gate_refcounts[i]; 980 } 981 982 void __stm32mp1_clk_enable(unsigned long id, bool secure) 983 { 984 const struct stm32mp1_clk_gate *gate; 985 int i = stm32mp1_clk_get_gated_id(id); 986 unsigned int *refcnt; 987 988 if (i < 0) { 989 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 990 panic(); 991 } 992 993 gate = gate_ref(i); 994 refcnt = &gate_refcounts[i]; 995 996 stm32mp1_clk_lock(&refcount_lock); 997 998 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 999 __clk_enable(gate); 1000 } 1001 1002 stm32mp1_clk_unlock(&refcount_lock); 1003 } 1004 1005 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1006 { 1007 const struct stm32mp1_clk_gate *gate; 1008 int i = stm32mp1_clk_get_gated_id(id); 1009 unsigned int *refcnt; 1010 1011 if (i < 0) { 1012 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1013 panic(); 1014 } 1015 1016 gate = gate_ref(i); 1017 refcnt = &gate_refcounts[i]; 1018 1019 stm32mp1_clk_lock(&refcount_lock); 1020 1021 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1022 __clk_disable(gate); 1023 } 1024 1025 stm32mp1_clk_unlock(&refcount_lock); 1026 } 1027 1028 void stm32mp_clk_enable(unsigned long id) 1029 { 1030 __stm32mp1_clk_enable(id, true); 1031 } 1032 1033 void stm32mp_clk_disable(unsigned long id) 1034 { 1035 __stm32mp1_clk_disable(id, true); 1036 } 1037 1038 bool stm32mp_clk_is_enabled(unsigned long id) 1039 { 1040 int i = stm32mp1_clk_get_gated_id(id); 1041 1042 if (i < 0) { 1043 panic(); 1044 } 1045 1046 return __clk_is_enabled(gate_ref(i)); 1047 } 1048 1049 unsigned long stm32mp_clk_get_rate(unsigned long id) 1050 { 1051 int p = stm32mp1_clk_get_parent(id); 1052 1053 if (p < 0) { 1054 return 0; 1055 } 1056 1057 return get_clock_rate(p); 1058 } 1059 1060 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1061 { 1062 uintptr_t address = stm32mp_rcc_base() + offset; 1063 1064 if (enable) { 1065 mmio_setbits_32(address, mask_on); 1066 } else { 1067 mmio_clrbits_32(address, mask_on); 1068 } 1069 } 1070 1071 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1072 { 1073 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1074 uintptr_t address = stm32mp_rcc_base() + offset; 1075 1076 mmio_write_32(address, mask_on); 1077 } 1078 1079 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1080 { 1081 uint64_t timeout; 1082 uint32_t mask_test; 1083 uintptr_t address = stm32mp_rcc_base() + offset; 1084 1085 if (enable) { 1086 mask_test = mask_rdy; 1087 } else { 1088 mask_test = 0; 1089 } 1090 1091 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1092 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1093 if (timeout_elapsed(timeout)) { 1094 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1095 mask_rdy, address, enable, mmio_read_32(address)); 1096 return -ETIMEDOUT; 1097 } 1098 } 1099 1100 return 0; 1101 } 1102 1103 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1104 { 1105 uint32_t value; 1106 uintptr_t rcc_base = stm32mp_rcc_base(); 1107 1108 if (digbyp) { 1109 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1110 } 1111 1112 if (bypass || digbyp) { 1113 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1114 } 1115 1116 /* 1117 * Warning: not recommended to switch directly from "high drive" 1118 * to "medium low drive", and vice-versa. 1119 */ 1120 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1121 RCC_BDCR_LSEDRV_SHIFT; 1122 1123 while (value != lsedrv) { 1124 if (value > lsedrv) { 1125 value--; 1126 } else { 1127 value++; 1128 } 1129 1130 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1131 RCC_BDCR_LSEDRV_MASK, 1132 value << RCC_BDCR_LSEDRV_SHIFT); 1133 } 1134 1135 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1136 } 1137 1138 static void stm32mp1_lse_wait(void) 1139 { 1140 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1141 VERBOSE("%s: failed\n", __func__); 1142 } 1143 } 1144 1145 static void stm32mp1_lsi_set(bool enable) 1146 { 1147 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1148 1149 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1150 VERBOSE("%s: failed\n", __func__); 1151 } 1152 } 1153 1154 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1155 { 1156 uintptr_t rcc_base = stm32mp_rcc_base(); 1157 1158 if (digbyp) { 1159 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1160 } 1161 1162 if (bypass || digbyp) { 1163 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1164 } 1165 1166 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1167 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1168 VERBOSE("%s: failed\n", __func__); 1169 } 1170 1171 if (css) { 1172 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1173 } 1174 } 1175 1176 static void stm32mp1_csi_set(bool enable) 1177 { 1178 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1179 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1180 VERBOSE("%s: failed\n", __func__); 1181 } 1182 } 1183 1184 static void stm32mp1_hsi_set(bool enable) 1185 { 1186 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1187 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1188 VERBOSE("%s: failed\n", __func__); 1189 } 1190 } 1191 1192 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1193 { 1194 uint64_t timeout; 1195 uintptr_t rcc_base = stm32mp_rcc_base(); 1196 uintptr_t address = rcc_base + RCC_OCRDYR; 1197 1198 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1199 RCC_HSICFGR_HSIDIV_MASK, 1200 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1201 1202 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1203 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1204 if (timeout_elapsed(timeout)) { 1205 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1206 address, mmio_read_32(address)); 1207 return -ETIMEDOUT; 1208 } 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int stm32mp1_hsidiv(unsigned long hsifreq) 1215 { 1216 uint8_t hsidiv; 1217 uint32_t hsidivfreq = MAX_HSI_HZ; 1218 1219 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1220 if (hsidivfreq == hsifreq) { 1221 break; 1222 } 1223 1224 hsidivfreq /= 2U; 1225 } 1226 1227 if (hsidiv == 4U) { 1228 ERROR("Invalid clk-hsi frequency\n"); 1229 return -1; 1230 } 1231 1232 if (hsidiv != 0U) { 1233 return stm32mp1_set_hsidiv(hsidiv); 1234 } 1235 1236 return 0; 1237 } 1238 1239 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1240 unsigned int clksrc, 1241 uint32_t *pllcfg, int plloff) 1242 { 1243 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1244 uintptr_t rcc_base = stm32mp_rcc_base(); 1245 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1246 enum stm32mp1_plltype type = pll->plltype; 1247 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1248 unsigned long refclk; 1249 uint32_t ifrge = 0U; 1250 uint32_t src, value, fracv; 1251 1252 /* Check PLL output */ 1253 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1254 return false; 1255 } 1256 1257 /* Check current clksrc */ 1258 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1259 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1260 return false; 1261 } 1262 1263 /* Check Div */ 1264 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1265 1266 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1267 (pllcfg[PLLCFG_M] + 1U); 1268 1269 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1270 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1271 return false; 1272 } 1273 1274 if ((type == PLL_800) && (refclk >= 8000000U)) { 1275 ifrge = 1U; 1276 } 1277 1278 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1279 RCC_PLLNCFGR1_DIVN_MASK; 1280 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1281 RCC_PLLNCFGR1_DIVM_MASK; 1282 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1283 RCC_PLLNCFGR1_IFRGE_MASK; 1284 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1285 return false; 1286 } 1287 1288 /* Fractional configuration */ 1289 fracv = fdt_read_uint32_default(plloff, "frac", 0); 1290 1291 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1292 value |= RCC_PLLNFRACR_FRACLE; 1293 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1294 return false; 1295 } 1296 1297 /* Output config */ 1298 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1299 RCC_PLLNCFGR2_DIVP_MASK; 1300 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1301 RCC_PLLNCFGR2_DIVQ_MASK; 1302 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1303 RCC_PLLNCFGR2_DIVR_MASK; 1304 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1305 return false; 1306 } 1307 1308 return true; 1309 } 1310 1311 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1312 { 1313 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1314 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1315 1316 mmio_write_32(pllxcr, RCC_PLLNCR_PLLON); 1317 } 1318 1319 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1320 { 1321 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1322 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1323 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1324 1325 /* Wait PLL lock */ 1326 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1327 if (timeout_elapsed(timeout)) { 1328 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1329 pll_id, pllxcr, mmio_read_32(pllxcr)); 1330 return -ETIMEDOUT; 1331 } 1332 } 1333 1334 /* Start the requested output */ 1335 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1336 1337 return 0; 1338 } 1339 1340 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1341 { 1342 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1343 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1344 uint64_t timeout; 1345 1346 /* Stop all output */ 1347 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1348 RCC_PLLNCR_DIVREN); 1349 1350 /* Stop PLL */ 1351 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1352 1353 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1354 /* Wait PLL stopped */ 1355 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1356 if (timeout_elapsed(timeout)) { 1357 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1358 pll_id, pllxcr, mmio_read_32(pllxcr)); 1359 return -ETIMEDOUT; 1360 } 1361 } 1362 1363 return 0; 1364 } 1365 1366 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1367 uint32_t *pllcfg) 1368 { 1369 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1370 uintptr_t rcc_base = stm32mp_rcc_base(); 1371 uint32_t value; 1372 1373 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1374 RCC_PLLNCFGR2_DIVP_MASK; 1375 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1376 RCC_PLLNCFGR2_DIVQ_MASK; 1377 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1378 RCC_PLLNCFGR2_DIVR_MASK; 1379 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1380 } 1381 1382 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1383 uint32_t *pllcfg, uint32_t fracv) 1384 { 1385 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1386 uintptr_t rcc_base = stm32mp_rcc_base(); 1387 enum stm32mp1_plltype type = pll->plltype; 1388 unsigned long refclk; 1389 uint32_t ifrge = 0; 1390 uint32_t src, value; 1391 1392 src = mmio_read_32(rcc_base + pll->rckxselr) & 1393 RCC_SELR_REFCLK_SRC_MASK; 1394 1395 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1396 (pllcfg[PLLCFG_M] + 1U); 1397 1398 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1399 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1400 return -EINVAL; 1401 } 1402 1403 if ((type == PLL_800) && (refclk >= 8000000U)) { 1404 ifrge = 1U; 1405 } 1406 1407 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1408 RCC_PLLNCFGR1_DIVN_MASK; 1409 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1410 RCC_PLLNCFGR1_DIVM_MASK; 1411 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1412 RCC_PLLNCFGR1_IFRGE_MASK; 1413 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1414 1415 /* Fractional configuration */ 1416 value = 0; 1417 mmio_write_32(rcc_base + pll->pllxfracr, value); 1418 1419 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1420 mmio_write_32(rcc_base + pll->pllxfracr, value); 1421 1422 value |= RCC_PLLNFRACR_FRACLE; 1423 mmio_write_32(rcc_base + pll->pllxfracr, value); 1424 1425 stm32mp1_pll_config_output(pll_id, pllcfg); 1426 1427 return 0; 1428 } 1429 1430 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1431 { 1432 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1433 uint32_t pllxcsg = 0; 1434 1435 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1436 RCC_PLLNCSGR_MOD_PER_MASK; 1437 1438 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1439 RCC_PLLNCSGR_INC_STEP_MASK; 1440 1441 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1442 RCC_PLLNCSGR_SSCG_MODE_MASK; 1443 1444 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1445 } 1446 1447 static int stm32mp1_set_clksrc(unsigned int clksrc) 1448 { 1449 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1450 uint64_t timeout; 1451 1452 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1453 clksrc & RCC_SELR_SRC_MASK); 1454 1455 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1456 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1457 if (timeout_elapsed(timeout)) { 1458 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1459 clksrc_address, mmio_read_32(clksrc_address)); 1460 return -ETIMEDOUT; 1461 } 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1468 { 1469 uint64_t timeout; 1470 1471 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1472 clkdiv & RCC_DIVR_DIV_MASK); 1473 1474 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1475 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1476 if (timeout_elapsed(timeout)) { 1477 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1478 clkdiv, address, mmio_read_32(address)); 1479 return -ETIMEDOUT; 1480 } 1481 } 1482 1483 return 0; 1484 } 1485 1486 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1487 { 1488 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1489 1490 /* 1491 * Binding clksrc : 1492 * bit15-4 offset 1493 * bit3: disable 1494 * bit2-0: MCOSEL[2:0] 1495 */ 1496 if ((clksrc & 0x8U) != 0U) { 1497 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1498 } else { 1499 mmio_clrsetbits_32(clksrc_address, 1500 RCC_MCOCFG_MCOSRC_MASK, 1501 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1502 mmio_clrsetbits_32(clksrc_address, 1503 RCC_MCOCFG_MCODIV_MASK, 1504 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1505 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1506 } 1507 } 1508 1509 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1510 { 1511 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1512 1513 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1514 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1515 mmio_clrsetbits_32(address, 1516 RCC_BDCR_RTCSRC_MASK, 1517 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1518 1519 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1520 } 1521 1522 if (lse_css) { 1523 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1524 } 1525 } 1526 1527 static void stm32mp1_stgen_config(void) 1528 { 1529 uintptr_t stgen; 1530 uint32_t cntfid0; 1531 unsigned long rate; 1532 unsigned long long counter; 1533 1534 stgen = fdt_get_stgen_base(); 1535 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1536 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1537 1538 if (cntfid0 == rate) { 1539 return; 1540 } 1541 1542 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1543 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); 1544 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; 1545 counter = (counter * rate / cntfid0); 1546 1547 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1548 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1549 mmio_write_32(stgen + CNTFID_OFF, rate); 1550 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1551 1552 write_cntfrq((u_register_t)rate); 1553 1554 /* Need to update timer with new frequency */ 1555 generic_delay_timer_init(); 1556 } 1557 1558 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1559 { 1560 uintptr_t stgen; 1561 unsigned long long cnt; 1562 1563 stgen = fdt_get_stgen_base(); 1564 1565 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1566 mmio_read_32(stgen + CNTCVL_OFF); 1567 1568 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1569 1570 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1571 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1572 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1573 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1574 } 1575 1576 static void stm32mp1_pkcs_config(uint32_t pkcs) 1577 { 1578 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1579 uint32_t value = pkcs & 0xFU; 1580 uint32_t mask = 0xFU; 1581 1582 if ((pkcs & BIT(31)) != 0U) { 1583 mask <<= 4; 1584 value <<= 4; 1585 } 1586 1587 mmio_clrsetbits_32(address, mask, value); 1588 } 1589 1590 int stm32mp1_clk_init(void) 1591 { 1592 uintptr_t rcc_base = stm32mp_rcc_base(); 1593 unsigned int clksrc[CLKSRC_NB]; 1594 unsigned int clkdiv[CLKDIV_NB]; 1595 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1596 int plloff[_PLL_NB]; 1597 int ret, len; 1598 enum stm32mp1_pll_id i; 1599 bool lse_css = false; 1600 bool pll3_preserve = false; 1601 bool pll4_preserve = false; 1602 bool pll4_bootrom = false; 1603 const fdt32_t *pkcs_cell; 1604 1605 /* Check status field to disable security */ 1606 if (!fdt_get_rcc_secure_status()) { 1607 mmio_write_32(rcc_base + RCC_TZCR, 0); 1608 } 1609 1610 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, 1611 (uint32_t)CLKSRC_NB); 1612 if (ret < 0) { 1613 return -FDT_ERR_NOTFOUND; 1614 } 1615 1616 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, 1617 (uint32_t)CLKDIV_NB); 1618 if (ret < 0) { 1619 return -FDT_ERR_NOTFOUND; 1620 } 1621 1622 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1623 char name[12]; 1624 1625 snprintf(name, sizeof(name), "st,pll@%d", i); 1626 plloff[i] = fdt_rcc_subnode_offset(name); 1627 1628 if (!fdt_check_node(plloff[i])) { 1629 continue; 1630 } 1631 1632 ret = fdt_read_uint32_array(plloff[i], "cfg", 1633 pllcfg[i], (int)PLLCFG_NB); 1634 if (ret < 0) { 1635 return -FDT_ERR_NOTFOUND; 1636 } 1637 } 1638 1639 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1640 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1641 1642 /* 1643 * Switch ON oscillator found in device-tree. 1644 * Note: HSI already ON after BootROM stage. 1645 */ 1646 if (stm32mp1_osc[_LSI] != 0U) { 1647 stm32mp1_lsi_set(true); 1648 } 1649 if (stm32mp1_osc[_LSE] != 0U) { 1650 bool bypass, digbyp; 1651 uint32_t lsedrv; 1652 1653 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1654 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1655 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1656 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1657 LSEDRV_MEDIUM_HIGH); 1658 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1659 } 1660 if (stm32mp1_osc[_HSE] != 0U) { 1661 bool bypass, digbyp, css; 1662 1663 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1664 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1665 css = fdt_osc_read_bool(_HSE, "st,css"); 1666 stm32mp1_hse_enable(bypass, digbyp, css); 1667 } 1668 /* 1669 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1670 * => switch on CSI even if node is not present in device tree 1671 */ 1672 stm32mp1_csi_set(true); 1673 1674 /* Come back to HSI */ 1675 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1676 if (ret != 0) { 1677 return ret; 1678 } 1679 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1680 if (ret != 0) { 1681 return ret; 1682 } 1683 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1684 if (ret != 0) { 1685 return ret; 1686 } 1687 1688 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1689 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1690 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1691 clksrc[CLKSRC_PLL3], 1692 pllcfg[_PLL3], 1693 plloff[_PLL3]); 1694 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1695 clksrc[CLKSRC_PLL4], 1696 pllcfg[_PLL4], 1697 plloff[_PLL4]); 1698 } 1699 1700 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1701 if (((i == _PLL3) && pll3_preserve) || 1702 ((i == _PLL4) && pll4_preserve)) { 1703 continue; 1704 } 1705 1706 ret = stm32mp1_pll_stop(i); 1707 if (ret != 0) { 1708 return ret; 1709 } 1710 } 1711 1712 /* Configure HSIDIV */ 1713 if (stm32mp1_osc[_HSI] != 0U) { 1714 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1715 if (ret != 0) { 1716 return ret; 1717 } 1718 stm32mp1_stgen_config(); 1719 } 1720 1721 /* Select DIV */ 1722 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1723 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1724 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1725 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1726 if (ret != 0) { 1727 return ret; 1728 } 1729 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1730 if (ret != 0) { 1731 return ret; 1732 } 1733 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1734 if (ret != 0) { 1735 return ret; 1736 } 1737 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1738 if (ret != 0) { 1739 return ret; 1740 } 1741 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1742 if (ret != 0) { 1743 return ret; 1744 } 1745 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1746 if (ret != 0) { 1747 return ret; 1748 } 1749 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1750 if (ret != 0) { 1751 return ret; 1752 } 1753 1754 /* No ready bit for RTC */ 1755 mmio_write_32(rcc_base + RCC_RTCDIVR, 1756 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1757 1758 /* Configure PLLs source */ 1759 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1760 if (ret != 0) { 1761 return ret; 1762 } 1763 1764 if (!pll3_preserve) { 1765 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1766 if (ret != 0) { 1767 return ret; 1768 } 1769 } 1770 1771 if (!pll4_preserve) { 1772 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1773 if (ret != 0) { 1774 return ret; 1775 } 1776 } 1777 1778 /* Configure and start PLLs */ 1779 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1780 uint32_t fracv; 1781 uint32_t csg[PLLCSG_NB]; 1782 1783 if (((i == _PLL3) && pll3_preserve) || 1784 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1785 continue; 1786 } 1787 1788 if (!fdt_check_node(plloff[i])) { 1789 continue; 1790 } 1791 1792 if ((i == _PLL4) && pll4_bootrom) { 1793 /* Set output divider if not done by the Bootrom */ 1794 stm32mp1_pll_config_output(i, pllcfg[i]); 1795 continue; 1796 } 1797 1798 fracv = fdt_read_uint32_default(plloff[i], "frac", 0); 1799 1800 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1801 if (ret != 0) { 1802 return ret; 1803 } 1804 ret = fdt_read_uint32_array(plloff[i], "csg", csg, 1805 (uint32_t)PLLCSG_NB); 1806 if (ret == 0) { 1807 stm32mp1_pll_csg(i, csg); 1808 } else if (ret != -FDT_ERR_NOTFOUND) { 1809 return ret; 1810 } 1811 1812 stm32mp1_pll_start(i); 1813 } 1814 /* Wait and start PLLs ouptut when ready */ 1815 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1816 if (!fdt_check_node(plloff[i])) { 1817 continue; 1818 } 1819 1820 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1821 if (ret != 0) { 1822 return ret; 1823 } 1824 } 1825 /* Wait LSE ready before to use it */ 1826 if (stm32mp1_osc[_LSE] != 0U) { 1827 stm32mp1_lse_wait(); 1828 } 1829 1830 /* Configure with expected clock source */ 1831 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1832 if (ret != 0) { 1833 return ret; 1834 } 1835 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1836 if (ret != 0) { 1837 return ret; 1838 } 1839 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1840 if (ret != 0) { 1841 return ret; 1842 } 1843 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1844 1845 /* Configure PKCK */ 1846 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1847 if (pkcs_cell != NULL) { 1848 bool ckper_disabled = false; 1849 uint32_t j; 1850 1851 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1852 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1853 1854 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1855 ckper_disabled = true; 1856 continue; 1857 } 1858 stm32mp1_pkcs_config(pkcs); 1859 } 1860 1861 /* 1862 * CKPER is source for some peripheral clocks 1863 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1864 * only if previous clock is still ON 1865 * => deactivated CKPER only after switching clock 1866 */ 1867 if (ckper_disabled) { 1868 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 1869 } 1870 } 1871 1872 /* Switch OFF HSI if not found in device-tree */ 1873 if (stm32mp1_osc[_HSI] == 0U) { 1874 stm32mp1_hsi_set(false); 1875 } 1876 stm32mp1_stgen_config(); 1877 1878 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1879 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 1880 RCC_DDRITFCR_DDRCKMOD_MASK, 1881 RCC_DDRITFCR_DDRCKMOD_SSR << 1882 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1883 1884 return 0; 1885 } 1886 1887 static void stm32mp1_osc_clk_init(const char *name, 1888 enum stm32mp_osc_id index) 1889 { 1890 uint32_t frequency; 1891 1892 if (fdt_osc_read_freq(name, &frequency) == 0) { 1893 stm32mp1_osc[index] = frequency; 1894 } 1895 } 1896 1897 static void stm32mp1_osc_init(void) 1898 { 1899 enum stm32mp_osc_id i; 1900 1901 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1902 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 1903 } 1904 } 1905 1906 int stm32mp1_clk_probe(void) 1907 { 1908 stm32mp1_osc_init(); 1909 1910 return 0; 1911 } 1912