feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region

feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region definition through DT.

Change-Id: I1bca9c0a89af88a72651e1a71e3f8950807eec40
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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fix(st-crypto): resolve MISRA warning in HASH

Resolve folowing MISRA warning in stm32_hash :
MISRA-c2012-10.3 MISRA-c2012-10.4 MISRA-c2012-17.7 MISRA-c2012-17.8
MISRA-c2012-18.4 MISRA-c2012-21.15

S

fix(st-crypto): resolve MISRA warning in HASH

Resolve folowing MISRA warning in stm32_hash :
MISRA-c2012-10.3 MISRA-c2012-10.4 MISRA-c2012-17.7 MISRA-c2012-17.8
MISRA-c2012-18.4 MISRA-c2012-21.15

Signed-off-by: Thomas BOURGOIN <thomas.bourgoin@foss.st.com>
Change-Id: Ia37b5b0f706701ca2827d47c9360dfcf83a48fc0

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fix(st-crypto): improve RNG health test configuration

The default health test configuration in RNG_HTCR is not good enough.
It implies too many zero random generations.
Set a better value to improve

fix(st-crypto): improve RNG health test configuration

The default health test configuration in RNG_HTCR is not good enough.
It implies too many zero random generations.
Set a better value to improve the IP behavior.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I7e05e52466be68fdbf5439931a9f01dcfa57a24d

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feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instanc

feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instance for the TF-A
purpose as it needs only one to work. The others are activated because
needed by specific IPs.

Seed errors are now also checked after null data read. The Reference
Manual recommends to always verify that RNG_DR is different from zero.
Because when it is the case a seed error can occur between RNG_SR
polling and RND_DR output reading (rare event).

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Ie4d7f01f4ffe5a9e2d0e5e7317b008edd3b80a17

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fix(dcc): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(dcc): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Iba1627367d9bb8c2f5e4a9d45de96dd891356abc
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signe

feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I39e366ed1988847bfa288adc0732d9b864e58bbd

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fix(console): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement. Enclosed statement bod

fix(console): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement. Enclosed statement body within the curly
braces.

Change-Id: I3fffc660cae07ae386d36bad46ae1d528a17b630
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes from topic "xlnx_fix_gen_op_datatype" into integration

* changes:
fix(el3-runtime): typecast operands to match data type
fix(arm): typecast operands to match data type

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I7a2565ce6b8beb71dc9c711327ab72ce825111cc
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(tpm): extend timeout before reading data

- extended timeout before reading data from timeout_msec_c (200ms) to timeout_msec_a (750ms)
- new timeout is compatible with spec and avoids incorrect b

fix(tpm): extend timeout before reading data

- extended timeout before reading data from timeout_msec_c (200ms) to timeout_msec_a (750ms)
- new timeout is compatible with spec and avoids incorrect behavior

Change-Id: I35a44e93a331a11fcab32b3b64c2adf770e5951d
Signed-off-by: Jenna May <jenna.may@arm.com>

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Merge "fix(mhu): shift by minor revision offset" into integration

Merge "feat(nxp-mmc): add timeout to blocking loops" into integration

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A0

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A009663 was not applied due to missing define.

Change-Id: I4f3669adf02dea487f89f81d2fc7344bb65f830d
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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Merge changes from topic "xlnx_fix_gen_con_datatype" into integration

* changes:
fix(console): typecast operands to match data type
fix(console): typecast operands to match data type

feat(nxp-mmc): add timeout to blocking loops

Replace all register polling loops with timeout-enabled versions,
allowing the caller to decide whether to panic or handle the error
gracefully.

Change-

feat(nxp-mmc): add timeout to blocking loops

Replace all register polling loops with timeout-enabled versions,
allowing the caller to decide whether to panic or handle the error
gracefully.

Change-Id: If296f06a20cb849e690d1193bda1378508d3f7e0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(nxp-crypto): restricts generating nxp_mkvb via ns-world" into integration

Merge "feat(dsu): support power control and autonomous powerdown config" into integration

fix(arm-drivers): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o

fix(arm-drivers): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I6464ba742af81a2fffe9782d032275486d32f3a1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

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fix(nxp-mmc): handle response for CMD0

Fixed a regression introduced by commit
a59d43fc222d ("refactor(nxp-mmc): populate command transfer type").

The commit incorrectly assumes that all commands w

fix(nxp-mmc): handle response for CMD0

Fixed a regression introduced by commit
a59d43fc222d ("refactor(nxp-mmc): populate command transfer type").

The commit incorrectly assumes that all commands will have a response
type, which is not always the case. For instance, Command 0 (used to
reset the card and enter idle state) does not expect a response. As a
result, the response type field will be explicitly set to zero in
such cases.

Change-Id: Id97b765b9720bbd02fafb30a271f134536fab5a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(mmc): replace 0 with MMC_RESPONSE_NONE

Use the newly introduced MMC_RESPONSE_NONE macro for Command 0,
where no response is expected.

Change-Id: I861a1bd009ea131677a23e2d94ea27bff3653360
S

refactor(mmc): replace 0 with MMC_RESPONSE_NONE

Use the newly introduced MMC_RESPONSE_NONE macro for Command 0,
where no response is expected.

Change-Id: I861a1bd009ea131677a23e2d94ea27bff3653360
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-

feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and trig

feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and triggers as well as to map the config frame in device
nGnRnE memory. All wires will default to the NS domain and the platform
can override this.

Change-Id: I93aec5809aec4328d1cba832c2c6e5891e398e5b
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to m

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to map the config frame in device nGnRnE
memory. All wires will default to NS and the platform may override this.

Change-Id: Icbd43503753cd76fd3d80ed47eba6926494bc323
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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