fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes

While ICC_SRE_EL2.SRE is 0, ICC_SRE_EL1.SRE is RAZ/WI. Except for an
isb between the two writes, there is nothing to guarantee t

fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes

While ICC_SRE_EL2.SRE is 0, ICC_SRE_EL1.SRE is RAZ/WI. Except for an
isb between the two writes, there is nothing to guarantee that the
ICC_SRE_EL2.SRE write has taken effect by the time the ICC_SRE_EL1.SRE
write occurs. Add the isb to guarantee that the write is successful.

Change-Id: Ib84193f49e67ed0a64d6e2c6c71fb99b5b58a211
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-I

fix(gic): fix coverity issue INTEGER_OVERFLOW

Avoid unsigned underflow when spi_id_min is below the base.
Make all shifts in the CHIPR value composition 64-bit, to
avoid flagging overflow.

Change-Id: I376809fc110ff45dd0682b4bcf8dab43cf03d300
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02

feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02557ba7569a536cece37e4c1fe98
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(gicv3): avoid incrementing global gicr_frames pointer

commit 75170704c9119a4947 (refactor(gicv3): clarify redistributor base
address usage with USE_GIC_DRIVER=3) introduced changes to walk the
r

fix(gicv3): avoid incrementing global gicr_frames pointer

commit 75170704c9119a4947 (refactor(gicv3): clarify redistributor base
address usage with USE_GIC_DRIVER=3) introduced changes to walk the
redistributor frames by incrementing the global `gicr_frames` pointer.
This leaves the pointer advanced after the first miss, so subsequent
CPUs do not start from the beginning of the array. Such behaviour is
incorrect in the presence of CPU hotplug or out-of-order CPU_ON
operations, where each CPU must be able to probe the full set of
redistributor frames independently.

Fix this by using a local iterator instead of modifying the global
`gicr_frames` pointer, preserving the array state for all CPUs.

While here, fix a typo in a comment and replace the `do…while`
loop with a safer `while` loop to avoid probing the zero terminator in
case a platform erroneously passes an empty array.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I6d6f73fb172c48f8e50b29ec2232648be3a6a6a0

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Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

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fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Icd480587b74c0e0a818498b680666ed43e94fef8
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body w

fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I657780b0e322a0aff990390a8dfc1af56dfd5c1d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpect

fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpected behavior
due to operator precedence and which improves the readibility and
maintainability.

Change-Id: I8d09f136faae2869fc1ef2d6eb46de035b7e6a1e
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction declerati

fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction decleration and definition should be match to
avoid conflicts.

Change-Id: Ic6cff6719a38dffe78e4756d3bb7cf32512c5344
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(gic): change gic_cpuif_enable/disable to weak

For some platform like NXP i.MX94/95, the gic cpu interface
enable & disable need some special handling except the generic
gic_cpuif_enable/disable

feat(gic): change gic_cpuif_enable/disable to weak

For some platform like NXP i.MX94/95, the gic cpu interface
enable & disable need some special handling except the generic
gic_cpuif_enable/disable API. To allow these platform to reuse
the generic gic driver support, need to mark these two APIs as weak
to allow platforms to provide platform specific implementation.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I742fcb60bef20b051363f1fa86c6254e2f463129

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signe

feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I39e366ed1988847bfa288adc0732d9b864e58bbd

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fix(gic): quote the correct flag on error

Generic GIC driver files should use the USE_GIC_DRIVER flag. When that's
not the case, the correct flag should be quotes to avoid confusion.

Change-Id: I0b

fix(gic): quote the correct flag on error

Generic GIC driver files should use the USE_GIC_DRIVER flag. When that's
not the case, the correct flag should be quotes to avoid confusion.

Change-Id: I0b0443d52c0b0e81d7b380285a278ffdeae17ca3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore: fix preprocessor checks

We can also drop the preprocessor check from plat_gic_init - it was
introduced because the tsp needed to call this function on gicv2 but not
gicv3 and this was the cle

chore: fix preprocessor checks

We can also drop the preprocessor check from plat_gic_init - it was
introduced because the tsp needed to call this function on gicv2 but not
gicv3 and this was the cleanest way to filter this out. Now that we have
the generic driver, the caller has all the tools to cater for this.
Callers have been converted so this is redundant.

Also, the FVP observes different behaviour on debug and release builds
in regards to the contents of plat_params_from_bl2. Make this explicit
so that release builds with ENABLE_ASSERTIONS=1 are possible.

Change-Id: I86959e67460d0c25c558f33c08e6233a8b6eeb7f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - c

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - calling
the top-level helpers from plat/arm/common/arm_gicvX.c or by using the
driver directly. Both of these methods allow for a high degree of
customisation - most functions are defined to be weak and there are no
calls to any of them in generic code.

As it turns out, requirements around those GICs are largely the same.
Platforms that use arm_gicvX.c use the helpers identically among each
other. Platforms that use the driver directly tend to end up with calls
that look a lot like the arm_gicvX.c helpers and the weakness of the
functions are never exercised.

All of this results in a lot of code duplication to do what is
essentially the same thing. Even though it's not a lot of code, when
multiplied among many platforms it becomes significant and makes
refactoring it quite difficult. It's also bug prone since the steps are
a little convoluted and things are likely to work even with subtle
errors (see 50009f61177421118f42d6a000611ba0e613d54b).

So promote as much of the GIC to be called from common code. Do the
setup in bl31_main() and have every PSCI method do the state management
directly instead of delegating it to the platform hooks. We can base
this implementation on arm_gicvX.c since they already offer logical
names and have worked quite well so far with minimal changes.

The main benefit of doing this is reduced code duplication. If we assume
that, outside of some platform setup, GIC management is identical, then
a platform can add support by telling the build system, regardless of
GIC revision. The other benefit is performance - BL31 and PSCI already
know the core_pos and they can pass it as an argument instead of having
to call plat_my_core_pos(). Now, the only platform specific GIC actions
necessary are the saving and restoring of context on entering and
exiting a power domain. The PSCI library does not keep track of this so
it is unable perform it itself. The routines themselves are also
provided.

For compatibility all of this is hidden behind a build flag. Platforms
are encouraged to adopt this driver, but it would not be practical to
convert and validate every GIC based platform.

This patch renames the functions in question to follow the
gic_<function>() convention. This allows the names to be version
agnostic.

Finally, drop the weak definitions - they are unused, likely to remain
so, and can be added back if the need arises.

Change-Id: I5b5267f4b72f633fb1096400ec8e4b208694135f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add suppo

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add support for local chip addressing

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feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version

feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.

The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.

On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.

Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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