| 9d4819a0 | 29-Nov-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(cpus): workaround for Neoverse V2 erratum 2662553" into integration |
| 324a63cd | 29-Nov-2023 |
Yann Gautier <yann.gautier@st.com> |
Merge "fix(docs): revise the description of REGISTER_CRYPTO_LIB" into integration |
| 5710229f | 29-Nov-2023 |
zhiyang.shi <zhiyang.shi@cixtech.com> |
fix(docs): revise the description of REGISTER_CRYPTO_LIB
verify_hash should be placed before calc_hash
align with crypto_mod.h
Change-Id: I536125502d83bb732cf70fbe516d5fe009dc95fe
Signed-off-by: zh
fix(docs): revise the description of REGISTER_CRYPTO_LIB
verify_hash should be placed before calc_hash
align with crypto_mod.h
Change-Id: I536125502d83bb732cf70fbe516d5fe009dc95fe
Signed-off-by: zhiyang.shi <zhiyang.shi@cixtech.com>
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| ad866942 | 28-Nov-2023 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(security): add support for SLS mitigation" into integration |
| 5305809a | 27-Nov-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "sm/errata" into integration
* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workarou
Merge changes from topic "sm/errata" into integration
* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workaround for Cortex-X3 erratum 2779509
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| 5fddf53c | 23-Nov-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "mb/deprecate-rss-for-fvp" into integration
* changes:
refactor(fvp): remove RSS usage
refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option |
| 98735809 | 21-Nov-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(changelog): changelog for v2.10 release
Added changelog for v2.10 release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
docs(changelog): changelog for v2.10 release
Added changelog for v2.10 release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Id06263047fcc1ec60e82f85cd09e2e4bc95830f5
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| 538516f5 | 28-Sep-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
feat(security): add support for SLS mitigation
This patch enables support for the gcc compiler option "-mharden-sls",
the default is not to use this option. Setting HARDEN_SLS=1 sets
"-mharden-sls=a
feat(security): add support for SLS mitigation
This patch enables support for the gcc compiler option "-mharden-sls",
the default is not to use this option. Setting HARDEN_SLS=1 sets
"-mharden-sls=all" that enables all hardening against straight line
speculation.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I59f5963c22431571f5aebe7e0c5642b32362f4c9
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| 912c4090 | 17-Oct-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V2 erratum 2662553
Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size s
fix(cpus): workaround for Neoverse V2 erratum 2662553
Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size statically to it's full size.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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|
| ccd8c023 | 21-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Revert "docs(changelog): changelog for v2.10 release"" into integration |
| 256c1c60 | 21-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Revert "docs(changelog): changelog for v2.10 release"
This reverts commit 0abbfab320344d4f2110e95d64863a3e82a51ec9.
Reason for revert: Changelog was based on rc0 tag but we got few more patches aft
Revert "docs(changelog): changelog for v2.10 release"
This reverts commit 0abbfab320344d4f2110e95d64863a3e82a51ec9.
Reason for revert: Changelog was based on rc0 tag but we got few more patches after that which were not captured.
Change-Id: I9829f2b6dc09f0bd5c538845cbae051f6e4c8a75
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| b54f7376 | 21-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs(threat-model): add a threat model for TF-A with Arm CCA" into integration |
| 61647ed4 | 21-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(tc): deprecate Arm TC1 FVP platform" into integration |
| 81d4094d | 14-Nov-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Cortex-A78C erratum 2743232
Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1
fix(cpus): workaround for Cortex-A78C erratum 2743232
Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest
Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| 71ed9173 | 07-Nov-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Neoverse V1 erratum 2348377
Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL
fix(cpus): workaround for Neoverse V1 erratum 2348377
Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest
Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| 355ce0a4 | 06-Nov-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Cortex-X3 erratum 2779509
Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUA
fix(cpus): workaround for Cortex-X3 erratum 2779509
Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUACTLR3_EL1[47], this might have a small
impact on power and has negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| b8a01c99 | 20-Nov-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "docs(changelog): changelog for v2.10 release" into integration |
| 6a2b11c2 | 20-Nov-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(tc): deprecate Arm TC1 FVP platform
Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platfor
refactor(tc): deprecate Arm TC1 FVP platform
Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platform have been officially discontinued.
The TC1 platform, now considered obsolete, has been succeeded by
the TC2 platform. It's noteworthy that the TC2 platform is already
integrated and supported in both TF-A and CI repositories.
Change-Id: Ia196a5fc975b4dbf3c913333daf595199968d95d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 0abbfab3 | 10-Nov-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
docs(changelog): changelog for v2.10 release
Change-Id: I44b88c3232d099b85ff71ee14c4918c4f8180146
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> |
| d840ae5d | 20-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "hm/rt-instr" into integration
* changes:
docs(juno): update PSCI instrumentation data
docs(n1sdp): update N1SDP PSCI instrumentation data |
| 10b545b2 | 20-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: add a section for experimental build options" into integration |
| 4281d02f | 16-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs(fvp): update model version documentation" into integration |
| 48856003 | 03-Nov-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
docs: add a section for experimental build options
A number of features are marked experimental in the build system through
makefiles but there wasn't an explicit document to list them.
Added a dedi
docs: add a section for experimental build options
A number of features are marked experimental in the build system through
makefiles but there wasn't an explicit document to list them.
Added a dedicated experimental build options section and moved
existing experimental build option descriptions in this section.
Restoring the change from [1] removing the experimental flag on the EL3
SPMC (this has been lost in rebasing a later change).
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24713
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2c458c6857c347114b265404e8b9ede9ac588463
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| 539c29a8 | 16-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(docs): update maintainers list" into integration |
| 9766f41d | 15-Nov-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(docs): update maintainers list
As part of the release process, revisit the list of maintainers to
keep it updated.
Change-Id: Ifdbbe0d0dd1c8db3e5fbc84affcceb6d3c7716d4
Signed-off-by: Bipin Ravi
fix(docs): update maintainers list
As part of the release process, revisit the list of maintainers to
keep it updated.
Change-Id: Ifdbbe0d0dd1c8db3e5fbc84affcceb6d3c7716d4
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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