| 6a4afebb | 23-Apr-2024 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(cpus): workaround for Cortex-X4 erratum 2740089" into integration |
| 8acdb13a | 23-Apr-2024 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(cpus): workaround for Cortex-A715 erratum 2728106" into integration |
| c643188f | 18-Apr-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
docs(mte2): update docs
Add a section under release for capturing and populating build options that are deprecated and removed.
Various fixes and refactor[1] led to removal of certain MTE build opt
docs(mte2): update docs
Add a section under release for capturing and populating build options that are deprecated and removed.
Various fixes and refactor[1] led to removal of certain MTE build options so capture this part in build-options docs.
[1]: https://review.trustedfirmware.org/q/topic:%22mte_fixes%22
Change-Id: I74a82f6f73f7f1dceea65a295ad2df60301ad838 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 624c9a0b | 21-Feb-2024 |
Tamas Ban <tamas.ban@arm.com> |
docs: change all occurrences of RSS to RSE
Changes all occurrences of "RSS" and "rss" in the documentation to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: Ia42078f5faa1d
docs: change all occurrences of RSS to RSE
Changes all occurrences of "RSS" and "rss" in the documentation to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: Ia42078f5faa1db331b1e5a35f01faeaf1afacb5f
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| a5a5947a | 21-Feb-2024 |
Tamas Ban <tamas.ban@arm.com> |
docs: rename all 'rss' files to 'rse'
Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: I93877ebeca1db6ee27dcb5446cc1f1a1e4e56775 |
| 75093b72 | 11-Apr-2024 |
Harrison Mutai <harrison.mutai@arm.com> |
docs(fconf): add TB_FW config bindings
Document bindings for TB_FW_CONFIG that are common between platforms. Since the information this device tree type contains pertains to firmware specific proper
docs(fconf): add TB_FW config bindings
Document bindings for TB_FW_CONFIG that are common between platforms. Since the information this device tree type contains pertains to firmware specific properties, we do not expect that the document will cover all uses, nor do we promise backward compatiblity.
Change-Id: I0e850c13b77cc62940ab5020a15bf8e503568ed8 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| c5407693 | 23-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs(fvp): restructure FVP platform documentation
The Arm FVP documentation has grown organically over the years. As a result, it has become a big document, which can be difficult to digest.
Also,
docs(fvp): restructure FVP platform documentation
The Arm FVP documentation has grown organically over the years. As a result, it has become a big document, which can be difficult to digest.
Also, the organization of some of the sections does not make sense. In particular, all "Running on the ... FVP" sections live under a section named "Booting a preloaded kernel image (Base FVP)". To illustrate this, here is the current table of contents:
Arm Fixed Virtual Platforms (FVP) Fixed Virtual Platform (FVP) Support Arm FVP Platform Specific Build Options Booting Firmware Update images Booting an EL3 payload Booting a preloaded kernel image (Base FVP) Obtaining the Flattened Device Treesp Running on the Foundation FVP with reset to BL1 entrypoint Running on the AEMv8 Base FVP with reset to BL1 entrypoint Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint Running on the AEMv8 Base FVP with reset to BL31 entrypoint Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
This patch breaks down this document in sub-documents, which are now included from the index file. The table of contents (ToC) reflects the new documents hierarchy. The depth of the ToC has been reduced to simplify the index page. Here is what it looks like now:
Arm Fixed Virtual Platforms (FVP) Fixed Virtual Platform (FVP) Support Arm FVP Platform Specific Build Options Running on the Foundation FVP Running on the AEMv8 Base FVP Running on the Cortex-A57-A53 Base FVP Running on the Cortex-A32 Base FVP (AArch32) Booting Firmware Update images Booting an EL3 payload Booting a preloaded kernel image (Base FVP)
Apart from moving information around in separate files, this patch also makes the following minor changes to the contents:
- Add a brief introduction about FVPs in the index page. - Change some of the titles names for conciseness.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Icb650e0ec2c7a86ccd6e7eea4e16a84c41442c96
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| 9728f991 | 19-Apr-2024 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "docs(plat): remove TC1 entry from the deprecation table" into integration |
| 4a20d5cb | 19-Apr-2024 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(plat): remove TC1 entry from the deprecation table
Since the TC1 platform has been eliminated from the TF-A source code and CI script repository, updated the deprecation table to remove its ent
docs(plat): remove TC1 entry from the deprecation table
Since the TC1 platform has been eliminated from the TF-A source code and CI script repository, updated the deprecation table to remove its entry.
Change-Id: I93ae03e1f810666e9a6d0c6172a322ff1e960c71 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| c833ca66 | 10-Apr-2024 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X4 erratum 2740089
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to all revisions <=r0p1 and is fixed in r0p2. The workaround is to insert a dsb before t
fix(cpus): workaround for Cortex-X4 erratum 2740089
Cortex-X4 erratum 2740089 is a Cat B erratum that applies to all revisions <=r0p1 and is fixed in r0p2. The workaround is to insert a dsb before the isb in the power down sequence.
SDEN documentation: https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| c8be7c08 | 18-Apr-2024 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(docs): typo in the romlib design" into integration |
| 3b57ae23 | 18-Apr-2024 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(docs): typo in the romlib design
There's a typo in the romlib design document when referring to the generator script. It should be romlib_generator.py instead of romlib_generate.py so fixed this
fix(docs): typo in the romlib design
There's a typo in the romlib design document when referring to the generator script. It should be romlib_generator.py instead of romlib_generate.py so fixed this typo.
Change-Id: I6db7ee66b13c2b0b9d8511da7e0d1b058366281b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 1b86ec5b | 15-Apr-2024 |
Harrison Mutai <harrison.mutai@arm.com> |
docs: decrease the minimum supported OpenSSL
Our code does not preclude the use of versions 1.0.x of OpenSSL. Instead, we discourage it's use due to security concerns. Update the documentation to re
docs: decrease the minimum supported OpenSSL
Our code does not preclude the use of versions 1.0.x of OpenSSL. Instead, we discourage it's use due to security concerns. Update the documentation to reflect this.
Change-Id: I5c60907337f10b05d5c43b0384247c5d4135db50 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| e75e5935 | 16-Apr-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs(build): update GCC to 13.2.Rel1 version" into integration |
| 10134e35 | 10-Apr-2024 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A715 erratum 2728106
Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
The workaround is to
fix(cpus): workaround for Cortex-A715 erratum 2728106
Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
The workaround is to execute an implementation specific sequence in the CPU.
SDEN documentation: https://developer.arm.com/documentation/SDEN2148827/latest
Change-Id: Ic825f9942e7eb13893fdbb44a2090b897758cbc4 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| 90801842 | 05-Apr-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
docs(build): update GCC to 13.2.Rel1 version
Updating toolchain to the latest production release version 13.2.Rel1 publicly available on: https://developer.arm.com/downloads/-/arm-gnu-toolchain-down
docs(build): update GCC to 13.2.Rel1 version
Updating toolchain to the latest production release version 13.2.Rel1 publicly available on: https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
We build TF-A in CI using x86_64 Linux hosted cross toolchains: --------------------------------------------------------------- * AArch32 bare-metal target (arm-none-eabi) * AArch64 bare-metal target (aarch64-none-elf)
Change-Id: I9b60728bcb1a48508ccd4fcbe0114b3029509a64 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| ab4d5dfe | 09-Apr-2024 |
Harrison Mutai <harrison.mutai@arm.com> |
docs: clarify build environment prerequisites
Our build system extensively uses syntax and tools that are not natively supported by Windows shells (i.e., CMD.exe and Powershell). This dependency nec
docs: clarify build environment prerequisites
Our build system extensively uses syntax and tools that are not natively supported by Windows shells (i.e., CMD.exe and Powershell). This dependency necessitates a UNIX-compatible build environment. This commit updates the prerequisites section in our documentation to reflect this.
Change-Id: Ia7e02d7a335e6c88bbaa0394650f1313cdfd6e40 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 04e9c66a | 08-Apr-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs: update release and code freeze dates" into integration |
| 19b73173 | 08-Apr-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs: remove entries of the deleted platforms" into integration |
| 7c9720f2 | 04-Apr-2024 |
Harrison Mutai <harrison.mutai@arm.com> |
docs: update release and code freeze dates
Change-Id: I850f26a66f017d5290ca4d3d670a7efed527f1ef Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> |
| 88f7c87b | 28-Mar-2024 |
Harry Moulton <harry.moulton@arm.com> |
docs(rmm): document console struct in rmm boot manifest
This change adds documentation for the console_list and console_info structures added to the RMM Boot Manifest v0.3.
Signed-off-by: Harry Mou
docs(rmm): document console struct in rmm boot manifest
This change adds documentation for the console_list and console_info structures added to the RMM Boot Manifest v0.3.
Signed-off-by: Harry Moulton <harry.moulton@arm.com> Change-Id: I3a4f9a4f1d34259bc69c0ab497cbfbc268d7a994
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| eee0ec48 | 26-Mar-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "mte_fixes" into integration
* changes: build(changelog): move mte to mte2 refactor(mte): remove mte, mte_perm |
| c282384d | 07-Mar-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(mte): remove mte, mte_perm
Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling of any feature bits in EL3. So remove both FEAT handling.
All mte regs that are currently cont
refactor(mte): remove mte, mte_perm
Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling of any feature bits in EL3. So remove both FEAT handling.
All mte regs that are currently context saved/restored are needed only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and remove FEAT_MTE usage.
BREAKING CHANGE: Any platform or downstream code trying to use SCR_EL3.ATA bit(26) will see failures as this is now moved to be used only with FEAT_MTE2 with commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2
Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 328d304d | 07-Mar-2024 |
Sona Mathew <sonarebecca.mathew@arm.com> |
chore: rename Poseidon to Neoverse V3
Rename Neoverse Poseidon to Neoverse V3, make changes to related build flags, macros, file names etc.
Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891 Sign
chore: rename Poseidon to Neoverse V3
Rename Neoverse Poseidon to Neoverse V3, make changes to related build flags, macros, file names etc.
Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| 3daf936b | 25-Mar-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(cpus): workaround for Cortex-A720 erratum 2926083" into integration |