Merge "docs(threat-model): add threat model for PSA FWU and TBBR FWU(recovery)" into integration

docs(threat-model): add threat model for PSA FWU and TBBR FWU(recovery)

Added a threat model for PSA firmware update as well as TBBR FWU aka
firmware recovery.

Change-Id: I2396e13144076d7294f61f681

docs(threat-model): add threat model for PSA FWU and TBBR FWU(recovery)

Added a threat model for PSA firmware update as well as TBBR FWU aka
firmware recovery.

Change-Id: I2396e13144076d7294f61f6817e1a8646225c6c2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(arm): update TBBR CoT dtsi file name in doc

Change-Id: I31ebee7574f5133aadbf2767377fd74a21775ce5
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

docs(fconf): update bindings for multi-RoT CoTs

Update CoT binding documentation to add the signing-key property
as optional in root-certificates and add rot_keys node

Change-Id: I1d1fbc0394275520c

docs(fconf): update bindings for multi-RoT CoTs

Update CoT binding documentation to add the signing-key property
as optional in root-certificates and add rot_keys node

Change-Id: I1d1fbc0394275520cfa43213d5b7006e51990fdd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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docs(security): security advisory for CVE-2023-49100

Reported-by: Christian Lindenmeier <christian.lindenmeier@fau.de>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I13fa93a65e501

docs(security): security advisory for CVE-2023-49100

Reported-by: Christian Lindenmeier <christian.lindenmeier@fau.de>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I13fa93a65e5017dae6c837e88cd80bda72d4c2a3

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fix(cpus): workaround for Cortex-A78C erratum 2683027

Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific

fix(cpus): workaround for Cortex-A78C erratum 2683027

Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific code sequence in EL3 during reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: I2bf9e675f48b62b4cd203100f7df40f4846aafa8
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2266875

Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]

fix(cpus): workaround for Cortex-X3 erratum 2266875

Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]=1 which will cause the CFP instruction to
invalidate all branch predictor resources regardless of context.

SDEN Documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I9c610777e222f57f520d223bb03fc5ad05af1077
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2302506

Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR

fix(cpus): workaround for Cortex-X3 erratum 2302506

Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave
like PLD/PRFM LD and not cause invalidation to other PE caches.

There might be a small performance degradation to this workaround
for certain workloads that share data.

SDEN can be found here:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I048b830867915b88afa36582c6da05734a56d22a
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(rockchip): fix documentation in how build bl31 in AARCH64

Rockchip Aarch64 SoCs expect TF-A's BL31

Change-Id: Ie74be32e2bd24c4de38990791b4a03d2b7695b4d
Signed-off-by: Michael Trimarchi <michael

fix(rockchip): fix documentation in how build bl31 in AARCH64

Rockchip Aarch64 SoCs expect TF-A's BL31

Change-Id: Ie74be32e2bd24c4de38990791b4a03d2b7695b4d
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

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docs(threat-model): provide PSR specification reference

Added an assumption in generic threat model that platform's hardware
conforms the Platform Security Requirements specification.

Change-Id: I7

docs(threat-model): provide PSR specification reference

Added an assumption in generic threat model that platform's hardware
conforms the Platform Security Requirements specification.

Change-Id: I753287feec1cd459edfd3d1c103e0e701827cc05
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ

feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.

By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.

e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd

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feat(context-mgmt): report context memory usage

This patch provides a reporting functionality to display the memory
consumed by the context in each security state and for each exception
level. Flag

feat(context-mgmt): report context memory usage

This patch provides a reporting functionality to display the memory
consumed by the context in each security state and for each exception
level. Flag PLATFORM_REPORT_CTX_MEM_USE enables or disables this
feature.

Change-Id: I1515366bf87561dcedf2b3206be167804df681d4
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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build(mpam): add new build option CTX_INCLUDE_MPAM_REGS

New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This opt

build(mpam): add new build option CTX_INCLUDE_MPAM_REGS

New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This option is currently disabled as MPAM is only
enabled for NS world.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie2e5e184cdb65f7e1a98d8fe81590253fd859679

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Merge "docs: update links to tf.org-wide process documents" into integration

Merge "fix(cpus): workaround for Cortex X3 erratum 2743088" into integration

docs: update links to tf.org-wide process documents

tf.org-wide documents have been migrated away from
developer.trustedfirmware.org, because the latter will be
decomissioned at some point in the fu

docs: update links to tf.org-wide process documents

tf.org-wide documents have been migrated away from
developer.trustedfirmware.org, because the latter will be
decomissioned at some point in the future. These documents are now
hosted in a new 'tf_docs' repository hosted on Github [1] and can be
easily browsed through a new ReadTheDocs website at [2].

Update all relevant links in TF-A documentation to refer to [2].

[1] https://github.com/TrustedFirmware/tf_docs
[2] https://trusted-firmware-docs.readthedocs.io/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib9d39c36250a05754fe5e46cb6f3044ecb776534

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fix(cpus): workaround for Cortex X3 erratum 2743088

Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instructio

fix(cpus): workaround for Cortex X3 erratum 2743088

Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instruction before the ISB of the powerdown code sequence specified in
the TRM.

SDEN documentation: https://developer.arm.com/documentation/2055130

Change-Id: I2c8577e3ca0781af8b1c3912e577d3bd77f92709
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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docs(versal): add ERRATA_ABI_SUPPORT build documentation

Add information about Versal platform for ERRATA_ABI_SUPPORT and
provide the build commands.

Signed-off-by: Prasad Kummari <prasad.kummari@a

docs(versal): add ERRATA_ABI_SUPPORT build documentation

Add information about Versal platform for ERRATA_ABI_SUPPORT and
provide the build commands.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I8466ea446814f888ae56f5cbb7bbdc06099d54f8

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fix(cpus): workaround for Cortex-A520 erratum 2858100

Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUAC

fix(cpus): workaround for Cortex-A520 erratum 2858100

Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677

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fix(cpus): workaround for Cortex-A520 erratum 2630792

Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1

fix(cpus): workaround for Cortex-A520 erratum 2630792

Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest

Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2778471

Cortex-X2 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUAC

fix(cpus): workaround for Cortex-X2 erratum 2778471

Cortex-X2 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: Ia95f0e276482283bf50e06c58c2bc5faab3f62c6
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 2778471

Cortex-A710 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set C

fix(cpus): workaround for Cortex-A710 erratum 2778471

Cortex-A710 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: Id3bb4a2673e41ff237682e46784d37752daf2f83
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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docs: fix errata in RMM-EL3 Communication Interface documentation

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I6d6b7ff084cc731470e873cfdf37beeec0d3635a

Merge "fix(cpus): workaround for Neoverse V2 erratum 2618597" into integration

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I23a81275d1e40cae39e6897093d6cdd3e11c08ea
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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