1/* 2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 30 /* dsb before isb of power down sequence */ 31 dsb sy 32workaround_runtime_end cortex_x4, ERRATUM(2740089) 33 34check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 35 36workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 37#if IMAGE_BL31 38 /* 39 * The Cortex X4 generic vectors are overridden to apply errata 40 * mitigation on exception entry from lower ELs. 41 */ 42 override_vector_table wa_cve_vbar_cortex_x4 43#endif /* IMAGE_BL31 */ 44workaround_reset_end cortex_x4, CVE(2022, 23960) 45 46check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 47 48cpu_reset_func_start cortex_x4 49 /* Disable speculative loads */ 50 msr SSBS, xzr 51cpu_reset_func_end cortex_x4 52 53 /* ---------------------------------------------------- 54 * HW will do the cache maintenance while powering down 55 * ---------------------------------------------------- 56 */ 57func cortex_x4_core_pwr_dwn 58 /* --------------------------------------------------- 59 * Enable CPU power down bit in power control register 60 * --------------------------------------------------- 61 */ 62 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 63 64 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 65 66 isb 67 ret 68endfunc cortex_x4_core_pwr_dwn 69 70errata_report_shim cortex_x4 71 72 /* --------------------------------------------- 73 * This function provides Cortex X4-specific 74 * register information for crash reporting. 75 * It needs to return with x6 pointing to 76 * a list of register names in ascii and 77 * x8 - x15 having values of registers to be 78 * reported. 79 * --------------------------------------------- 80 */ 81.section .rodata.cortex_x4_regs, "aS" 82cortex_x4_regs: /* The ascii list of register names to be reported */ 83 .asciz "cpuectlr_el1", "" 84 85func cortex_x4_cpu_reg_dump 86 adr x6, cortex_x4_regs 87 mrs x8, CORTEX_X4_CPUECTLR_EL1 88 ret 89endfunc cortex_x4_cpu_reg_dump 90 91declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 92 cortex_x4_reset_func, \ 93 cortex_x4_core_pwr_dwn 94