docs(rmm): document console struct in rmm boot manifest

This change adds documentation for the console_list and
console_info structures added to the RMM Boot Manifest v0.3.

Signed-off-by: Harry Mou

docs(rmm): document console struct in rmm boot manifest

This change adds documentation for the console_list and
console_info structures added to the RMM Boot Manifest v0.3.

Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Change-Id: I3a4f9a4f1d34259bc69c0ab497cbfbc268d7a994

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Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "fix(cpus): workaround for Cortex-A720 erratum 2926083" into integration

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPID

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "chore: update status of Cortex-X3 erratum 2615812" into integration

Merge "fix(cpus): workaround for Cortex-A720 erratum 2940794" into integration

Merge changes from topic "st_docs_update" into integration

* changes:
docs(st): set OP-TEE as default BL32
docs(st): one device flag for ST platforms

chore: update status of Cortex-X3 erratum 2615812

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Ied7150bab505a743401cf4afa9a0a5f81d5fdff1
Signed-off-by: Sona

chore: update status of Cortex-X3 erratum 2615812

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Ied7150bab505a743401cf4afa9a0a5f81d5fdff1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of

fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of the CPUACTLR2_EL1 to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I1488802e0ec7c16349c9633bb45de4d0e1faa9ad
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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docs(threat_model): cover the 'timing' side channel threat

Incorporate a timing side-channel attack into the TF-A generic
threat model. There is no software mitigation measures in TF-A
against this

docs(threat_model): cover the 'timing' side channel threat

Incorporate a timing side-channel attack into the TF-A generic
threat model. There is no software mitigation measures in TF-A
against this specific type of attack.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I10e53f8ed85a6da32de4fa6a210805f950018102

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docs(st): set OP-TEE as default BL32

Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more recei

docs(st): set OP-TEE as default BL32

Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more receive new features, but should still remain
as it is in the TF-A code.

[1]: https://wiki.st.com/stm32mpu/wiki/STM32_MPU_OpenSTLinux_release_note_-_v5.0.0#TF-A

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic49338dbba3fdcebcb1e477e6a1dbde32783482b

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docs(st): one device flag for ST platforms

Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build c

docs(st): one device flag for ST platforms

Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build command line for ST platforms.
This is in line with STMicroelectionics recommendation [1] about those
compilation flags.

[1]: https://wiki.st.com/stm32mpu/wiki/How_to_configure_TF-A_BL2#Build_command_details

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6f6ab17d45d00289989a606d15c143e5710c64ce

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Merge "refactor(mbedtls): remove mbedtls 2.x support" into integration

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910222c8abd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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docs(maintainers): add missing ST files

The files under tools/fiptool/plat_fiptool/st/ directory were not listed
as files maintained by STMicroelectronics.

Signed-off-by: Yann Gautier <yann.gautier

docs(maintainers): add missing ST files

The files under tools/fiptool/plat_fiptool/st/ directory were not listed
as files maintained by STMicroelectronics.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4120368253447d4dadc4ce4b6957ffbe6310da86

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docs(maintainers): add Maxime as co-maintainer for ST platforms

Add Maxime Méré as a co-maintainer for STMicroelectronics platforms.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I05

docs(maintainers): add Maxime as co-maintainer for ST platforms

Add Maxime Méré as a co-maintainer for STMicroelectronics platforms.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I05dda2049000d99f0e482492ec43d02ad1d5d0c8

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docs(maintainers): update ST platform ports title

STM32MP1 is no more the only product to be supported in TF-A with the
new STM32MP2. Change "STM32MP1 platform port" to "STMicroelectronics
platform

docs(maintainers): update ST platform ports title

STM32MP1 is no more the only product to be supported in TF-A with the
new STM32MP2. Change "STM32MP1 platform port" to "STMicroelectronics
platform ports" to better reflect this.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I30b1fd4310d38092e3e815cb635b474fc84bdc30

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docs(maintainers): sort github aliases

The aliases for github were added either by alphabetical order or at the
end of list. Sort them alphabetically with Linux sort tool, regardless
of uppercase/lo

docs(maintainers): sort github aliases

The aliases for github were added either by alphabetical order or at the
end of list. Sort them alphabetically with Linux sort tool, regardless
of uppercase/lowercase letters.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia247e102ab5fb0f7b8b6de76f23a869cc3f83d2c

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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docs: remove entries of the deleted platforms

Remove the details of the platforms from the 'deprecated
platforms' table those are already deleted.
This is in-sync with other depreaction tables [1] w

docs: remove entries of the deleted platforms

Remove the details of the platforms from the 'deprecated
platforms' table those are already deleted.
This is in-sync with other depreaction tables [1] which
only has deprecation entries and not deleted entries.

[1]: https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html#removal-of-deprecated-interfaces

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8c8e4ba4e7fa88ea83632202d17c7d35cdc200a

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feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI t

feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI that has been
validated to boot Linux and a private EDK2 build.

It's a drop-in replacement for the custom TF-A armstub now included in
the EEPROM images.

Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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docs: add documentation for `entry_point_info`

Change-Id: I20b5f2cf70bfff09126f3c0645f40d3e410a4c70
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>