docs(rd1ae): update documentation to include BL32

Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25

docs(rd1ae): update documentation to include BL32

Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25fdc114bb71d3ad7e1bb2d845f758d6af037e3d

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Merge "docs(maintainers): update qti maintainer" into integration

Merge "fix(docs): fix the indent and the build command for MT8188" into integration

Merge "docs(changelog): changelog for v2.12 release" into integration

Merge "docs: update build tool prerequisites" into integration

Merge "docs(tc): deprecate tc2 in documentation" into integration

docs(tc): deprecate tc2 in documentation

added a note to specify that tc2 has been deprecated

Change-Id: I7ab69a2560e0e56379f4e144d41da20671c1ca9d
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

docs(changelog): changelog for v2.12 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.12.0

Change-Id: Idb74f6a31bf2691e7666e2738030d

docs(changelog): changelog for v2.12 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.12.0

Change-Id: Idb74f6a31bf2691e7666e2738030d6f0e2b8c519
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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docs(fvp): update FVP model versions as per usage

Update the documentation to reflect the various FVP models
used in the OpenCI environment.

Change-Id: I6144ab7c41d3776421164125d07371dadc9252b5
Sig

docs(fvp): update FVP model versions as per usage

Update the documentation to reflect the various FVP models
used in the OpenCI environment.

Change-Id: I6144ab7c41d3776421164125d07371dadc9252b5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs: update build tool prerequisites

Bump `dtc`, `clang` and `sphinx` to reconcile our minimum requirements
with the versions used in CI.

Change-Id: Ia848b4bdd93dc833ea03eda5b002561468042f52
Signe

docs: update build tool prerequisites

Bump `dtc`, `clang` and `sphinx` to reconcile our minimum requirements
with the versions used in CI.

Change-Id: Ia848b4bdd93dc833ea03eda5b002561468042f52
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes Ic92c2abf,Id9182f65 into integration

* changes:
docs(juno): update PSCI instrumentation data
docs(n1sdp): update PSCI instrumentation data

Merge "docs(prerequisites): add Poetry installation instructions" into integration

docs(juno): update PSCI instrumentation data

Update for v2.12 release based on v2.12-rc0

Change-Id: Ic92c2abfc65dc1e9f979564eecd65cb2c285cb25
Signed-off-by: Zachary Leaf <zachary.leaf@arm.com>

docs(n1sdp): update PSCI instrumentation data

Update for v2.12 release based on v2.12-rc0

Change-Id: Id9182f65518c0b41d478d3f24edc3befbd9d2cf6
Signed-off-by: Zachary Leaf <zachary.leaf@arm.com>

docs(prerequisites): add Poetry installation instructions

This small change removes the footnote from Poetry that it is only used
for building documentation, as it is now used for some of the Python

docs(prerequisites): add Poetry installation instructions

This small change removes the footnote from Poetry that it is only used
for building documentation, as it is now used for some of the Python
tooling in the repository from the build system.

Additionally, add a link to the official installation guide for Poetry.

Change-Id: Ie36b7ecd8066cbf2a14a1085d84fa9bd9c4409ba
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(context-mgmt): add Root-Context documentation

* This patch adds some details on the EL3/Root-Context
and its related interfaces.

* Additionally it updates the existing details on the
inter

docs(context-mgmt): add Root-Context documentation

* This patch adds some details on the EL3/Root-Context
and its related interfaces.

* Additionally it updates the existing details on the
interfaces, related to various CPU context entries which
have been improvised recently.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I81a992fe09feca4dc3d579a48e54a4763425e052

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docs(juno): update Juno tested SCP version to 2.15

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I29452d0abadf9b5980ca9680ca2c78080c4c33a0

Merge "feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA" into integration

feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA

Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte*
store instruction. A related instruction is ST64BV0, which will replace
the lowest

feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA

Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte*
store instruction. A related instruction is ST64BV0, which will replace
the lowest 32 bits of the data with a value taken from the ACCDATA_EL1
system register (so that EL0 cannot alter them).
Using that ST64BV0 instruction and accessing the ACCDATA_EL1 system
register is guarded by two SCR_EL3 bits, which we should set to avoid a
trap into EL3, when lower ELs use one of those.

Add the required bits and pieces to make this feature usable:
- Add the ENABLE_FEAT_LS64_ACCDATA build option (defaulting to 0).
- Add the CPUID and SCR_EL3 bit definitions associated with FEAT_LS64.
- Add a feature check to check for the existing four variants of the
LS64 feature and detect future extensions.
- Add code to save and restore the ACCDATA_EL1 register on
secure/non-secure context switches.
- Enable the feature with runtime detection for FVP and Arm FPGA.

Please note that the *basic* FEAT_LS64 feature does not feature any trap
bits, it's only the addition of the ACCDATA_EL1 system register that
adds these traps and the SCR_EL3 bits.

Change-Id: Ie3e2ca2d9c4fbbd45c0cc6089accbb825579138a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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build: install dependencies before doc build

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I0448caa4e22c13d4dd821261642833d49ff7a234

fix(docs): fix the example command for doc build

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I8ee666ee4cd135d09380ce31751ddba9962ff831

docs: el3 token signing

Add documentation for the feature where EL3 can be used to sign realm
attestation token requests using RMM_EL3_TOKEN_SIGN command.
This patch also adds documentation for the

docs: el3 token signing

Add documentation for the feature where EL3 can be used to sign realm
attestation token requests using RMM_EL3_TOKEN_SIGN command.
This patch also adds documentation for the RMM_EL3_FEATURES features
command that can be used to discover support for features such as
RMM_EL3_TOKEN_SIGN.

Change-Id: Iab5a157761ed17931210c3702f813198fc9c4b3a
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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feat(docs): add DPE to RSE desing doc

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iec38be8a3eb93a54d9b5bc7db7a7ff8c126920ac

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I23

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I234a2400d00fea606c5312ebddf94e2624463ff8

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feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the poss

feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the possible attacks.
- Rephrase the section that describes the Measured Boot backends.

Change-Id: I6577a56184992bf16f4aa1b773d1636781cbb049
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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