1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sysreg128.h> 37 #include <lib/extensions/sys_reg_trace.h> 38 #include <lib/extensions/tcr2.h> 39 #include <lib/extensions/trbe.h> 40 #include <lib/extensions/trf.h> 41 #include <lib/utils.h> 42 43 #if ENABLE_FEAT_TWED 44 /* Make sure delay value fits within the range(0-15) */ 45 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 46 #endif /* ENABLE_FEAT_TWED */ 47 48 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 49 static bool has_secure_perworld_init; 50 51 static void manage_extensions_common(cpu_context_t *ctx); 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 } 195 #endif /* ENABLE_RME */ 196 197 /****************************************************************************** 198 * This function performs initializations that are specific to NON-SECURE state 199 * and updates the cpu context specified by 'ctx'. 200 *****************************************************************************/ 201 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 202 { 203 u_register_t scr_el3; 204 el3_state_t *state; 205 206 state = get_el3state_ctx(ctx); 207 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 208 209 /* SCR_NS: Set the NS bit */ 210 scr_el3 |= SCR_NS_BIT; 211 212 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 213 if (is_feat_mte2_supported()) { 214 scr_el3 |= SCR_ATA_BIT; 215 } 216 217 #if !CTX_INCLUDE_PAUTH_REGS 218 /* 219 * Pointer Authentication feature, if present, is always enabled by default 220 * for Non secure lower exception levels. We do not have an explicit 221 * flag to set it. 222 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 223 * exception levels of secure and realm worlds. 224 * 225 * To prevent the leakage between the worlds during world switch, 226 * we enable it only for the non-secure world. 227 * 228 * If the Secure/realm world wants to use pointer authentication, 229 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 230 * it will be enabled globally for all the contexts. 231 * 232 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 233 * other than EL3 234 * 235 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 236 * than EL3 237 */ 238 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 239 240 #endif /* CTX_INCLUDE_PAUTH_REGS */ 241 242 #if HANDLE_EA_EL3_FIRST_NS 243 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 244 scr_el3 |= SCR_EA_BIT; 245 #endif 246 247 #if RAS_TRAP_NS_ERR_REC_ACCESS 248 /* 249 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 250 * and RAS ERX registers from EL1 and EL2(from any security state) 251 * are trapped to EL3. 252 * Set here to trap only for NS EL1/EL2 253 * 254 */ 255 scr_el3 |= SCR_TERR_BIT; 256 #endif 257 258 /* CSV2 version 2 and above */ 259 if (is_feat_csv2_2_supported()) { 260 /* Enable access to the SCXTNUM_ELx registers. */ 261 scr_el3 |= SCR_EnSCXT_BIT; 262 } 263 264 #ifdef IMAGE_BL31 265 /* 266 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 267 * indicated by the interrupt routing model for BL31. 268 */ 269 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 270 #endif 271 272 if (is_feat_the_supported()) { 273 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 274 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 275 */ 276 scr_el3 |= SCR_RCWMASKEn_BIT; 277 } 278 279 if (is_feat_sctlr2_supported()) { 280 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 281 * SCTLR2_ELx registers. 282 */ 283 scr_el3 |= SCR_SCTLR2En_BIT; 284 } 285 286 if (is_feat_d128_supported()) { 287 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 288 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 289 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 290 */ 291 scr_el3 |= SCR_D128En_BIT; 292 } 293 294 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 295 296 /* Initialize EL2 context registers */ 297 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 298 299 /* 300 * Initialize SCTLR_EL2 context register with reset value. 301 */ 302 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 303 304 if (is_feat_hcx_supported()) { 305 /* 306 * Initialize register HCRX_EL2 with its init value. 307 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 308 * chance that this can lead to unexpected behavior in lower 309 * ELs that have not been updated since the introduction of 310 * this feature if not properly initialized, especially when 311 * it comes to those bits that enable/disable traps. 312 */ 313 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 314 HCRX_EL2_INIT_VAL); 315 } 316 317 if (is_feat_fgt_supported()) { 318 /* 319 * Initialize HFG*_EL2 registers with a default value so legacy 320 * systems unaware of FEAT_FGT do not get trapped due to their lack 321 * of initialization for this feature. 322 */ 323 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 324 HFGITR_EL2_INIT_VAL); 325 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 326 HFGRTR_EL2_INIT_VAL); 327 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 328 HFGWTR_EL2_INIT_VAL); 329 } 330 #else 331 /* Initialize EL1 context registers */ 332 setup_el1_context(ctx, ep); 333 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 334 335 manage_extensions_nonsecure(ctx); 336 } 337 338 /******************************************************************************* 339 * The following function performs initialization of the cpu_context 'ctx' 340 * for first use that is common to all security states, and sets the 341 * initial entrypoint state as specified by the entry_point_info structure. 342 * 343 * The EE and ST attributes are used to configure the endianness and secure 344 * timer availability for the new execution context. 345 ******************************************************************************/ 346 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 347 { 348 u_register_t scr_el3; 349 u_register_t mdcr_el3; 350 el3_state_t *state; 351 gp_regs_t *gp_regs; 352 353 state = get_el3state_ctx(ctx); 354 355 /* Clear any residual register values from the context */ 356 zeromem(ctx, sizeof(*ctx)); 357 358 /* 359 * The lower-EL context is zeroed so that no stale values leak to a world. 360 * It is assumed that an all-zero lower-EL context is good enough for it 361 * to boot correctly. However, there are very few registers where this 362 * is not true and some values need to be recreated. 363 */ 364 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 365 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 366 367 /* 368 * These bits are set in the gicv3 driver. Losing them (especially the 369 * SRE bit) is problematic for all worlds. Henceforth recreate them. 370 */ 371 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 372 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 373 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 374 375 /* 376 * The actlr_el2 register can be initialized in platform's reset handler 377 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 378 */ 379 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 380 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 381 382 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 383 scr_el3 = SCR_RESET_VAL; 384 385 /* 386 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 387 * EL2, EL1 and EL0 are not trapped to EL3. 388 * 389 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 390 * EL2, EL1 and EL0 are not trapped to EL3. 391 * 392 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 393 * both Security states and both Execution states. 394 * 395 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 396 * Non-secure memory. 397 */ 398 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 399 400 scr_el3 |= SCR_SIF_BIT; 401 402 /* 403 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 404 * Exception level as specified by SPSR. 405 */ 406 if (GET_RW(ep->spsr) == MODE_RW_64) { 407 scr_el3 |= SCR_RW_BIT; 408 } 409 410 /* 411 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 412 * Secure timer registers to EL3, from AArch64 state only, if specified 413 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 414 * bit always behaves as 1 (i.e. secure physical timer register access 415 * is not trapped) 416 */ 417 if (EP_GET_ST(ep->h.attr) != 0U) { 418 scr_el3 |= SCR_ST_BIT; 419 } 420 421 /* 422 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 423 * SCR_EL3.HXEn. 424 */ 425 if (is_feat_hcx_supported()) { 426 scr_el3 |= SCR_HXEn_BIT; 427 } 428 429 /* 430 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 431 * registers are trapped to EL3. 432 */ 433 #if ENABLE_FEAT_RNG_TRAP 434 scr_el3 |= SCR_TRNDR_BIT; 435 #endif 436 437 #if FAULT_INJECTION_SUPPORT 438 /* Enable fault injection from lower ELs */ 439 scr_el3 |= SCR_FIEN_BIT; 440 #endif 441 442 #if CTX_INCLUDE_PAUTH_REGS 443 /* 444 * Enable Pointer Authentication globally for all the worlds. 445 * 446 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 447 * other than EL3 448 * 449 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 450 * than EL3 451 */ 452 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 453 #endif /* CTX_INCLUDE_PAUTH_REGS */ 454 455 /* 456 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 457 */ 458 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 459 scr_el3 |= SCR_TCR2EN_BIT; 460 } 461 462 /* 463 * SCR_EL3.PIEN: Enable permission indirection and overlay 464 * registers for AArch64 if present. 465 */ 466 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 467 scr_el3 |= SCR_PIEN_BIT; 468 } 469 470 /* 471 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 472 */ 473 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 474 scr_el3 |= SCR_GCSEn_BIT; 475 } 476 477 /* 478 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 479 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 480 * next mode is Hyp. 481 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 482 * same conditions as HVC instructions and when the processor supports 483 * ARMv8.6-FGT. 484 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 485 * CNTPOFF_EL2 register under the same conditions as HVC instructions 486 * and when the processor supports ECV. 487 */ 488 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 489 || ((GET_RW(ep->spsr) != MODE_RW_64) 490 && (GET_M32(ep->spsr) == MODE32_hyp))) { 491 scr_el3 |= SCR_HCE_BIT; 492 493 if (is_feat_fgt_supported()) { 494 scr_el3 |= SCR_FGTEN_BIT; 495 } 496 497 if (is_feat_ecv_supported()) { 498 scr_el3 |= SCR_ECVEN_BIT; 499 } 500 } 501 502 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 503 if (is_feat_twed_supported()) { 504 /* Set delay in SCR_EL3 */ 505 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 506 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 507 << SCR_TWEDEL_SHIFT); 508 509 /* Enable WFE delay */ 510 scr_el3 |= SCR_TWEDEn_BIT; 511 } 512 513 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 514 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 515 if (is_feat_sel2_supported()) { 516 scr_el3 |= SCR_EEL2_BIT; 517 } 518 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 519 520 /* 521 * Populate EL3 state so that we've the right context 522 * before doing ERET 523 */ 524 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 525 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 526 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 527 528 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 529 mdcr_el3 = MDCR_EL3_RESET_VAL; 530 531 /* --------------------------------------------------------------------- 532 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 533 * Some fields are architecturally UNKNOWN on reset. 534 * 535 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 536 * Debug exceptions, other than Breakpoint Instruction exceptions, are 537 * disabled from all ELs in Secure state. 538 * 539 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 540 * privileged debug from S-EL1. 541 * 542 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 543 * access to the powerdown debug registers do not trap to EL3. 544 * 545 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 546 * debug registers, other than those registers that are controlled by 547 * MDCR_EL3.TDOSA. 548 */ 549 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 550 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 551 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 552 553 /* 554 * Configure MDCR_EL3 register as applicable for each world 555 * (NS/Secure/Realm) context. 556 */ 557 manage_extensions_common(ctx); 558 559 /* 560 * Store the X0-X7 value from the entrypoint into the context 561 * Use memcpy as we are in control of the layout of the structures 562 */ 563 gp_regs = get_gpregs_ctx(ctx); 564 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 565 } 566 567 /******************************************************************************* 568 * Context management library initialization routine. This library is used by 569 * runtime services to share pointers to 'cpu_context' structures for secure 570 * non-secure and realm states. Management of the structures and their associated 571 * memory is not done by the context management library e.g. the PSCI service 572 * manages the cpu context used for entry from and exit to the non-secure state. 573 * The Secure payload dispatcher service manages the context(s) corresponding to 574 * the secure state. It also uses this library to get access to the non-secure 575 * state cpu context pointers. 576 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 577 * which will be used for programming an entry into a lower EL. The same context 578 * will be used to save state upon exception entry from that EL. 579 ******************************************************************************/ 580 void __init cm_init(void) 581 { 582 /* 583 * The context management library has only global data to initialize, but 584 * that will be done when the BSS is zeroed out. 585 */ 586 } 587 588 /******************************************************************************* 589 * This is the high-level function used to initialize the cpu_context 'ctx' for 590 * first use. It performs initializations that are common to all security states 591 * and initializations specific to the security state specified in 'ep' 592 ******************************************************************************/ 593 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 594 { 595 unsigned int security_state; 596 597 assert(ctx != NULL); 598 599 /* 600 * Perform initializations that are common 601 * to all security states 602 */ 603 setup_context_common(ctx, ep); 604 605 security_state = GET_SECURITY_STATE(ep->h.attr); 606 607 /* Perform security state specific initializations */ 608 switch (security_state) { 609 case SECURE: 610 setup_secure_context(ctx, ep); 611 break; 612 #if ENABLE_RME 613 case REALM: 614 setup_realm_context(ctx, ep); 615 break; 616 #endif 617 case NON_SECURE: 618 setup_ns_context(ctx, ep); 619 break; 620 default: 621 ERROR("Invalid security state\n"); 622 panic(); 623 break; 624 } 625 } 626 627 /******************************************************************************* 628 * Enable architecture extensions for EL3 execution. This function only updates 629 * registers in-place which are expected to either never change or be 630 * overwritten by el3_exit. 631 ******************************************************************************/ 632 #if IMAGE_BL31 633 void cm_manage_extensions_el3(void) 634 { 635 if (is_feat_amu_supported()) { 636 amu_init_el3(); 637 } 638 639 if (is_feat_sme_supported()) { 640 sme_init_el3(); 641 } 642 643 pmuv3_init_el3(); 644 } 645 #endif /* IMAGE_BL31 */ 646 647 /****************************************************************************** 648 * Function to initialise the registers with the RESET values in the context 649 * memory, which are maintained per world. 650 ******************************************************************************/ 651 #if IMAGE_BL31 652 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 653 { 654 /* 655 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 656 * 657 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 658 * by Advanced SIMD, floating-point or SVE instructions (if 659 * implemented) do not trap to EL3. 660 * 661 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 662 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 663 */ 664 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 665 666 per_world_ctx->ctx_cptr_el3 = cptr_el3; 667 668 /* 669 * Initialize MPAM3_EL3 to its default reset value 670 * 671 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 672 * all lower ELn MPAM3_EL3 register access to, trap to EL3 673 */ 674 675 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 676 } 677 #endif /* IMAGE_BL31 */ 678 679 /******************************************************************************* 680 * Initialise per_world_context for Non-Secure world. 681 * This function enables the architecture extensions, which have same value 682 * across the cores for the non-secure world. 683 ******************************************************************************/ 684 #if IMAGE_BL31 685 void manage_extensions_nonsecure_per_world(void) 686 { 687 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 688 689 if (is_feat_sme_supported()) { 690 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 691 } 692 693 if (is_feat_sve_supported()) { 694 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 695 } 696 697 if (is_feat_amu_supported()) { 698 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 699 } 700 701 if (is_feat_sys_reg_trace_supported()) { 702 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 703 } 704 705 if (is_feat_mpam_supported()) { 706 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 707 } 708 } 709 #endif /* IMAGE_BL31 */ 710 711 /******************************************************************************* 712 * Initialise per_world_context for Secure world. 713 * This function enables the architecture extensions, which have same value 714 * across the cores for the secure world. 715 ******************************************************************************/ 716 static void manage_extensions_secure_per_world(void) 717 { 718 #if IMAGE_BL31 719 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 720 721 if (is_feat_sme_supported()) { 722 723 if (ENABLE_SME_FOR_SWD) { 724 /* 725 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 726 * SME, SVE, and FPU/SIMD context properly managed. 727 */ 728 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 729 } else { 730 /* 731 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 732 * world can safely use the associated registers. 733 */ 734 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 735 } 736 } 737 if (is_feat_sve_supported()) { 738 if (ENABLE_SVE_FOR_SWD) { 739 /* 740 * Enable SVE and FPU in secure context, SPM must ensure 741 * that the SVE and FPU register contexts are properly managed. 742 */ 743 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 744 } else { 745 /* 746 * Disable SVE and FPU in secure context so non-secure world 747 * can safely use them. 748 */ 749 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 750 } 751 } 752 753 /* NS can access this but Secure shouldn't */ 754 if (is_feat_sys_reg_trace_supported()) { 755 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 756 } 757 758 has_secure_perworld_init = true; 759 #endif /* IMAGE_BL31 */ 760 } 761 762 /******************************************************************************* 763 * Enable architecture extensions on first entry to Non-secure world only 764 * and disable for secure world. 765 * 766 * NOTE: Arch features which have been provided with the capability of getting 767 * enabled only for non-secure world and being disabled for secure world are 768 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 769 ******************************************************************************/ 770 static void manage_extensions_common(cpu_context_t *ctx) 771 { 772 #if IMAGE_BL31 773 if (is_feat_spe_supported()) { 774 /* 775 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 776 */ 777 spe_enable(ctx); 778 } 779 780 if (is_feat_trbe_supported()) { 781 /* 782 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 783 * Realm state. 784 */ 785 trbe_enable(ctx); 786 } 787 788 if (is_feat_trf_supported()) { 789 /* 790 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 791 */ 792 trf_enable(ctx); 793 } 794 #endif /* IMAGE_BL31 */ 795 } 796 797 /******************************************************************************* 798 * Enable architecture extensions on first entry to Non-secure world. 799 ******************************************************************************/ 800 static void manage_extensions_nonsecure(cpu_context_t *ctx) 801 { 802 #if IMAGE_BL31 803 if (is_feat_amu_supported()) { 804 amu_enable(ctx); 805 } 806 807 if (is_feat_sme_supported()) { 808 sme_enable(ctx); 809 } 810 811 if (is_feat_fgt2_supported()) { 812 fgt2_enable(ctx); 813 } 814 815 if (is_feat_debugv8p9_supported()) { 816 debugv8p9_extended_bp_wp_enable(ctx); 817 } 818 819 if (is_feat_brbe_supported()) { 820 brbe_enable(ctx); 821 } 822 823 pmuv3_enable(ctx); 824 #endif /* IMAGE_BL31 */ 825 } 826 827 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 828 static __unused void enable_pauth_el2(void) 829 { 830 u_register_t hcr_el2 = read_hcr_el2(); 831 /* 832 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 833 * accessing key registers or using pointer authentication instructions 834 * from lower ELs. 835 */ 836 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 837 838 write_hcr_el2(hcr_el2); 839 } 840 841 #if INIT_UNUSED_NS_EL2 842 /******************************************************************************* 843 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 844 * world when EL2 is empty and unused. 845 ******************************************************************************/ 846 static void manage_extensions_nonsecure_el2_unused(void) 847 { 848 #if IMAGE_BL31 849 if (is_feat_spe_supported()) { 850 spe_init_el2_unused(); 851 } 852 853 if (is_feat_amu_supported()) { 854 amu_init_el2_unused(); 855 } 856 857 if (is_feat_mpam_supported()) { 858 mpam_init_el2_unused(); 859 } 860 861 if (is_feat_trbe_supported()) { 862 trbe_init_el2_unused(); 863 } 864 865 if (is_feat_sys_reg_trace_supported()) { 866 sys_reg_trace_init_el2_unused(); 867 } 868 869 if (is_feat_trf_supported()) { 870 trf_init_el2_unused(); 871 } 872 873 pmuv3_init_el2_unused(); 874 875 if (is_feat_sve_supported()) { 876 sve_init_el2_unused(); 877 } 878 879 if (is_feat_sme_supported()) { 880 sme_init_el2_unused(); 881 } 882 883 #if ENABLE_PAUTH 884 enable_pauth_el2(); 885 #endif /* ENABLE_PAUTH */ 886 #endif /* IMAGE_BL31 */ 887 } 888 #endif /* INIT_UNUSED_NS_EL2 */ 889 890 /******************************************************************************* 891 * Enable architecture extensions on first entry to Secure world. 892 ******************************************************************************/ 893 static void manage_extensions_secure(cpu_context_t *ctx) 894 { 895 #if IMAGE_BL31 896 if (is_feat_sme_supported()) { 897 if (ENABLE_SME_FOR_SWD) { 898 /* 899 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 900 * must ensure SME, SVE, and FPU/SIMD context properly managed. 901 */ 902 sme_init_el3(); 903 sme_enable(ctx); 904 } else { 905 /* 906 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 907 * world can safely use the associated registers. 908 */ 909 sme_disable(ctx); 910 } 911 } 912 #endif /* IMAGE_BL31 */ 913 } 914 915 #if !IMAGE_BL1 916 /******************************************************************************* 917 * The following function initializes the cpu_context for a CPU specified by 918 * its `cpu_idx` for first use, and sets the initial entrypoint state as 919 * specified by the entry_point_info structure. 920 ******************************************************************************/ 921 void cm_init_context_by_index(unsigned int cpu_idx, 922 const entry_point_info_t *ep) 923 { 924 cpu_context_t *ctx; 925 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 926 cm_setup_context(ctx, ep); 927 } 928 #endif /* !IMAGE_BL1 */ 929 930 /******************************************************************************* 931 * The following function initializes the cpu_context for the current CPU 932 * for first use, and sets the initial entrypoint state as specified by the 933 * entry_point_info structure. 934 ******************************************************************************/ 935 void cm_init_my_context(const entry_point_info_t *ep) 936 { 937 cpu_context_t *ctx; 938 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 939 cm_setup_context(ctx, ep); 940 } 941 942 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 943 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 944 { 945 #if INIT_UNUSED_NS_EL2 946 u_register_t hcr_el2 = HCR_RESET_VAL; 947 u_register_t mdcr_el2; 948 u_register_t scr_el3; 949 950 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 951 952 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 953 if ((scr_el3 & SCR_RW_BIT) != 0U) { 954 hcr_el2 |= HCR_RW_BIT; 955 } 956 957 write_hcr_el2(hcr_el2); 958 959 /* 960 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 961 * All fields have architecturally UNKNOWN reset values. 962 */ 963 write_cptr_el2(CPTR_EL2_RESET_VAL); 964 965 /* 966 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 967 * reset and are set to zero except for field(s) listed below. 968 * 969 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 970 * Non-secure EL0 and EL1 accesses to the physical timer registers. 971 * 972 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 973 * Non-secure EL0 and EL1 accesses to the physical counter registers. 974 */ 975 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 976 977 /* 978 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 979 * UNKNOWN value. 980 */ 981 write_cntvoff_el2(0); 982 983 /* 984 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 985 * respectively. 986 */ 987 write_vpidr_el2(read_midr_el1()); 988 write_vmpidr_el2(read_mpidr_el1()); 989 990 /* 991 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 992 * 993 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 994 * translation is disabled, cache maintenance operations depend on the 995 * VMID. 996 * 997 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 998 * disabled. 999 */ 1000 write_vttbr_el2(VTTBR_RESET_VAL & 1001 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1002 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1003 1004 /* 1005 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1006 * Some fields are architecturally UNKNOWN on reset. 1007 * 1008 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1009 * register accesses to the Debug ROM registers are not trapped to EL2. 1010 * 1011 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1012 * accesses to the powerdown debug registers are not trapped to EL2. 1013 * 1014 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1015 * debug registers do not trap to EL2. 1016 * 1017 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1018 * EL2. 1019 */ 1020 mdcr_el2 = MDCR_EL2_RESET_VAL & 1021 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1022 MDCR_EL2_TDE_BIT); 1023 1024 write_mdcr_el2(mdcr_el2); 1025 1026 /* 1027 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1028 * 1029 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1030 * EL1 accesses to System registers do not trap to EL2. 1031 */ 1032 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1033 1034 /* 1035 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1036 * reset. 1037 * 1038 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1039 * and prevent timer interrupts. 1040 */ 1041 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1042 1043 manage_extensions_nonsecure_el2_unused(); 1044 #endif /* INIT_UNUSED_NS_EL2 */ 1045 } 1046 1047 /******************************************************************************* 1048 * Prepare the CPU system registers for first entry into realm, secure, or 1049 * normal world. 1050 * 1051 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1052 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1053 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1054 * For all entries, the EL1 registers are initialized from the cpu_context 1055 ******************************************************************************/ 1056 void cm_prepare_el3_exit(uint32_t security_state) 1057 { 1058 u_register_t sctlr_el2, scr_el3; 1059 cpu_context_t *ctx = cm_get_context(security_state); 1060 1061 assert(ctx != NULL); 1062 1063 if (security_state == NON_SECURE) { 1064 uint64_t el2_implemented = el_implemented(2); 1065 1066 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1067 CTX_SCR_EL3); 1068 1069 if (el2_implemented != EL_IMPL_NONE) { 1070 1071 /* 1072 * If context is not being used for EL2, initialize 1073 * HCRX_EL2 with its init value here. 1074 */ 1075 if (is_feat_hcx_supported()) { 1076 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1077 } 1078 1079 /* 1080 * Initialize Fine-grained trap registers introduced 1081 * by FEAT_FGT so all traps are initially disabled when 1082 * switching to EL2 or a lower EL, preventing undesired 1083 * behavior. 1084 */ 1085 if (is_feat_fgt_supported()) { 1086 /* 1087 * Initialize HFG*_EL2 registers with a default 1088 * value so legacy systems unaware of FEAT_FGT 1089 * do not get trapped due to their lack of 1090 * initialization for this feature. 1091 */ 1092 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1093 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1094 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1095 } 1096 1097 /* Condition to ensure EL2 is being used. */ 1098 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1099 /* Initialize SCTLR_EL2 register with reset value. */ 1100 sctlr_el2 = SCTLR_EL2_RES1; 1101 1102 /* 1103 * If workaround of errata 764081 for Cortex-A75 1104 * is used then set SCTLR_EL2.IESB to enable 1105 * Implicit Error Synchronization Barrier. 1106 */ 1107 if (errata_a75_764081_applies()) { 1108 sctlr_el2 |= SCTLR_IESB_BIT; 1109 } 1110 1111 write_sctlr_el2(sctlr_el2); 1112 } else { 1113 /* 1114 * (scr_el3 & SCR_HCE_BIT==0) 1115 * EL2 implemented but unused. 1116 */ 1117 init_nonsecure_el2_unused(ctx); 1118 } 1119 } 1120 } 1121 #if (!CTX_INCLUDE_EL2_REGS) 1122 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1123 cm_el1_sysregs_context_restore(security_state); 1124 #endif 1125 cm_set_next_eret_context(security_state); 1126 } 1127 1128 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1129 1130 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1131 { 1132 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1133 if (is_feat_amu_supported()) { 1134 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1135 } 1136 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1137 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1138 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1139 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1140 } 1141 1142 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1143 { 1144 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1145 if (is_feat_amu_supported()) { 1146 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1147 } 1148 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1149 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1150 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1151 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1152 } 1153 1154 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1155 { 1156 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1157 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1158 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1159 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1160 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1161 } 1162 1163 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1164 { 1165 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1166 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1167 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1168 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1169 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1170 } 1171 1172 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1173 { 1174 u_register_t mpam_idr = read_mpamidr_el1(); 1175 1176 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1177 1178 /* 1179 * The context registers that we intend to save would be part of the 1180 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1181 */ 1182 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1183 return; 1184 } 1185 1186 /* 1187 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1188 * MPAMIDR_HAS_HCR_BIT == 1. 1189 */ 1190 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1191 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1192 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1193 1194 /* 1195 * The number of MPAMVPM registers is implementation defined, their 1196 * number is stored in the MPAMIDR_EL1 register. 1197 */ 1198 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1199 case 7: 1200 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1201 __fallthrough; 1202 case 6: 1203 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1204 __fallthrough; 1205 case 5: 1206 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1207 __fallthrough; 1208 case 4: 1209 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1210 __fallthrough; 1211 case 3: 1212 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1213 __fallthrough; 1214 case 2: 1215 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1216 __fallthrough; 1217 case 1: 1218 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1219 break; 1220 } 1221 } 1222 1223 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1224 { 1225 u_register_t mpam_idr = read_mpamidr_el1(); 1226 1227 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1228 1229 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1230 return; 1231 } 1232 1233 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1234 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1235 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1236 1237 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1238 case 7: 1239 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1240 __fallthrough; 1241 case 6: 1242 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1243 __fallthrough; 1244 case 5: 1245 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1246 __fallthrough; 1247 case 4: 1248 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1249 __fallthrough; 1250 case 3: 1251 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1252 __fallthrough; 1253 case 2: 1254 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1255 __fallthrough; 1256 case 1: 1257 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1258 break; 1259 } 1260 } 1261 1262 /* --------------------------------------------------------------------------- 1263 * The following registers are not added: 1264 * ICH_AP0R<n>_EL2 1265 * ICH_AP1R<n>_EL2 1266 * ICH_LR<n>_EL2 1267 * 1268 * NOTE: For a system with S-EL2 present but not enabled, accessing 1269 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1270 * SCR_EL3.NS = 1 before accessing this register. 1271 * --------------------------------------------------------------------------- 1272 */ 1273 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1274 { 1275 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1276 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1277 #else 1278 u_register_t scr_el3 = read_scr_el3(); 1279 write_scr_el3(scr_el3 | SCR_NS_BIT); 1280 isb(); 1281 1282 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1283 1284 write_scr_el3(scr_el3); 1285 isb(); 1286 #endif 1287 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1288 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1289 } 1290 1291 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1292 { 1293 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1294 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1295 #else 1296 u_register_t scr_el3 = read_scr_el3(); 1297 write_scr_el3(scr_el3 | SCR_NS_BIT); 1298 isb(); 1299 1300 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1301 1302 write_scr_el3(scr_el3); 1303 isb(); 1304 #endif 1305 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1306 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1307 } 1308 1309 /* ----------------------------------------------------- 1310 * The following registers are not added: 1311 * AMEVCNTVOFF0<n>_EL2 1312 * AMEVCNTVOFF1<n>_EL2 1313 * ----------------------------------------------------- 1314 */ 1315 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1316 { 1317 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1318 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1319 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1320 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1321 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1322 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1323 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1324 if (CTX_INCLUDE_AARCH32_REGS) { 1325 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1326 } 1327 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1328 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1329 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1330 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1331 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1332 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1333 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1334 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1335 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1336 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1337 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1338 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1339 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1340 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1341 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1342 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1343 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1344 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1345 1346 write_el2_ctx_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1347 write_el2_ctx_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1348 } 1349 1350 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1351 { 1352 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1353 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1354 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1355 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1356 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1357 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1358 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1359 if (CTX_INCLUDE_AARCH32_REGS) { 1360 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1361 } 1362 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1363 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1364 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1365 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1366 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1367 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1368 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1369 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1370 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1371 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1372 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1373 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1374 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1375 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1376 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1377 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1378 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1379 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1380 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1381 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1382 } 1383 1384 /******************************************************************************* 1385 * Save EL2 sysreg context 1386 ******************************************************************************/ 1387 void cm_el2_sysregs_context_save(uint32_t security_state) 1388 { 1389 cpu_context_t *ctx; 1390 el2_sysregs_t *el2_sysregs_ctx; 1391 1392 ctx = cm_get_context(security_state); 1393 assert(ctx != NULL); 1394 1395 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1396 1397 el2_sysregs_context_save_common(el2_sysregs_ctx); 1398 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1399 1400 if (is_feat_mte2_supported()) { 1401 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1402 } 1403 1404 if (is_feat_mpam_supported()) { 1405 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1406 } 1407 1408 if (is_feat_fgt_supported()) { 1409 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1410 } 1411 1412 if (is_feat_fgt2_supported()) { 1413 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1414 } 1415 1416 if (is_feat_ecv_v2_supported()) { 1417 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1418 } 1419 1420 if (is_feat_vhe_supported()) { 1421 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1422 read_contextidr_el2()); 1423 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1424 } 1425 1426 if (is_feat_ras_supported()) { 1427 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1428 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1429 } 1430 1431 if (is_feat_nv2_supported()) { 1432 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1433 } 1434 1435 if (is_feat_trf_supported()) { 1436 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1437 } 1438 1439 if (is_feat_csv2_2_supported()) { 1440 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1441 read_scxtnum_el2()); 1442 } 1443 1444 if (is_feat_hcx_supported()) { 1445 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1446 } 1447 1448 if (is_feat_tcr2_supported()) { 1449 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1450 } 1451 1452 if (is_feat_sxpie_supported()) { 1453 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1454 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1455 } 1456 1457 if (is_feat_sxpoe_supported()) { 1458 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1459 } 1460 1461 if (is_feat_s2pie_supported()) { 1462 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1463 } 1464 1465 if (is_feat_gcs_supported()) { 1466 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1467 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1468 } 1469 1470 if (is_feat_sctlr2_supported()) { 1471 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1472 } 1473 } 1474 1475 /******************************************************************************* 1476 * Restore EL2 sysreg context 1477 ******************************************************************************/ 1478 void cm_el2_sysregs_context_restore(uint32_t security_state) 1479 { 1480 cpu_context_t *ctx; 1481 el2_sysregs_t *el2_sysregs_ctx; 1482 1483 ctx = cm_get_context(security_state); 1484 assert(ctx != NULL); 1485 1486 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1487 1488 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1489 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1490 1491 if (is_feat_mte2_supported()) { 1492 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1493 } 1494 1495 if (is_feat_mpam_supported()) { 1496 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1497 } 1498 1499 if (is_feat_fgt_supported()) { 1500 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1501 } 1502 1503 if (is_feat_fgt2_supported()) { 1504 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1505 } 1506 1507 if (is_feat_ecv_v2_supported()) { 1508 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1509 } 1510 1511 if (is_feat_vhe_supported()) { 1512 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1513 contextidr_el2)); 1514 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1515 } 1516 1517 if (is_feat_ras_supported()) { 1518 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1519 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1520 } 1521 1522 if (is_feat_nv2_supported()) { 1523 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1524 } 1525 1526 if (is_feat_trf_supported()) { 1527 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1528 } 1529 1530 if (is_feat_csv2_2_supported()) { 1531 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1532 scxtnum_el2)); 1533 } 1534 1535 if (is_feat_hcx_supported()) { 1536 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1537 } 1538 1539 if (is_feat_tcr2_supported()) { 1540 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1541 } 1542 1543 if (is_feat_sxpie_supported()) { 1544 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1545 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1546 } 1547 1548 if (is_feat_sxpoe_supported()) { 1549 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1550 } 1551 1552 if (is_feat_s2pie_supported()) { 1553 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1554 } 1555 1556 if (is_feat_gcs_supported()) { 1557 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1558 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1559 } 1560 1561 if (is_feat_sctlr2_supported()) { 1562 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1563 } 1564 } 1565 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1566 1567 #if IMAGE_BL31 1568 /********************************************************************************* 1569 * This function allows Architecture features asymmetry among cores. 1570 * TF-A assumes that all the cores in the platform has architecture feature parity 1571 * and hence the context is setup on different core (e.g. primary sets up the 1572 * context for secondary cores).This assumption may not be true for systems where 1573 * cores are not conforming to same Arch version or there is CPU Erratum which 1574 * requires certain feature to be be disabled only on a given core. 1575 * 1576 * This function is called on secondary cores to override any disparity in context 1577 * setup by primary, this would be called during warmboot path. 1578 *********************************************************************************/ 1579 void cm_handle_asymmetric_features(void) 1580 { 1581 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1582 1583 assert(ctx != NULL); 1584 1585 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1586 if (is_feat_spe_supported()) { 1587 spe_enable(ctx); 1588 } else { 1589 spe_disable(ctx); 1590 } 1591 #endif 1592 1593 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1594 if (check_if_affected_core() == ERRATA_APPLIES) { 1595 if (is_feat_trbe_supported()) { 1596 trbe_disable(ctx); 1597 } 1598 } 1599 #endif 1600 1601 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1602 el3_state_t *el3_state = get_el3state_ctx(ctx); 1603 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1604 1605 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1606 tcr2_enable(ctx); 1607 } else { 1608 tcr2_disable(ctx); 1609 } 1610 #endif 1611 1612 } 1613 #endif 1614 1615 /******************************************************************************* 1616 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1617 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1618 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1619 * cm_prepare_el3_exit function. 1620 ******************************************************************************/ 1621 void cm_prepare_el3_exit_ns(void) 1622 { 1623 #if IMAGE_BL31 1624 /* 1625 * Check and handle Architecture feature asymmetry among cores. 1626 * 1627 * In warmboot path secondary cores context is initialized on core which 1628 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1629 * it in this function call. 1630 * For Symmetric cores this is an empty function. 1631 */ 1632 cm_handle_asymmetric_features(); 1633 #endif 1634 1635 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1636 #if ENABLE_ASSERTIONS 1637 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1638 assert(ctx != NULL); 1639 1640 /* Assert that EL2 is used. */ 1641 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1642 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1643 (el_implemented(2U) != EL_IMPL_NONE)); 1644 #endif /* ENABLE_ASSERTIONS */ 1645 1646 /* Restore EL2 sysreg contexts */ 1647 cm_el2_sysregs_context_restore(NON_SECURE); 1648 cm_set_next_eret_context(NON_SECURE); 1649 #else 1650 cm_prepare_el3_exit(NON_SECURE); 1651 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1652 } 1653 1654 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1655 /******************************************************************************* 1656 * The next set of six functions are used by runtime services to save and restore 1657 * EL1 context on the 'cpu_context' structure for the specified security state. 1658 ******************************************************************************/ 1659 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1660 { 1661 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1662 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1663 1664 #if (!ERRATA_SPECULATIVE_AT) 1665 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1666 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1667 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1668 1669 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1670 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1671 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1672 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1673 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1674 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1675 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1676 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1677 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1678 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1679 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1680 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1681 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1682 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1683 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1684 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1685 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1686 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1687 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1688 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1689 1690 if (CTX_INCLUDE_AARCH32_REGS) { 1691 /* Save Aarch32 registers */ 1692 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1693 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1694 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1695 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1696 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1697 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1698 } 1699 1700 if (NS_TIMER_SWITCH) { 1701 /* Save NS Timer registers */ 1702 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1703 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1704 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1705 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1706 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1707 } 1708 1709 if (is_feat_mte2_supported()) { 1710 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1711 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1712 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1713 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1714 } 1715 1716 if (is_feat_ras_supported()) { 1717 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1718 } 1719 1720 if (is_feat_s1pie_supported()) { 1721 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1722 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1723 } 1724 1725 if (is_feat_s1poe_supported()) { 1726 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1727 } 1728 1729 if (is_feat_s2poe_supported()) { 1730 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1731 } 1732 1733 if (is_feat_tcr2_supported()) { 1734 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1735 } 1736 1737 if (is_feat_trf_supported()) { 1738 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1739 } 1740 1741 if (is_feat_csv2_2_supported()) { 1742 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1743 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1744 } 1745 1746 if (is_feat_gcs_supported()) { 1747 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1748 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1749 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1750 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1751 } 1752 1753 if (is_feat_the_supported()) { 1754 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1755 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1756 } 1757 1758 if (is_feat_sctlr2_supported()) { 1759 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1760 } 1761 1762 } 1763 1764 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1765 { 1766 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1767 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1768 1769 #if (!ERRATA_SPECULATIVE_AT) 1770 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1771 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1772 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1773 1774 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1775 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1776 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1777 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1778 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1779 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1780 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1781 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1782 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1783 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1784 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1785 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1786 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1787 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1788 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1789 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1790 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1791 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1792 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1793 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1794 1795 if (CTX_INCLUDE_AARCH32_REGS) { 1796 /* Restore Aarch32 registers */ 1797 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1798 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1799 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1800 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1801 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1802 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1803 } 1804 1805 if (NS_TIMER_SWITCH) { 1806 /* Restore NS Timer registers */ 1807 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1808 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1809 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1810 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1811 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1812 } 1813 1814 if (is_feat_mte2_supported()) { 1815 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1816 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1817 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1818 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1819 } 1820 1821 if (is_feat_ras_supported()) { 1822 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1823 } 1824 1825 if (is_feat_s1pie_supported()) { 1826 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1827 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1828 } 1829 1830 if (is_feat_s1poe_supported()) { 1831 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1832 } 1833 1834 if (is_feat_s2poe_supported()) { 1835 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1836 } 1837 1838 if (is_feat_tcr2_supported()) { 1839 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1840 } 1841 1842 if (is_feat_trf_supported()) { 1843 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1844 } 1845 1846 if (is_feat_csv2_2_supported()) { 1847 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1848 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1849 } 1850 1851 if (is_feat_gcs_supported()) { 1852 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1853 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1854 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1855 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1856 } 1857 1858 if (is_feat_the_supported()) { 1859 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1860 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1861 } 1862 1863 if (is_feat_sctlr2_supported()) { 1864 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1865 } 1866 1867 } 1868 1869 /******************************************************************************* 1870 * The next couple of functions are used by runtime services to save and restore 1871 * EL1 context on the 'cpu_context' structure for the specified security state. 1872 ******************************************************************************/ 1873 void cm_el1_sysregs_context_save(uint32_t security_state) 1874 { 1875 cpu_context_t *ctx; 1876 1877 ctx = cm_get_context(security_state); 1878 assert(ctx != NULL); 1879 1880 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1881 1882 #if IMAGE_BL31 1883 if (security_state == SECURE) 1884 PUBLISH_EVENT(cm_exited_secure_world); 1885 else 1886 PUBLISH_EVENT(cm_exited_normal_world); 1887 #endif 1888 } 1889 1890 void cm_el1_sysregs_context_restore(uint32_t security_state) 1891 { 1892 cpu_context_t *ctx; 1893 1894 ctx = cm_get_context(security_state); 1895 assert(ctx != NULL); 1896 1897 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1898 1899 #if IMAGE_BL31 1900 if (security_state == SECURE) 1901 PUBLISH_EVENT(cm_entering_secure_world); 1902 else 1903 PUBLISH_EVENT(cm_entering_normal_world); 1904 #endif 1905 } 1906 1907 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1908 1909 /******************************************************************************* 1910 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1911 * given security state with the given entrypoint 1912 ******************************************************************************/ 1913 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1914 { 1915 cpu_context_t *ctx; 1916 el3_state_t *state; 1917 1918 ctx = cm_get_context(security_state); 1919 assert(ctx != NULL); 1920 1921 /* Populate EL3 state so that ERET jumps to the correct entry */ 1922 state = get_el3state_ctx(ctx); 1923 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1924 } 1925 1926 /******************************************************************************* 1927 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1928 * pertaining to the given security state 1929 ******************************************************************************/ 1930 void cm_set_elr_spsr_el3(uint32_t security_state, 1931 uintptr_t entrypoint, uint32_t spsr) 1932 { 1933 cpu_context_t *ctx; 1934 el3_state_t *state; 1935 1936 ctx = cm_get_context(security_state); 1937 assert(ctx != NULL); 1938 1939 /* Populate EL3 state so that ERET jumps to the correct entry */ 1940 state = get_el3state_ctx(ctx); 1941 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1942 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1943 } 1944 1945 /******************************************************************************* 1946 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1947 * pertaining to the given security state using the value and bit position 1948 * specified in the parameters. It preserves all other bits. 1949 ******************************************************************************/ 1950 void cm_write_scr_el3_bit(uint32_t security_state, 1951 uint32_t bit_pos, 1952 uint32_t value) 1953 { 1954 cpu_context_t *ctx; 1955 el3_state_t *state; 1956 u_register_t scr_el3; 1957 1958 ctx = cm_get_context(security_state); 1959 assert(ctx != NULL); 1960 1961 /* Ensure that the bit position is a valid one */ 1962 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1963 1964 /* Ensure that the 'value' is only a bit wide */ 1965 assert(value <= 1U); 1966 1967 /* 1968 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1969 * and set it to its new value. 1970 */ 1971 state = get_el3state_ctx(ctx); 1972 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1973 scr_el3 &= ~(1UL << bit_pos); 1974 scr_el3 |= (u_register_t)value << bit_pos; 1975 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1976 } 1977 1978 /******************************************************************************* 1979 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1980 * given security state. 1981 ******************************************************************************/ 1982 u_register_t cm_get_scr_el3(uint32_t security_state) 1983 { 1984 cpu_context_t *ctx; 1985 el3_state_t *state; 1986 1987 ctx = cm_get_context(security_state); 1988 assert(ctx != NULL); 1989 1990 /* Populate EL3 state so that ERET jumps to the correct entry */ 1991 state = get_el3state_ctx(ctx); 1992 return read_ctx_reg(state, CTX_SCR_EL3); 1993 } 1994 1995 /******************************************************************************* 1996 * This function is used to program the context that's used for exception 1997 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1998 * the required security state 1999 ******************************************************************************/ 2000 void cm_set_next_eret_context(uint32_t security_state) 2001 { 2002 cpu_context_t *ctx; 2003 2004 ctx = cm_get_context(security_state); 2005 assert(ctx != NULL); 2006 2007 cm_set_next_context(ctx); 2008 } 2009