| 3bff910d | 15-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Introduce COT build option
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.
Right now, the only a
Introduce COT build option
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.
Right now, the only available CoT is TBBR.
Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 6de32378 | 28-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Add support for documentation build as a target in Makefile
Command to build HTML-formatted pages from docs:
make doc
Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9
Signed-off-by: Madhukar Pa
Add support for documentation build as a target in Makefile
Command to build HTML-formatted pages from docs:
make doc
Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| 8efec9e0 | 29-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I0fb7cf79,Ia8eb4710 into integration
* changes:
qemu: Implement qemu_system_off via semihosting.
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address. |
| 8c105290 | 23-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.
Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.
Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 91ff490d | 28-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Neovers N1: added support to update presence of External LLC" into integration |
| f2d6b4ee | 24-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal L
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
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|
| d974301d | 17-Jan-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
TSP: add PIE support
This implementation simply mimics that of BL31.
Change-Id: Ibbaa4ca012d38ac211c52b0b3e97449947160e07
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
| 69af7fcf | 17-Jan-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
BL2_AT_EL3: add PIE support
This implementation simply mimics that of BL31.
I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case.
It would make the linker script a bit uglier.
Chan
BL2_AT_EL3: add PIE support
This implementation simply mimics that of BL31.
I did not implement the ENABLE_PIE support for BL2_IN_XIP_MEM=1 case.
It would make the linker script a bit uglier.
Change-Id: If3215abd99f2758dfb232e44b50320d04eba808b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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|
| 208ebe7c | 23-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "xilinx: versal: PLM to ATF handover" into integration |
| 74464d5b | 15-Jan-2020 |
Andrew Walbran <qwandor@google.com> |
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
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|
| 09035d10 | 22-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
spm-mm: correcting instructions to build SPM for FVP
Out of two possible implementation of Secure Partition Manager(SPM)
currently only Management mode (MM) design is supported and the support
for S
spm-mm: correcting instructions to build SPM for FVP
Out of two possible implementation of Secure Partition Manager(SPM)
currently only Management mode (MM) design is supported and the support
for SPM based on SPCI Alpha 1 prototype has been removed.
Earlier both implementation used common build flag "ENABLE_SPM" but it
has since been decoupled and MM uses a separate build FLAG "SPM_MM".
Instructions to build it for FVP was still using "ENABLE_SPM", which has
beend corrected in this patch.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I505b98173d6051816436aa602ced6dbec4efc776
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|
| 31ce893e | 23-Jan-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xili
xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
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|
| f44d291f | 22-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "add-versal-soc-support" into integration
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx:
Merge changes from topic "add-versal-soc-support" into integration
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx: versal: Wire silicon default setup
versal: Increase OCM memory size for DEBUG builds
plat: xilinx: versal: Dont set IOU switch clock
arm64: versal: Adjust cpu clock for versal virtual
xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
plat: versal: Add Get_ChipID API
plat: xilinx: versal: Add load Pdi API support
xilinx: versal: Add feature check API
xilinx: versal: Implement set wakeup source for client
plat: xilinx: versal: Add GET_CALLBACK_DATA function
xilinx: versal: Add PSCI APIs for system shutdown & reset
xilinx: versal: Add PSCI APIs for suspend/resume
xilinx: versal: Remove no_pmc ops to ON power domain
xilinx: versal: Add set wakeup source API
xilinx: versal: Add client wakeup API
xilinx: versal: Add query data API
xilinx: versal: Add request wakeup API
xilinx: versal: Add PM_INIT_FINALIZE API for versal
xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
xilinx: versal: enable ipi mailbox service
xilinx: move ipi mailbox svc to xilinx common
plat: xilinx: versal: Implement PM IOCTL API
xilinx: versal: Implement power down/restart related EEMI API
xilinx: versal: Add SMC handler for EEMI API
xilinx: versal: Implement PLL related PM APIs
xilinx: versal: Implement clock related PM APIs
xilinx: versal: Implement pin control related PM APIs
xilinx: versal: Implement reset related PM APIs
xilinx: versal: Implement device related PM APIs
xilinx: versal: Add support for suspend related APIs
xilinx: versal: Add get_api_version support
xilinx: Add support to send PM API to PMC using IPI for versal
plat: xilinx: versal: Move versal_def.h to include directory
plat: xilinx: versal: Move versal_private.h to include directory
plat: xilinx: zynqmp: Use GIC framework for warm restart
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|
| c9c0b66f | 22-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Set lld as the default linker for Clang builds" into integration |
| 3b3d406e | 21-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs: Add upcoming Change Log to Table of Contents" into integration |
| ac7764bb | 17-Oct-2019 |
Lionel Debieve <lionel.debieve@st.com> |
doc: stm32mp1: Update build command line
Add new flags for storage support that must be used in the build
command line. Add the complete build steps for an OP-TEE configuration.
Signed-off-by: Lion
doc: stm32mp1: Update build command line
Add new flags for storage support that must be used in the build
command line. Add the complete build steps for an OP-TEE configuration.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I0c682f6eb0aab83aa929f4ba734d3151c264aeed
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|
| 641f16e7 | 17-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Set lld as the default linker for Clang builds
The LLVM linker replaces the GNU linker as default for the link on Clang
builds. It is possible to override the default linker by setting the LD build
Set lld as the default linker for Clang builds
The LLVM linker replaces the GNU linker as default for the link on Clang
builds. It is possible to override the default linker by setting the LD build
flag.
The patch also updates the TF-A doc.
Change-Id: Ic08552b9994d4fa8f0d4863e67a2726c1dce2e35
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
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|
| 992d2fe0 | 17-Jan-2020 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: Add upcoming Change Log to Table of Contents
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I2a7f38eaae3a78fc3caa37833af755c15e8236ce |
| 38aac6d4 | 16-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "docs: Creating a Change Log Template File" into integration |
| 7b9f0cfd | 10-Jul-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
plat: xilinx: versal: Make silicon default build target
This patch makes default build target as silicon instead of QEMU.
The default can be overwritten by specifying it through build flag
VERSAL_PL
plat: xilinx: versal: Make silicon default build target
This patch makes default build target as silicon instead of QEMU.
The default can be overwritten by specifying it through build flag
VERSAL_PLATFORM.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ia4cb1df1f206db3e514e8ce969acca875e973ace
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|
| 43309051 | 09-Dec-2019 |
Jan Kiszka <jan.kiszka@siemens.com> |
rpi4: Fix documentation of armstub config entry
It's in fact mandatory. Seen with RPi firmware 1.20190925.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26
rpi4: Fix documentation of armstub config entry
It's in fact mandatory. Seen with RPi firmware 1.20190925.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892
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|
| dadd8060 | 13-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "docs: GCC toolchain upgrade to version 9.2-2019.12" into integration |
| f35e5ab3 | 10-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs: GCC toolchain upgrade to version 9.2-2019.12
This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com
We build TF-A in CI using:
AArch32 bare-metal tar
docs: GCC toolchain upgrade to version 9.2-2019.12
This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com
We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)
Change-Id: I910200174d5bad985504d1af4a1ae5819b524003
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| 5b33ad17 | 13-Dec-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned i
Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.
Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.
2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent
Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.
Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
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|
| 3c0d784c | 09-Dec-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: Creating a Change Log Template File
Creating a Change Log Template for ALL to update with relevant
new features, changes, fixes and known issues for each upcoming
release of Trusted Firmware-A
docs: Creating a Change Log Template File
Creating a Change Log Template for ALL to update with relevant
new features, changes, fixes and known issues for each upcoming
release of Trusted Firmware-A.
The contents of this file should be added to the collective change log
at the time of release code freeze.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Idfbdcef0d40b10312dc88b6e1cbe31856fda887e
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|