Rename Cortex-Deimos to Cortex-A77

Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

Remove references to old project name from common files

The project has been renamed from "Arm Trusted Firmware (ATF)" to
"Trusted Firmware-A (TF-A)" long ago. A few references to the old
project na

Remove references to old project name from common files

The project has been renamed from "Arm Trusted Firmware (ATF)" to
"Trusted Firmware-A (TF-A)" long ago. A few references to the old
project name that still remained in various places have now been
removed.

This change doesn't affect any platform files. Any "ATF" references
inside platform files, still remain.

Change-Id: Id97895faa5b1845e851d4d50f5750de7a55bf99e
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Fix RST rendering problem

Change-Id: Ic5aab23b549d0bf8e0f7053b46fd59243214aac1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

rockchip: px30: support px30

px30 is a Quad-core soc and Cortex-a53 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspen

rockchip: px30: support px30

px30 is a Quad-core soc and Cortex-a53 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system

Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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docs: removing references to GitHub

Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge changes from topic "lw/n1_errata_fixes" into integration

* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262

Merge changes from topic "lw/n1_errata_fixes" into integration

* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262888
Workaround for Neoverse N1 erratum 1262606
Workaround for Neoverse N1 erratum 1257314
Workaround for Neoverse N1 erratum 1220197
Workaround for Neoverse N1 erratum 1207823
Workaround for Neoverse N1 erratum 1165347
Workaround for Neoverse N1 erratum 1130799
Workaround for Neoverse N1 erratum 1073348

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Workaround for Neoverse N1 erratum 1275112

Neoverse N1 erratum 1275112 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1275112

Neoverse N1 erratum 1275112 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1262888

Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1262888

Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1262606

Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1262606

Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1257314

Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1257314

Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1220197

Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the

Workaround for Neoverse N1 erratum 1220197

Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1207823

Neoverse N1 erratum 1207823 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1207823

Neoverse N1 erratum 1207823 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1165347

Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the

Workaround for Neoverse N1 erratum 1165347

Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1130799

Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1130799

Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Workaround for Neoverse N1 erratum 1073348

Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the imp

Workaround for Neoverse N1 erratum 1073348

Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge changes from topic "banned_api_list" into integration

* changes:
Fix the License header template in imx_aipstz.c
docs: Add the list of banned/use with caution APIs

docs: Add the list of banned/use with caution APIs

Credit to sam.ellis@arm.com for the input to create the list.

Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce
Signed-off-by: Soby Mathew <sob

docs: Add the list of banned/use with caution APIs

Credit to sam.ellis@arm.com for the input to create the list.

Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge "doc: Fix typo in file interrupt-framework-design.rst" into integration

Fix links in documentation

Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

doc: Fix typo in file interrupt-framework-design.rst

Signed-off-by: Peng Donglin <dolinux.peng@gmail.com>
Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc

Merge "doc: Isolate security-related build options" into integration

stm32mp1: update doc for U-Boot compilation

U-Boot should be compiled with stm32mp15_trusted_defconfig which is
supported since tag v2019.07-rc1 with commit [1].

The creation of the U-Boot binary w

stm32mp1: update doc for U-Boot compilation

U-Boot should be compiled with stm32mp15_trusted_defconfig which is
supported since tag v2019.07-rc1 with commit [1].

The creation of the U-Boot binary with stm32 header is done at U-Boot
compilation step, it is no more required to call the extra command.

[1] https://git.denx.de/?p=u-boot.git;a=commit;h=015289580f81

Change-Id: Ia875c22184785fc2e02ad07993a649069cd5ce34
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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doc: Isolate security-related build options

Reference security specific build options from the user guide.

Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67
Signed-off-by: Ambroise Vincent <ambr

doc: Isolate security-related build options

Reference security specific build options from the user guide.

Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Merge "Update maintainers list" into integration

Update maintainers list

Also sort alphabetically the links at the bottom, a couple of them were
not sorted.

Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <joh

Update maintainers list

Also sort alphabetically the links at the bottom, a couple of them were
not sorted.

Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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