| 8708a884 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
plat: marvell: armada: a3k: Allow use of the system Crypto++ library
This change introduces two new A3720 parameters, CRYPTOPP_LIBDIR and
CRYPTOPP_INCDIR, which can be used to specify directory path
plat: marvell: armada: a3k: Allow use of the system Crypto++ library
This change introduces two new A3720 parameters, CRYPTOPP_LIBDIR and
CRYPTOPP_INCDIR, which can be used to specify directory paths to
pre-compiled Crypto++ library and header files.
When both new parameters are specified then the source code of Crypto++ via
CRYPTOPP_PATH parameter is not needed. And therefore it allows TF-A build
process to use system Crypto++ library.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6d440f86153373b11b8d098bb68eb7325e86b20b
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|
| 494be3ee | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update info about WTP and MV_DDR_PATH parameters
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id5e36b7ba3a840cb3598c580e806b52d8e8dd70f |
| 26dccba6 | 27-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "scmi-msg" into integration
* changes:
doc: maintainers: add scmi server
drivers: move scmi-msg out of st |
| 70311692 | 26-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Fix documentation typos and misspellings" into integration |
| 1cea0213 | 26-Jan-2021 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
Marvell finally started providing the latest version of mv-ddr-marvell and
A3700-utils-marvell code in master branch of their gi
docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
Marvell finally started providing the latest version of mv-ddr-marvell and
A3700-utils-marvell code in master branch of their git repositories.
Reflect this in build instructions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I08d1189dac60eb2a28335c68f611c1da634106f6
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|
| 12b66a91 | 22-Jan-2021 |
Peng Fan <peng.fan@nxp.com> |
doc: maintainers: add scmi server
Add maintainer entry for scmi server
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I673d7395a8cea3b553832e330c8a8ce37f8c2a5c |
| 49e4a5fc | 24-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions" into integration |
| 47147013 | 21-Jan-2021 |
David Horstmann <david.horstmann@arm.com> |
Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4
Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
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|
| 6b2924bb | 20-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration
* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
rene
Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration
* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
renesas: rzg: emmc: Enable RZ/G2M support
plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
drivers: renesas: rzg: Add HiHope RZ/G2M board support
tools: renesas: Add tool support for RZ/G2 platforms
show more ...
|
| 6047a105 | 15-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2
Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2 SoC's
renesas: rzg: Add PFC support for RZ/G2M
renesas: rzg: Add QoS support for RZ/G2M
renesas: rzg: Add support for DRAM initialization
show more ...
|
| 337e4933 | 14-Jan-2021 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes I36e4d672,I47610cee into integration
* changes:
Workaround for Cortex N1 erratum 1946160
Workaround for Cortex A78 erratum 1951500 |
| d0b367b7 | 14-Jan-2021 |
Luka Kovacic <luka.kovacic@sartura.hr> |
docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions
The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).
Addi
docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions
The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).
Additionally building instructions are added for the GST ESPRESSObin-Ultra
board (1 GB, DDR4 RAM variant), which has been tested successfully and booted
TF-A on the board.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Change-Id: Ie5724df27c1ee2e8f6a52664520579e872471e93
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|
| 263ee781 | 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire at
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics. This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
show more ...
|
| 3a2710dc | 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic in
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
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|
| afda405b | 19-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Update RZ/G2 code owner list
Add Lad Prabhakar as the code owner for the newly added
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ic9bacaf31d653e1e
doc: renesas: Update RZ/G2 code owner list
Add Lad Prabhakar as the code owner for the newly added
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ic9bacaf31d653e1e553fa70043053805f56a2b84
show more ...
|
| d60642a4 | 19-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Update code owner for Renesas platforms
Add Marek Vasut as the code owner for the common code shared by
both Renesas R-Car and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp
doc: renesas: Update code owner for Renesas platforms
Add Marek Vasut as the code owner for the common code shared by
both Renesas R-Car and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I3c0a402f4663ffcf4d2df408a3ccd4d1a8629b3a
show more ...
|
| 2bc48585 | 07-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev
doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a
show more ...
|
| 06ea86fe | 13-Jan-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
show more ...
|
| e26c59d2 | 06-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, the
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
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|
| fde125cb | 06-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration |
| d9243f26 | 05-Jan-2021 |
Marek Behún <marek.behun@nic.cz> |
plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset h
plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)
The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f
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|
| 74ac817a | 10-Dec-2020 |
Nishanth Menon <nm@ti.com> |
maintainers: Update maintainers for TI port
Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cha
maintainers: Update maintainers for TI port
Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia1be294631421913bcbc3d346947195cb442d437
show more ...
|
| 669ee776 | 21-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_C
Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_CONFIG
plat: tc0: enable opteed support
plat: arm: Increase SP max size
show more ...
|
| 3f0d8369 | 16-Dec-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire ato
Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.
SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
show more ...
|
| 29a8814f | 15-Dec-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Add support for FEAT_MTPMU for Armv8.6" into integration |