| 2baf5038 | 07-Jul-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3k): Fix check for external dependences
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Ext
fix(plat/marvell/a3k): Fix check for external dependences
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
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| 528dafc3 | 28-Jun-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded a
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.
TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.
So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
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| 9fa5db4d | 05-Jul-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "sb/measured-boot" into integration
* changes:
refactor(plat/fvp): tidy up list of images to measure
docs: explain Measured Boot dependency on Trusted Boot |
| 80000975 | 01-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: update maintainer entry for nxp platform code" into integration |
| 75569c30 | 25-Mar-2021 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
docs: update maintainer entry for nxp platform code
Add maintainer entry for NXP platform code
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Idd5407b8a9c1aa50ba812b2b1a7ce45e8fac5027 |
| c1c14b34 | 30-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1" into integration |
| 81a8b2da | 30-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): enable SVE for the secure world" into integration |
| 204fd991 | 29-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "errata: workaround for Cortex A77 errata 1791578" into integration |
| cc255b9f | 10-Jun-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: explain Measured Boot dependency on Trusted Boot
Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| 7285fd5f | 10-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The un
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14bf
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
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| 0c5e7d1c | 22-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is conf
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
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| 1a691455 | 30-Apr-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
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| 3f0bec7c | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
h
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
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| 64b8db7e | 22-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(dt-bindings): align irq bindings with kernel" into integration |
| ed0f0a09 | 15-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "docs: change Linaro release version to 20.01" into integration |
| f1b6b014 | 25-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(dt-bindings): align irq bindings with kernel
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in
refactor(dt-bindings): align irq bindings with kernel
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in TF-A.
With this alignment, a new macro is added (GIC_CPU_MASK_SIMPLE).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib45174f35f1796ebb7f34af861b59810cfb808b0
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|
| dd0592c9 | 10-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: change owner for MediaTek platforms" into integration |
| e3c07d2f | 07-Jun-2021 |
Jacky Bai <ping.bai@nxp.com> |
docs(imx8m): update build support for imx8mq
Due to the small OCRAM space used for TF-A, we will
meet imx8mq build failure caused by too small RAM size.
We CANNOT support it in TF-A CI. It does NOT
docs(imx8m): update build support for imx8mq
Due to the small OCRAM space used for TF-A, we will
meet imx8mq build failure caused by too small RAM size.
We CANNOT support it in TF-A CI. It does NOT mean that
imx8mq will be dropped by NXP. NXP will still actively
maintain it in NXP official release.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iad726ffbc4eedc5f6770612bb9750986b9324ae9
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|
| 7737fdf0 | 06-Jun-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs: add threat model code owners" into integration |
| 99a99eb4 | 01-Jun-2021 |
Zelalem <zelalem.aweke@arm.com> |
docs: change Linaro release version to 20.01
We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm
docs: change Linaro release version to 20.01
We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173
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| b35f8f2d | 31-May-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(tc0): add support for trusted services" into integration |
| e55d12b7 | 27-May-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes:
TF-A: Document SMC_PCI_SUPPORT option
SMCCC/PCI: Handle std svc boilerplate
SMCCC/PCI: Add initial PCI con
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes:
TF-A: Document SMC_PCI_SUPPORT option
SMCCC/PCI: Handle std svc boilerplate
SMCCC/PCI: Add initial PCI conduit definitions
SMCCC: Hoist SMC_32 sanitization
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| 481c7b6b | 25-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(docs): fix typos in v2.5 release documentation
Two issues in documentation were identified after the release.
This patch fixes these typos.
1. Matternhorn ELP CPU was made available through v2.
fix(docs): fix typos in v2.5 release documentation
Two issues in documentation were identified after the release.
This patch fixes these typos.
1. Matternhorn ELP CPU was made available through v2.5 release, not
Matternhorn CPU
2. We had upgraded TF-A to use GCC 10.2 toolchain family and used this
toolchain for release testing
Change-Id: I33e59bb5a6d13f4d40dbb3352004d5b133431d65
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 2d31cb07 | 27-Jan-2021 |
Jeremy Linton <jeremy.linton@arm.com> |
TF-A: Document SMC_PCI_SUPPORT option
Add some basic documentation and pointers for the SMCCC PCI
build options.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ia35f31d15066ea74135
TF-A: Document SMC_PCI_SUPPORT option
Add some basic documentation and pointers for the SMCCC PCI
build options.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ia35f31d15066ea74135367cde2dce2f26e6ab31e
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| 1cf6340d | 03-May-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
docs: change owner for MediaTek platforms
Change owner for MediaTek platforms.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I60848a2c1b236cef61c2c22d8278197ad257b1c2 |