1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/smccc.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <platform_def.h> 19 #include <services/arm_arch_svc.h> 20 #if SPM_MM 21 #include <services/spm_mm_partition.h> 22 #endif 23 24 #include <plat/arm/common/arm_config.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 28 #include "fvp_private.h" 29 30 /* Defines for GIC Driver build time selection */ 31 #define FVP_GICV2 1 32 #define FVP_GICV3 2 33 34 /******************************************************************************* 35 * arm_config holds the characteristics of the differences between the three FVP 36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 37 * at each boot stage by the primary before enabling the MMU (to allow 38 * interconnect configuration) & used thereafter. Each BL will have its own copy 39 * to allow independent operation. 40 ******************************************************************************/ 41 arm_config_t arm_config; 42 43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 44 DEVICE0_SIZE, \ 45 MT_DEVICE | MT_RW | MT_SECURE) 46 47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 48 DEVICE1_SIZE, \ 49 MT_DEVICE | MT_RW | MT_SECURE) 50 51 /* 52 * Need to be mapped with write permissions in order to set a new non-volatile 53 * counter value. 54 */ 55 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 56 DEVICE2_SIZE, \ 57 MT_DEVICE | MT_RW | MT_SECURE) 58 59 /* 60 * Table of memory regions for various BL stages to map using the MMU. 61 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 62 * of mapping it. 63 * 64 * The flash needs to be mapped as writable in order to erase the FIP's Table of 65 * Contents in case of unrecoverable error (see plat_error_handler()). 66 */ 67 #ifdef IMAGE_BL1 68 const mmap_region_t plat_arm_mmap[] = { 69 ARM_MAP_SHARED_RAM, 70 V2M_MAP_FLASH0_RW, 71 V2M_MAP_IOFPGA, 72 MAP_DEVICE0, 73 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 74 MAP_DEVICE1, 75 #endif 76 #if TRUSTED_BOARD_BOOT 77 /* To access the Root of Trust Public Key registers. */ 78 MAP_DEVICE2, 79 /* Map DRAM to authenticate NS_BL2U image. */ 80 ARM_MAP_NS_DRAM1, 81 #endif 82 {0} 83 }; 84 #endif 85 #ifdef IMAGE_BL2 86 const mmap_region_t plat_arm_mmap[] = { 87 ARM_MAP_SHARED_RAM, 88 V2M_MAP_FLASH0_RW, 89 V2M_MAP_IOFPGA, 90 MAP_DEVICE0, 91 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 92 MAP_DEVICE1, 93 #endif 94 ARM_MAP_NS_DRAM1, 95 #ifdef __aarch64__ 96 ARM_MAP_DRAM2, 97 #endif 98 #if defined(SPD_spmd) 99 ARM_MAP_TRUSTED_DRAM, 100 #endif 101 #ifdef SPD_tspd 102 ARM_MAP_TSP_SEC_MEM, 103 #endif 104 #if TRUSTED_BOARD_BOOT 105 /* To access the Root of Trust Public Key registers. */ 106 MAP_DEVICE2, 107 #if !BL2_AT_EL3 108 ARM_MAP_BL1_RW, 109 #endif 110 #endif /* TRUSTED_BOARD_BOOT */ 111 #if SPM_MM 112 ARM_SP_IMAGE_MMAP, 113 #endif 114 #if ARM_BL31_IN_DRAM 115 ARM_MAP_BL31_SEC_DRAM, 116 #endif 117 #ifdef SPD_opteed 118 ARM_MAP_OPTEE_CORE_MEM, 119 ARM_OPTEE_PAGEABLE_LOAD_MEM, 120 #endif 121 {0} 122 }; 123 #endif 124 #ifdef IMAGE_BL2U 125 const mmap_region_t plat_arm_mmap[] = { 126 MAP_DEVICE0, 127 V2M_MAP_IOFPGA, 128 {0} 129 }; 130 #endif 131 #ifdef IMAGE_BL31 132 const mmap_region_t plat_arm_mmap[] = { 133 ARM_MAP_SHARED_RAM, 134 #if USE_DEBUGFS 135 /* Required by devfip, can be removed if devfip is not used */ 136 V2M_MAP_FLASH0_RW, 137 #endif /* USE_DEBUGFS */ 138 ARM_MAP_EL3_TZC_DRAM, 139 V2M_MAP_IOFPGA, 140 MAP_DEVICE0, 141 MAP_DEVICE1, 142 ARM_V2M_MAP_MEM_PROTECT, 143 #if SPM_MM 144 ARM_SPM_BUF_EL3_MMAP, 145 #endif 146 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 147 ARM_DTB_DRAM_NS, 148 {0} 149 }; 150 151 #if defined(IMAGE_BL31) && SPM_MM 152 const mmap_region_t plat_arm_secure_partition_mmap[] = { 153 V2M_MAP_IOFPGA_EL0, /* for the UART */ 154 MAP_REGION_FLAT(DEVICE0_BASE, \ 155 DEVICE0_SIZE, \ 156 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 157 ARM_SP_IMAGE_MMAP, 158 ARM_SP_IMAGE_NS_BUF_MMAP, 159 ARM_SP_IMAGE_RW_MMAP, 160 ARM_SPM_BUF_EL0_MMAP, 161 {0} 162 }; 163 #endif 164 #endif 165 #ifdef IMAGE_BL32 166 const mmap_region_t plat_arm_mmap[] = { 167 #ifndef __aarch64__ 168 ARM_MAP_SHARED_RAM, 169 ARM_V2M_MAP_MEM_PROTECT, 170 #endif 171 V2M_MAP_IOFPGA, 172 MAP_DEVICE0, 173 MAP_DEVICE1, 174 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 175 ARM_DTB_DRAM_NS, 176 {0} 177 }; 178 #endif 179 180 ARM_CASSERT_MMAP 181 182 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 183 static const int fvp_cci400_map[] = { 184 PLAT_FVP_CCI400_CLUS0_SL_PORT, 185 PLAT_FVP_CCI400_CLUS1_SL_PORT, 186 }; 187 188 static const int fvp_cci5xx_map[] = { 189 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 190 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 191 }; 192 193 static unsigned int get_interconnect_master(void) 194 { 195 unsigned int master; 196 u_register_t mpidr; 197 198 mpidr = read_mpidr_el1(); 199 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 200 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 201 202 assert(master < FVP_CLUSTER_COUNT); 203 return master; 204 } 205 #endif 206 207 #if defined(IMAGE_BL31) && SPM_MM 208 /* 209 * Boot information passed to a secure partition during initialisation. Linear 210 * indices in MP information will be filled at runtime. 211 */ 212 static spm_mm_mp_info_t sp_mp_info[] = { 213 [0] = {0x80000000, 0}, 214 [1] = {0x80000001, 0}, 215 [2] = {0x80000002, 0}, 216 [3] = {0x80000003, 0}, 217 [4] = {0x80000100, 0}, 218 [5] = {0x80000101, 0}, 219 [6] = {0x80000102, 0}, 220 [7] = {0x80000103, 0}, 221 }; 222 223 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 224 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 225 .h.version = VERSION_1, 226 .h.size = sizeof(spm_mm_boot_info_t), 227 .h.attr = 0, 228 .sp_mem_base = ARM_SP_IMAGE_BASE, 229 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 230 .sp_image_base = ARM_SP_IMAGE_BASE, 231 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 232 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 233 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 234 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 235 .sp_image_size = ARM_SP_IMAGE_SIZE, 236 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 237 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 238 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 239 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 240 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 241 .num_cpus = PLATFORM_CORE_COUNT, 242 .mp_info = &sp_mp_info[0], 243 }; 244 245 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 246 { 247 return plat_arm_secure_partition_mmap; 248 } 249 250 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 251 void *cookie) 252 { 253 return &plat_arm_secure_partition_boot_info; 254 } 255 #endif 256 257 /******************************************************************************* 258 * A single boot loader stack is expected to work on both the Foundation FVP 259 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 260 * SYS_ID register provides a mechanism for detecting the differences between 261 * these platforms. This information is stored in a per-BL array to allow the 262 * code to take the correct path.Per BL platform configuration. 263 ******************************************************************************/ 264 void __init fvp_config_setup(void) 265 { 266 unsigned int rev, hbi, bld, arch, sys_id; 267 268 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 269 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 270 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 271 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 272 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 273 274 if (arch != ARCH_MODEL) { 275 ERROR("This firmware is for FVP models\n"); 276 panic(); 277 } 278 279 /* 280 * The build field in the SYS_ID tells which variant of the GIC 281 * memory is implemented by the model. 282 */ 283 switch (bld) { 284 case BLD_GIC_VE_MMAP: 285 ERROR("Legacy Versatile Express memory map for GIC peripheral" 286 " is not supported\n"); 287 panic(); 288 break; 289 case BLD_GIC_A53A57_MMAP: 290 break; 291 default: 292 ERROR("Unsupported board build %x\n", bld); 293 panic(); 294 } 295 296 /* 297 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 298 * for the Foundation FVP. 299 */ 300 switch (hbi) { 301 case HBI_FOUNDATION_FVP: 302 arm_config.flags = 0; 303 304 /* 305 * Check for supported revisions of Foundation FVP 306 * Allow future revisions to run but emit warning diagnostic 307 */ 308 switch (rev) { 309 case REV_FOUNDATION_FVP_V2_0: 310 case REV_FOUNDATION_FVP_V2_1: 311 case REV_FOUNDATION_FVP_v9_1: 312 case REV_FOUNDATION_FVP_v9_6: 313 break; 314 default: 315 WARN("Unrecognized Foundation FVP revision %x\n", rev); 316 break; 317 } 318 break; 319 case HBI_BASE_FVP: 320 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 321 322 /* 323 * Check for supported revisions 324 * Allow future revisions to run but emit warning diagnostic 325 */ 326 switch (rev) { 327 case REV_BASE_FVP_V0: 328 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 329 break; 330 case REV_BASE_FVP_REVC: 331 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 332 ARM_CONFIG_FVP_HAS_CCI5XX); 333 break; 334 default: 335 WARN("Unrecognized Base FVP revision %x\n", rev); 336 break; 337 } 338 break; 339 default: 340 ERROR("Unsupported board HBI number 0x%x\n", hbi); 341 panic(); 342 } 343 344 /* 345 * We assume that the presence of MT bit, and therefore shifted 346 * affinities, is uniform across the platform: either all CPUs, or no 347 * CPUs implement it. 348 */ 349 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 350 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 351 } 352 353 354 void __init fvp_interconnect_init(void) 355 { 356 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 357 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 358 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 359 panic(); 360 } 361 362 plat_arm_interconnect_init(); 363 #else 364 uintptr_t cci_base = 0U; 365 const int *cci_map = NULL; 366 unsigned int map_size = 0U; 367 368 /* Initialize the right interconnect */ 369 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 370 cci_base = PLAT_FVP_CCI5XX_BASE; 371 cci_map = fvp_cci5xx_map; 372 map_size = ARRAY_SIZE(fvp_cci5xx_map); 373 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 374 cci_base = PLAT_FVP_CCI400_BASE; 375 cci_map = fvp_cci400_map; 376 map_size = ARRAY_SIZE(fvp_cci400_map); 377 } else { 378 return; 379 } 380 381 assert(cci_base != 0U); 382 assert(cci_map != NULL); 383 cci_init(cci_base, cci_map, map_size); 384 #endif 385 } 386 387 void fvp_interconnect_enable(void) 388 { 389 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 390 plat_arm_interconnect_enter_coherency(); 391 #else 392 unsigned int master; 393 394 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 395 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 396 master = get_interconnect_master(); 397 cci_enable_snoop_dvm_reqs(master); 398 } 399 #endif 400 } 401 402 void fvp_interconnect_disable(void) 403 { 404 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 405 plat_arm_interconnect_exit_coherency(); 406 #else 407 unsigned int master; 408 409 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 410 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 411 master = get_interconnect_master(); 412 cci_disable_snoop_dvm_reqs(master); 413 } 414 #endif 415 } 416 417 #if TRUSTED_BOARD_BOOT 418 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 419 { 420 assert(heap_addr != NULL); 421 assert(heap_size != NULL); 422 423 return arm_get_mbedtls_heap(heap_addr, heap_size); 424 } 425 #endif 426 427 void fvp_timer_init(void) 428 { 429 #if USE_SP804_TIMER 430 /* Enable the clock override for SP804 timer 0, which means that no 431 * clock dividers are applied and the raw (35MHz) clock will be used. 432 */ 433 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 434 435 /* Initialize delay timer driver using SP804 dual timer 0 */ 436 sp804_timer_init(V2M_SP804_TIMER0_BASE, 437 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 438 #else 439 generic_delay_timer_init(); 440 441 /* Enable System level generic timer */ 442 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 443 CNTCR_FCREQ(0U) | CNTCR_EN); 444 #endif /* USE_SP804_TIMER */ 445 } 446 447 /***************************************************************************** 448 * plat_is_smccc_feature_available() - This function checks whether SMCCC 449 * feature is availabile for platform. 450 * @fid: SMCCC function id 451 * 452 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 453 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 454 *****************************************************************************/ 455 int32_t plat_is_smccc_feature_available(u_register_t fid) 456 { 457 switch (fid) { 458 case SMCCC_ARCH_SOC_ID: 459 return SMC_ARCH_CALL_SUCCESS; 460 default: 461 return SMC_ARCH_CALL_NOT_SUPPORTED; 462 } 463 } 464 465 /* Get SOC version */ 466 int32_t plat_get_soc_version(void) 467 { 468 return (int32_t) 469 ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT) 470 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT) 471 | FVP_SOC_ID); 472 } 473 474 /* Get SOC revision */ 475 int32_t plat_get_soc_revision(void) 476 { 477 unsigned int sys_id; 478 479 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 480 return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) & 481 V2M_SYS_ID_REV_MASK); 482 } 483