| 263ee781 | 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire at
Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics. This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
show more ...
|
| 3a2710dc | 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic in
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
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|
| afda405b | 19-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Update RZ/G2 code owner list
Add Lad Prabhakar as the code owner for the newly added
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ic9bacaf31d653e1e
doc: renesas: Update RZ/G2 code owner list
Add Lad Prabhakar as the code owner for the newly added
RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ic9bacaf31d653e1e553fa70043053805f56a2b84
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|
| d60642a4 | 19-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Update code owner for Renesas platforms
Add Marek Vasut as the code owner for the common code shared by
both Renesas R-Car and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp
doc: renesas: Update code owner for Renesas platforms
Add Marek Vasut as the code owner for the common code shared by
both Renesas R-Car and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I3c0a402f4663ffcf4d2df408a3ccd4d1a8629b3a
show more ...
|
| 2bc48585 | 07-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev
doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a
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|
| 06ea86fe | 13-Jan-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
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|
| e26c59d2 | 06-Oct-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, the
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
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|
| fde125cb | 06-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration |
| d9243f26 | 05-Jan-2021 |
Marek Behún <marek.behun@nic.cz> |
plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset h
plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor
Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)
The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f
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|
| 74ac817a | 10-Dec-2020 |
Nishanth Menon <nm@ti.com> |
maintainers: Update maintainers for TI port
Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cha
maintainers: Update maintainers for TI port
Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia1be294631421913bcbc3d346947195cb442d437
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|
| 669ee776 | 21-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_C
Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_CONFIG
plat: tc0: enable opteed support
plat: arm: Increase SP max size
show more ...
|
| 3f0d8369 | 16-Dec-2020 |
johpow01 <john.powell@arm.com> |
Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire ato
Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.
SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
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|
| 29a8814f | 15-Dec-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Add support for FEAT_MTPMU for Armv8.6" into integration |
| be3a3bc7 | 08-Dec-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04
docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a
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|
| de155790 | 11-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "TF-A: Add build option for Arm Feature Modifiers" into integration |
| bd054fd6 | 11-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in mem
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in memory map
plat/arm/sgi: add platform id value for rdn2 platform
plat/arm/sgi: platform definitions for upcoming platforms
plat/arm/sgi: refactor header file inclusions
plat/arm/sgi: refactor the inclusion of memory mapping
show more ...
|
| 0063dd17 | 23-Nov-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happ
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
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|
| f1821790 | 07-Dec-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults t
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.
Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 745da67b | 25-Nov-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Update the FIP generation process using SP images
Updated the documentation for the FIP generation process using
SP images.
Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by:
docs: Update the FIP generation process using SP images
Updated the documentation for the FIP generation process using
SP images.
Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 7b24e48a | 08-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi
doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
show more ...
|
| 91cc872c | 02-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms" into integration |
| 25bbbd2d | 23-Oct-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
show more ...
|
| f20cb7e5 | 29-Oct-2020 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and inf
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and information about default values.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc957307b1b627b403a8d960e85f5ac9e15aee5
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|
| 7b12a8d6 | 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Revert workaround for A77 erratum 1800714" into integration |
| b9ad2bb8 | 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Revert workaround for A76 erratum 1800710" into integration |