| 182ce101 | 07-Oct-2020 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1940577
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acq
errata: workaround for Neoverse V1 errata 1940577
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acquire atomic instructions without release semantics.
This issue is present in revisions r0p0 - r1p1 but this workaround
only applies to revisions r1p0 - r1p1, there is no workaround for older
versions.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
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| 8cf5afaf | 19-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I2b3aa9bd,I3237199b into integration
* changes:
docs: add mt6795 to deprecated list
feat(plat/mediatek/mt8195): add DCM driver |
| 586aafa3 | 19-Jul-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1791573" into integration |
| fc3300a5 | 13-Jul-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
docs: add mt6795 to deprecated list
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be |
| 33e3e925 | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
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| c7911137 | 16-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(maintainers): add Julius Werner as Rockchip platform code owner" into integration |
| 8d15e46c | 12-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: update supported FVP models as per release 11.15.14
Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| c0cb6122 | 08-Jul-2021 |
Julius Werner <jwerner@chromium.org> |
docs(maintainers): add Julius Werner as Rockchip platform code owner
The two existing plat/rockchip code owners seem to be no longer active
in the project and are not responding to reviews. There ha
docs(maintainers): add Julius Werner as Rockchip platform code owner
The two existing plat/rockchip code owners seem to be no longer active
in the project and are not responding to reviews. There have been a
couple of small fixup patches[1][2][3] pending for months that couldn't
be checked in for lack of Code-Owner-Review+1 flag. Add myself to the
code owner list to unblock this bottleneck (I have been deeply involved
in the rk3399 port, at least, so I know most of the code reasonably
well).
[1] https://review.trustedfirmware.org/9616
[2] https://review.trustedfirmware.org/9990
[2] https://review.trustedfirmware.org/10415
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7b2bb73c35a9bea91ff46ee445a22819d2045d9
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| 2baf5038 | 07-Jul-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3k): Fix check for external dependences
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Ext
fix(plat/marvell/a3k): Fix check for external dependences
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
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| 528dafc3 | 28-Jun-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded a
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.
TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.
So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
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| 9fa5db4d | 05-Jul-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "sb/measured-boot" into integration
* changes:
refactor(plat/fvp): tidy up list of images to measure
docs: explain Measured Boot dependency on Trusted Boot |
| 80000975 | 01-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: update maintainer entry for nxp platform code" into integration |
| 75569c30 | 25-Mar-2021 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
docs: update maintainer entry for nxp platform code
Add maintainer entry for NXP platform code
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Idd5407b8a9c1aa50ba812b2b1a7ce45e8fac5027 |
| c1c14b34 | 30-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1" into integration |
| 81a8b2da | 30-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): enable SVE for the secure world" into integration |
| 204fd991 | 29-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "errata: workaround for Cortex A77 errata 1791578" into integration |
| cc255b9f | 10-Jun-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: explain Measured Boot dependency on Trusted Boot
Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| 7285fd5f | 10-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The un
feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14bf
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
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| 0c5e7d1c | 22-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is conf
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
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| 1a691455 | 30-Apr-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
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| 3f0bec7c | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
h
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
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| 64b8db7e | 22-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(dt-bindings): align irq bindings with kernel" into integration |
| ed0f0a09 | 15-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "docs: change Linaro release version to 20.01" into integration |
| f1b6b014 | 25-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(dt-bindings): align irq bindings with kernel
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in
refactor(dt-bindings): align irq bindings with kernel
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux.
Just copy the 2 files here. They both have MIT license which is accepted
in TF-A.
With this alignment, a new macro is added (GIC_CPU_MASK_SIMPLE).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib45174f35f1796ebb7f34af861b59810cfb808b0
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|
| dd0592c9 | 10-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: change owner for MediaTek platforms" into integration |