1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_PRIVATE_H 8 #define GICV3_PRIVATE_H 9 10 #include <assert.h> 11 #include <stdint.h> 12 13 #include <drivers/arm/gic_common.h> 14 #include <drivers/arm/gicv3.h> 15 #include <lib/mmio.h> 16 17 #include "../common/gic_common_private.h" 18 19 /******************************************************************************* 20 * GICv3 private macro definitions 21 ******************************************************************************/ 22 23 /* Constants to indicate the status of the RWP bit */ 24 #define RWP_TRUE U(1) 25 #define RWP_FALSE U(0) 26 27 /* Calculate GIC register bit number corresponding to its interrupt ID */ 28 #define BIT_NUM(REG, id) \ 29 ((id) & ((1U << REG##R_SHIFT) - 1U)) 30 31 /* 32 * Calculate 8, 32 and 64-bit GICD register offset 33 * corresponding to its interrupt ID 34 */ 35 #if GIC_EXT_INTID 36 /* GICv3.1 */ 37 #define GICD_OFFSET_8(REG, id) \ 38 (((id) <= MAX_SPI_ID) ? \ 39 GICD_##REG##R + (uintptr_t)(id) : \ 40 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID) 41 42 #define GICD_OFFSET(REG, id) \ 43 (((id) <= MAX_SPI_ID) ? \ 44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 45 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 46 REG##R_SHIFT) << 2)) 47 48 #define GICD_OFFSET_64(REG, id) \ 49 (((id) <= MAX_SPI_ID) ? \ 50 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \ 51 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ 52 REG##R_SHIFT) << 3)) 53 54 #else /* GICv3 */ 55 #define GICD_OFFSET_8(REG, id) \ 56 (GICD_##REG##R + (uintptr_t)(id)) 57 58 #define GICD_OFFSET(REG, id) \ 59 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 60 61 #define GICD_OFFSET_64(REG, id) \ 62 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3)) 63 #endif /* GIC_EXT_INTID */ 64 65 /* 66 * Read/Write 8, 32 and 64-bit GIC Distributor register 67 * corresponding to its interrupt ID 68 */ 69 #define GICD_READ(REG, base, id) \ 70 mmio_read_32((base) + GICD_OFFSET(REG, (id))) 71 72 #define GICD_READ_64(REG, base, id) \ 73 mmio_read_64((base) + GICD_OFFSET_64(REG, (id))) 74 75 #define GICD_WRITE_8(REG, base, id, val) \ 76 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val)) 77 78 #define GICD_WRITE(REG, base, id, val) \ 79 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val)) 80 81 #define GICD_WRITE_64(REG, base, id, val) \ 82 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val)) 83 84 /* 85 * Bit operations on GIC Distributor register corresponding 86 * to its interrupt ID 87 */ 88 /* Get bit in GIC Distributor register */ 89 #define GICD_GET_BIT(REG, base, id) \ 90 ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \ 91 BIT_NUM(REG, (id))) & 1U) 92 93 /* Set bit in GIC Distributor register */ 94 #define GICD_SET_BIT(REG, base, id) \ 95 mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \ 96 ((uint32_t)1 << BIT_NUM(REG, (id)))) 97 98 /* Clear bit in GIC Distributor register */ 99 #define GICD_CLR_BIT(REG, base, id) \ 100 mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \ 101 ((uint32_t)1 << BIT_NUM(REG, (id)))) 102 103 /* Write bit in GIC Distributor register */ 104 #define GICD_WRITE_BIT(REG, base, id) \ 105 mmio_write_32((base) + GICD_OFFSET(REG, (id)), \ 106 ((uint32_t)1 << BIT_NUM(REG, (id)))) 107 108 /* 109 * Calculate 8 and 32-bit GICR register offset 110 * corresponding to its interrupt ID 111 */ 112 #if GIC_EXT_INTID 113 /* GICv3.1 */ 114 #define GICR_OFFSET_8(REG, id) \ 115 (((id) <= MAX_PPI_ID) ? \ 116 GICR_##REG##R + (uintptr_t)(id) : \ 117 GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID)) 118 119 #define GICR_OFFSET(REG, id) \ 120 (((id) <= MAX_PPI_ID) ? \ 121 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ 122 GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\ 123 >> REG##R_SHIFT) << 2)) 124 #else /* GICv3 */ 125 #define GICR_OFFSET_8(REG, id) \ 126 (GICR_##REG##R + (uintptr_t)(id)) 127 128 #define GICR_OFFSET(REG, id) \ 129 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) 130 #endif /* GIC_EXT_INTID */ 131 132 /* Read/Write GIC Redistributor register corresponding to its interrupt ID */ 133 #define GICR_READ(REG, base, id) \ 134 mmio_read_32((base) + GICR_OFFSET(REG, (id))) 135 136 #define GICR_WRITE_8(REG, base, id, val) \ 137 mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val)) 138 139 #define GICR_WRITE(REG, base, id, val) \ 140 mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val)) 141 142 /* 143 * Bit operations on GIC Redistributor register 144 * corresponding to its interrupt ID 145 */ 146 /* Get bit in GIC Redistributor register */ 147 #define GICR_GET_BIT(REG, base, id) \ 148 ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \ 149 BIT_NUM(REG, (id))) & 1U) 150 151 /* Write bit in GIC Redistributor register */ 152 #define GICR_WRITE_BIT(REG, base, id) \ 153 mmio_write_32((base) + GICR_OFFSET(REG, (id)), \ 154 ((uint32_t)1 << BIT_NUM(REG, (id)))) 155 156 /* Set bit in GIC Redistributor register */ 157 #define GICR_SET_BIT(REG, base, id) \ 158 mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \ 159 ((uint32_t)1 << BIT_NUM(REG, (id)))) 160 161 /* Clear bit in GIC Redistributor register */ 162 #define GICR_CLR_BIT(REG, base, id) \ 163 mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \ 164 ((uint32_t)1 << BIT_NUM(REG, (id)))) 165 166 /* 167 * Macro to convert an mpidr to a value suitable for programming into a 168 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 169 * to GICv3. 170 */ 171 static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, 172 unsigned int irm) 173 { 174 return (mpidr & ~(U(0xff) << 24)) | 175 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); 176 } 177 178 /* 179 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 180 * are zeroes. 181 */ 182 #ifdef __aarch64__ 183 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 184 { 185 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | 186 ((typer_val >> 32) & U(0xffffff)); 187 } 188 #else 189 static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) 190 { 191 return (((typer_val) >> 32) & U(0xffffff)); 192 } 193 #endif 194 195 /******************************************************************************* 196 * GICv3 private global variables declarations 197 ******************************************************************************/ 198 extern const gicv3_driver_data_t *gicv3_driver_data; 199 200 /******************************************************************************* 201 * Private GICv3 function prototypes for accessing entire registers. 202 * Note: The raw register values correspond to multiple interrupt IDs and 203 * the number of interrupt IDs involved depends on the register accessed. 204 ******************************************************************************/ 205 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 206 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 207 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 208 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 209 210 /******************************************************************************* 211 * Private GICv3 function prototypes for accessing the GIC registers 212 * corresponding to a single interrupt ID. These functions use bitwise 213 * operations or appropriate register accesses to modify or return 214 * the bit-field corresponding the single interrupt ID. 215 ******************************************************************************/ 216 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 217 unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id); 218 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id); 219 unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id); 220 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 221 void gicr_set_igrpmodr(uintptr_t base, unsigned int id); 222 void gicr_set_isenabler(uintptr_t base, unsigned int id); 223 void gicr_set_icenabler(uintptr_t base, unsigned int id); 224 void gicr_set_ispendr(uintptr_t base, unsigned int id); 225 void gicr_set_icpendr(uintptr_t base, unsigned int id); 226 void gicr_set_igroupr(uintptr_t base, unsigned int id); 227 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 228 void gicr_clr_igrpmodr(uintptr_t base, unsigned int id); 229 void gicr_clr_igroupr(uintptr_t base, unsigned int id); 230 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 231 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg); 232 233 /******************************************************************************* 234 * Private GICv3 helper function prototypes 235 ******************************************************************************/ 236 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base); 237 void gicv3_spis_config_defaults(uintptr_t gicd_base); 238 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); 239 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 240 const interrupt_prop_t *interrupt_props, 241 unsigned int interrupt_props_num); 242 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 243 const interrupt_prop_t *interrupt_props, 244 unsigned int interrupt_props_num); 245 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 246 unsigned int rdistif_num, 247 uintptr_t gicr_base, 248 mpidr_hash_fn mpidr_to_core_pos); 249 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 250 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 251 252 /******************************************************************************* 253 * GIC Distributor interface accessors 254 ******************************************************************************/ 255 /* 256 * Wait for updates to: 257 * GICD_CTLR[2:0] - the Group Enables 258 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit 259 * GICD_ICENABLER<n> - the clearing of enable state for SPIs 260 */ 261 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 262 { 263 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) { 264 } 265 } 266 267 static inline uint32_t gicd_read_pidr2(uintptr_t base) 268 { 269 return mmio_read_32(base + GICD_PIDR2_GICV3); 270 } 271 272 static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id) 273 { 274 assert(id >= MIN_SPI_ID); 275 return GICD_READ_64(IROUTE, base, id); 276 } 277 278 static inline void gicd_write_irouter(uintptr_t base, 279 unsigned int id, 280 uint64_t affinity) 281 { 282 assert(id >= MIN_SPI_ID); 283 GICD_WRITE_64(IROUTE, base, id, affinity); 284 } 285 286 static inline void gicd_clr_ctlr(uintptr_t base, 287 unsigned int bitmap, 288 unsigned int rwp) 289 { 290 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 291 if (rwp != 0U) { 292 gicd_wait_for_pending_write(base); 293 } 294 } 295 296 static inline void gicd_set_ctlr(uintptr_t base, 297 unsigned int bitmap, 298 unsigned int rwp) 299 { 300 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 301 if (rwp != 0U) { 302 gicd_wait_for_pending_write(base); 303 } 304 } 305 306 /******************************************************************************* 307 * GIC Redistributor interface accessors 308 ******************************************************************************/ 309 static inline uint32_t gicr_read_ctlr(uintptr_t base) 310 { 311 return mmio_read_32(base + GICR_CTLR); 312 } 313 314 static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) 315 { 316 mmio_write_32(base + GICR_CTLR, val); 317 } 318 319 static inline uint64_t gicr_read_typer(uintptr_t base) 320 { 321 return mmio_read_64(base + GICR_TYPER); 322 } 323 324 static inline uint32_t gicr_read_waker(uintptr_t base) 325 { 326 return mmio_read_32(base + GICR_WAKER); 327 } 328 329 static inline void gicr_write_waker(uintptr_t base, uint32_t val) 330 { 331 mmio_write_32(base + GICR_WAKER, val); 332 } 333 334 /* 335 * Wait for updates to: 336 * GICR_ICENABLER0 337 * GICR_CTLR.DPG1S 338 * GICR_CTLR.DPG1NS 339 * GICR_CTLR.DPG0 340 * GICR_CTLR, which clears EnableLPIs from 1 to 0 341 */ 342 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 343 { 344 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { 345 } 346 } 347 348 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 349 { 350 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { 351 } 352 } 353 354 /* Private implementation of Distributor power control hooks */ 355 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 356 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 357 358 /******************************************************************************* 359 * GIC Redistributor functions for accessing entire registers. 360 * Note: The raw register values correspond to multiple interrupt IDs and 361 * the number of interrupt IDs involved depends on the register accessed. 362 ******************************************************************************/ 363 364 /* 365 * Accessors to read/write GIC Redistributor ICENABLER0 register 366 */ 367 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 368 { 369 return mmio_read_32(base + GICR_ICENABLER0); 370 } 371 372 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 373 { 374 mmio_write_32(base + GICR_ICENABLER0, val); 375 } 376 377 /* 378 * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE 379 * register corresponding to its number 380 */ 381 static inline unsigned int gicr_read_icenabler(uintptr_t base, 382 unsigned int reg_num) 383 { 384 return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2)); 385 } 386 387 static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num, 388 unsigned int val) 389 { 390 mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val); 391 } 392 393 /* 394 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers 395 */ 396 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 397 { 398 return mmio_read_32(base + GICR_ICFGR0); 399 } 400 401 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 402 { 403 return mmio_read_32(base + GICR_ICFGR1); 404 } 405 406 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 407 { 408 mmio_write_32(base + GICR_ICFGR0, val); 409 } 410 411 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 412 { 413 mmio_write_32(base + GICR_ICFGR1, val); 414 } 415 416 /* 417 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE 418 * register corresponding to its number 419 */ 420 static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num) 421 { 422 return mmio_read_32(base + GICR_ICFGR + (reg_num << 2)); 423 } 424 425 static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num, 426 unsigned int val) 427 { 428 mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val); 429 } 430 431 /* 432 * Accessor to write GIC Redistributor ICPENDR0 register 433 */ 434 static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val) 435 { 436 mmio_write_32(base + GICR_ICPENDR0, val); 437 } 438 439 /* 440 * Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE 441 * register corresponding to its number 442 */ 443 static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num, 444 unsigned int val) 445 { 446 mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val); 447 } 448 449 /* 450 * Accessors to read/write GIC Redistributor IGROUPR0 register 451 */ 452 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 453 { 454 return mmio_read_32(base + GICR_IGROUPR0); 455 } 456 457 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 458 { 459 mmio_write_32(base + GICR_IGROUPR0, val); 460 } 461 462 /* 463 * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE 464 * register corresponding to its number 465 */ 466 static inline unsigned int gicr_read_igroupr(uintptr_t base, 467 unsigned int reg_num) 468 { 469 return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2)); 470 } 471 472 static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num, 473 unsigned int val) 474 { 475 mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val); 476 } 477 478 /* 479 * Accessors to read/write GIC Redistributor IGRPMODR0 register 480 */ 481 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 482 { 483 return mmio_read_32(base + GICR_IGRPMODR0); 484 } 485 486 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 487 { 488 mmio_write_32(base + GICR_IGRPMODR0, val); 489 } 490 491 /* 492 * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE 493 * register corresponding to its number 494 */ 495 static inline unsigned int gicr_read_igrpmodr(uintptr_t base, 496 unsigned int reg_num) 497 { 498 return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2)); 499 } 500 501 static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num, 502 unsigned int val) 503 { 504 mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val); 505 } 506 507 /* 508 * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register 509 * corresponding to its number, 4 interrupts IDs at a time. 510 */ 511 static inline unsigned int gicr_ipriorityr_read(uintptr_t base, 512 unsigned int reg_num) 513 { 514 return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2)); 515 } 516 517 static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num, 518 unsigned int val) 519 { 520 mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val); 521 } 522 523 /* 524 * Accessors to read/write GIC Redistributor ISACTIVER0 register 525 */ 526 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 527 { 528 return mmio_read_32(base + GICR_ISACTIVER0); 529 } 530 531 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 532 { 533 mmio_write_32(base + GICR_ISACTIVER0, val); 534 } 535 536 /* 537 * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE 538 * register corresponding to its number 539 */ 540 static inline unsigned int gicr_read_isactiver(uintptr_t base, 541 unsigned int reg_num) 542 { 543 return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2)); 544 } 545 546 static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num, 547 unsigned int val) 548 { 549 mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val); 550 } 551 552 /* 553 * Accessors to read/write GIC Redistributor ISENABLER0 register 554 */ 555 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 556 { 557 return mmio_read_32(base + GICR_ISENABLER0); 558 } 559 560 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 561 { 562 mmio_write_32(base + GICR_ISENABLER0, val); 563 } 564 565 /* 566 * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE 567 * register corresponding to its number 568 */ 569 static inline unsigned int gicr_read_isenabler(uintptr_t base, 570 unsigned int reg_num) 571 { 572 return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2)); 573 } 574 575 static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num, 576 unsigned int val) 577 { 578 mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val); 579 } 580 581 /* 582 * Accessors to read/write GIC Redistributor ISPENDR0 register 583 */ 584 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 585 { 586 return mmio_read_32(base + GICR_ISPENDR0); 587 } 588 589 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 590 { 591 mmio_write_32(base + GICR_ISPENDR0, val); 592 } 593 594 /* 595 * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE 596 * register corresponding to its number 597 */ 598 static inline unsigned int gicr_read_ispendr(uintptr_t base, 599 unsigned int reg_num) 600 { 601 return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2)); 602 } 603 604 static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num, 605 unsigned int val) 606 { 607 mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val); 608 } 609 610 /* 611 * Accessors to read/write GIC Redistributor NSACR register 612 */ 613 static inline unsigned int gicr_read_nsacr(uintptr_t base) 614 { 615 return mmio_read_32(base + GICR_NSACR); 616 } 617 618 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 619 { 620 mmio_write_32(base + GICR_NSACR, val); 621 } 622 623 /* 624 * Accessors to read/write GIC Redistributor PROPBASER register 625 */ 626 static inline uint64_t gicr_read_propbaser(uintptr_t base) 627 { 628 return mmio_read_64(base + GICR_PROPBASER); 629 } 630 631 static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) 632 { 633 mmio_write_64(base + GICR_PROPBASER, val); 634 } 635 636 /* 637 * Accessors to read/write GIC Redistributor PENDBASER register 638 */ 639 static inline uint64_t gicr_read_pendbaser(uintptr_t base) 640 { 641 return mmio_read_64(base + GICR_PENDBASER); 642 } 643 644 static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) 645 { 646 mmio_write_64(base + GICR_PENDBASER, val); 647 } 648 649 /******************************************************************************* 650 * GIC ITS functions to read and write entire ITS registers. 651 ******************************************************************************/ 652 static inline uint32_t gits_read_ctlr(uintptr_t base) 653 { 654 return mmio_read_32(base + GITS_CTLR); 655 } 656 657 static inline void gits_write_ctlr(uintptr_t base, uint32_t val) 658 { 659 mmio_write_32(base + GITS_CTLR, val); 660 } 661 662 static inline uint64_t gits_read_cbaser(uintptr_t base) 663 { 664 return mmio_read_64(base + GITS_CBASER); 665 } 666 667 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 668 { 669 mmio_write_64(base + GITS_CBASER, val); 670 } 671 672 static inline uint64_t gits_read_cwriter(uintptr_t base) 673 { 674 return mmio_read_64(base + GITS_CWRITER); 675 } 676 677 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 678 { 679 mmio_write_64(base + GITS_CWRITER, val); 680 } 681 682 static inline uint64_t gits_read_baser(uintptr_t base, 683 unsigned int its_table_id) 684 { 685 assert(its_table_id < 8U); 686 return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); 687 } 688 689 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, 690 uint64_t val) 691 { 692 assert(its_table_id < 8U); 693 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); 694 } 695 696 /* 697 * Wait for Quiescent bit when GIC ITS is disabled 698 */ 699 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 700 { 701 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 702 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) { 703 } 704 } 705 706 #endif /* GICV3_PRIVATE_H */ 707