1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gic_common.h> 14 15 #include "../common/gic_common_private.h" 16 #include "gicv3_private.h" 17 18 /****************************************************************************** 19 * This function marks the core as awake in the re-distributor and 20 * ensures that the interface is active. 21 *****************************************************************************/ 22 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 23 { 24 /* 25 * The WAKER_PS_BIT should be changed to 0 26 * only when WAKER_CA_BIT is 1. 27 */ 28 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 29 30 /* Mark the connected core as awake */ 31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 32 33 /* Wait till the WAKER_CA_BIT changes to 0 */ 34 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 35 } 36 } 37 38 /****************************************************************************** 39 * This function marks the core as asleep in the re-distributor and ensures 40 * that the interface is quiescent. 41 *****************************************************************************/ 42 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 43 { 44 /* Mark the connected core as asleep */ 45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 46 47 /* Wait till the WAKER_CA_BIT changes to 1 */ 48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 49 } 50 } 51 52 /******************************************************************************* 53 * This function probes the Redistributor frames when the driver is initialised 54 * and saves their base addresses. These base addresses are used later to 55 * initialise each Redistributor interface. 56 ******************************************************************************/ 57 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 58 unsigned int rdistif_num, 59 uintptr_t gicr_base, 60 mpidr_hash_fn mpidr_to_core_pos) 61 { 62 u_register_t mpidr; 63 unsigned int proc_num; 64 uint64_t typer_val; 65 uintptr_t rdistif_base = gicr_base; 66 67 assert(rdistif_base_addrs != NULL); 68 69 /* 70 * Iterate over the Redistributor frames. Store the base address of each 71 * frame in the platform provided array. Use the "Processor Number" 72 * field to index into the array if the platform has not provided a hash 73 * function to convert an MPIDR (obtained from the "Affinity Value" 74 * field into a linear index. 75 */ 76 do { 77 typer_val = gicr_read_typer(rdistif_base); 78 if (mpidr_to_core_pos != NULL) { 79 mpidr = mpidr_from_gicr_typer(typer_val); 80 proc_num = mpidr_to_core_pos(mpidr); 81 } else { 82 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 83 TYPER_PROC_NUM_MASK; 84 } 85 86 if (proc_num < rdistif_num) { 87 rdistif_base_addrs[proc_num] = rdistif_base; 88 } 89 90 rdistif_base += (1U << GICR_PCPUBASE_SHIFT); 91 } while ((typer_val & TYPER_LAST_BIT) == 0U); 92 } 93 94 /******************************************************************************* 95 * Helper function to get the maximum SPI INTID + 1. 96 ******************************************************************************/ 97 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base) 98 { 99 unsigned int spi_limit; 100 unsigned int typer_reg = gicd_read_typer(gicd_base); 101 102 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */ 103 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 104 105 /* Filter out special INTIDs 1020-1023 */ 106 if (spi_limit > (MAX_SPI_ID + 1U)) { 107 return MAX_SPI_ID + 1U; 108 } 109 110 return spi_limit; 111 } 112 113 /******************************************************************************* 114 * Helper function to configure the default attributes of (E)SPIs. 115 ******************************************************************************/ 116 void gicv3_spis_config_defaults(uintptr_t gicd_base) 117 { 118 unsigned int i, num_ints; 119 #if GIC_EXT_INTID 120 unsigned int num_eints; 121 #endif 122 unsigned int typer_reg = gicd_read_typer(gicd_base); 123 124 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 125 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 126 127 /* 128 * The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so 129 * the maximum possible value for num_ints is 1024. Limit the value to 130 * MAX_SPI_ID + 1 to avoid getting wrong address in GICD_OFFSET() macro. 131 */ 132 if (num_ints > MAX_SPI_ID + 1U) { 133 num_ints = MAX_SPI_ID + 1U; 134 } 135 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1); 136 137 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 138 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 139 gicd_write_igroupr(gicd_base, i, ~0U); 140 } 141 142 #if GIC_EXT_INTID 143 /* Check if extended SPI range is implemented */ 144 if ((typer_reg & TYPER_ESPI) != 0U) { 145 /* 146 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 147 */ 148 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 149 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 150 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1); 151 152 for (i = MIN_ESPI_ID; i < num_eints; 153 i += (1U << IGROUPR_SHIFT)) { 154 gicd_write_igroupr(gicd_base, i, ~0U); 155 } 156 } else { 157 num_eints = 0U; 158 INFO("ESPI range is not implemented.\n"); 159 } 160 #endif 161 162 /* Setup the default (E)SPI priorities doing four at a time */ 163 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 164 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 165 } 166 167 #if GIC_EXT_INTID 168 for (i = MIN_ESPI_ID; i < num_eints; 169 i += (1U << IPRIORITYR_SHIFT)) { 170 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 171 } 172 #endif 173 /* 174 * Treat all (E)SPIs as level triggered by default, write 16 at a time 175 */ 176 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 177 gicd_write_icfgr(gicd_base, i, 0U); 178 } 179 180 #if GIC_EXT_INTID 181 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 182 gicd_write_icfgr(gicd_base, i, 0U); 183 } 184 #endif 185 } 186 187 /******************************************************************************* 188 * Helper function to configure properties of secure (E)SPIs 189 ******************************************************************************/ 190 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 191 const interrupt_prop_t *interrupt_props, 192 unsigned int interrupt_props_num) 193 { 194 unsigned int i; 195 const interrupt_prop_t *current_prop; 196 unsigned long long gic_affinity_val; 197 unsigned int ctlr_enable = 0U; 198 199 /* Make sure there's a valid property array */ 200 if (interrupt_props_num > 0U) { 201 assert(interrupt_props != NULL); 202 } 203 204 for (i = 0U; i < interrupt_props_num; i++) { 205 current_prop = &interrupt_props[i]; 206 207 unsigned int intr_num = current_prop->intr_num; 208 209 /* Skip SGI, (E)PPI and LPI interrupts */ 210 if (!IS_SPI(intr_num)) { 211 continue; 212 } 213 214 /* Configure this interrupt as a secure interrupt */ 215 gicd_clr_igroupr(gicd_base, intr_num); 216 217 /* Configure this interrupt as G0 or a G1S interrupt */ 218 assert((current_prop->intr_grp == INTR_GROUP0) || 219 (current_prop->intr_grp == INTR_GROUP1S)); 220 221 if (current_prop->intr_grp == INTR_GROUP1S) { 222 gicd_set_igrpmodr(gicd_base, intr_num); 223 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 224 } else { 225 gicd_clr_igrpmodr(gicd_base, intr_num); 226 ctlr_enable |= CTLR_ENABLE_G0_BIT; 227 } 228 229 /* Set interrupt configuration */ 230 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg); 231 232 /* Set the priority of this interrupt */ 233 gicd_set_ipriorityr(gicd_base, intr_num, 234 current_prop->intr_pri); 235 236 /* Target (E)SPIs to the primary CPU */ 237 gic_affinity_val = 238 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 239 gicd_write_irouter(gicd_base, intr_num, 240 gic_affinity_val); 241 242 /* Enable this interrupt */ 243 gicd_set_isenabler(gicd_base, intr_num); 244 } 245 246 return ctlr_enable; 247 } 248 249 /******************************************************************************* 250 * Helper function to configure the default attributes of (E)SPIs 251 ******************************************************************************/ 252 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 253 { 254 unsigned int i, ppi_regs_num, regs_num; 255 256 #if GIC_EXT_INTID 257 /* Calculate number of PPI registers */ 258 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 259 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 260 /* All other values except PPInum [0-2] are reserved */ 261 if (ppi_regs_num > 3U) { 262 ppi_regs_num = 1U; 263 } 264 #else 265 ppi_regs_num = 1U; 266 #endif 267 /* 268 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 269 * This is a more scalable approach as it avoids clearing 270 * the enable bits in the GICD_CTLR. 271 */ 272 for (i = 0U; i < ppi_regs_num; ++i) { 273 gicr_write_icenabler(gicr_base, i, ~0U); 274 } 275 276 /* Wait for pending writes to GICR_ICENABLER */ 277 gicr_wait_for_pending_write(gicr_base); 278 279 /* 32 interrupt IDs per GICR_IGROUPR register */ 280 for (i = 0U; i < ppi_regs_num; ++i) { 281 /* Treat all SGIs/(E)PPIs as G1NS by default */ 282 gicr_write_igroupr(gicr_base, i, ~0U); 283 } 284 285 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 286 regs_num = ppi_regs_num << 3; 287 for (i = 0U; i < regs_num; ++i) { 288 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 289 gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL); 290 } 291 292 /* 16 interrupt IDs per GICR_ICFGR register */ 293 regs_num = ppi_regs_num << 1; 294 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 295 /* Configure all (E)PPIs as level triggered by default */ 296 gicr_write_icfgr(gicr_base, i, 0U); 297 } 298 } 299 300 /******************************************************************************* 301 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 302 ******************************************************************************/ 303 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 304 const interrupt_prop_t *interrupt_props, 305 unsigned int interrupt_props_num) 306 { 307 unsigned int i; 308 const interrupt_prop_t *current_prop; 309 unsigned int ctlr_enable = 0U; 310 311 /* Make sure there's a valid property array */ 312 if (interrupt_props_num > 0U) { 313 assert(interrupt_props != NULL); 314 } 315 316 for (i = 0U; i < interrupt_props_num; i++) { 317 current_prop = &interrupt_props[i]; 318 319 unsigned int intr_num = current_prop->intr_num; 320 321 /* Skip (E)SPI interrupt */ 322 if (!IS_SGI_PPI(intr_num)) { 323 continue; 324 } 325 326 /* Configure this interrupt as a secure interrupt */ 327 gicr_clr_igroupr(gicr_base, intr_num); 328 329 /* Configure this interrupt as G0 or a G1S interrupt */ 330 assert((current_prop->intr_grp == INTR_GROUP0) || 331 (current_prop->intr_grp == INTR_GROUP1S)); 332 333 if (current_prop->intr_grp == INTR_GROUP1S) { 334 gicr_set_igrpmodr(gicr_base, intr_num); 335 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 336 } else { 337 gicr_clr_igrpmodr(gicr_base, intr_num); 338 ctlr_enable |= CTLR_ENABLE_G0_BIT; 339 } 340 341 /* Set the priority of this interrupt */ 342 gicr_set_ipriorityr(gicr_base, intr_num, 343 current_prop->intr_pri); 344 345 /* 346 * Set interrupt configuration for (E)PPIs. 347 * Configurations for SGIs 0-15 are ignored. 348 */ 349 if (intr_num >= MIN_PPI_ID) { 350 gicr_set_icfgr(gicr_base, intr_num, 351 current_prop->intr_cfg); 352 } 353 354 /* Enable this interrupt */ 355 gicr_set_isenabler(gicr_base, intr_num); 356 } 357 358 return ctlr_enable; 359 } 360 361 /** 362 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region 363 * @gicr_frame: base address of the GICR region to check 364 * 365 * This iterates over the GICR_TYPER registers of multiple GICR frames in 366 * a GICR region, to find the instance which has the LAST bit set. For most 367 * systems this corresponds to the number of cores handled by a redistributor, 368 * but there could be disabled cores among them. 369 * It assumes that each GICR region is fully accessible (till the LAST bit 370 * marks the end of the region). 371 * If a platform has multiple GICR regions, this function would need to be 372 * called multiple times, providing the respective GICR base address each time. 373 * 374 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) 375 ******************************************************************************/ 376 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) 377 { 378 uintptr_t rdistif_base = gicr_frame; 379 unsigned int count; 380 381 for (count = 1; count < PLATFORM_CORE_COUNT; count++) { 382 if ((gicr_read_typer(rdistif_base) & TYPER_LAST_BIT) != 0U) { 383 break; 384 } 385 rdistif_base += (1U << GICR_PCPUBASE_SHIFT); 386 } 387 388 return count; 389 } 390