fix(cpus): workaround for Cortex-A76 erratum 2743102

Cortex-A76 erratum 2743102 is a Cat B erratum that applies to
all revisions <=r4p1 and is still open. The workaround is to
insert a dsb before th

fix(cpus): workaround for Cortex-A76 erratum 2743102

Cortex-A76 erratum 2743102 is a Cat B erratum that applies to
all revisions <=r4p1 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN885749/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie2cd73bd91417d30b5633d80b2fbee32944bc2de

show more ...

fix(cpus): workaround for Neoverse N1 erratum 2743102

Neoverse N1 erratum 2743102 is a Cat B erratum that applies to
all revisions <=r4p1 and is still open. The workaround is to
insert a dsb before

fix(cpus): workaround for Neoverse N1 erratum 2743102

Neoverse N1 erratum 2743102 is a Cat B erratum that applies to
all revisions <=r4p1 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN885747/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I81a8793c1a118764df3ac97b67f5e088f56f6a20

show more ...

docs(spm): update FF-A manifest binding

Added action in response to Non-secure interrupt attribute to the
partition manifest.

Change-Id: I1d4f85e58b2f1fea7230dffc6a4361f7fd65be15
Signed-off-by: Mad

docs(spm): update FF-A manifest binding

Added action in response to Non-secure interrupt attribute to the
partition manifest.

Change-Id: I1d4f85e58b2f1fea7230dffc6a4361f7fd65be15
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

Merge "chore(docs): update supported FVP models doc" into integration

chore(docs): update supported FVP models doc

Update supported models list according to changes for v2.8 release in
ci/tf-a-ci-scripts repository

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeiste

chore(docs): update supported FVP models doc

Update supported models list according to changes for v2.8 release in
ci/tf-a-ci-scripts repository

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica7e062db77237220bcd861837f392496db1653a

show more ...

Merge "build: deprecate Arm rdn1edge and sgi575 FVP platforms" into integration

Merge changes from topic "db/deps" into integration

* changes:
feat(compiler-rt): update compiler-rt source files
fix(deps): add missing aeabi_memcpy.S
feat(zlib): update zlib source files
d

Merge changes from topic "db/deps" into integration

* changes:
feat(compiler-rt): update compiler-rt source files
fix(deps): add missing aeabi_memcpy.S
feat(zlib): update zlib source files
docs(changelog): add zlib and compiler-rt scope
feat(libfdt): upgrade libfdt source files
docs(prerequisites): upgrade to Mbed TLS 2.28.1

show more ...

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
docs(spm): add threat model for el3 spmc
docs(spm): add design documentation

fix(cpus): workaround for Cortex-A710 erratum 2291219

Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CP

fix(cpus): workaround for Cortex-A710 erratum 2291219

Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691

show more ...

fix(cpus): workaround for Cortex-X3 erratum 2313909

Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions
r0p0 and r1p0, and is fixed in r1p1. The workaround is to set
CPUACTLR2_EL1

fix(cpus): workaround for Cortex-X3 erratum 2313909

Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions
r0p0 and r1p0, and is fixed in r1p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d

show more ...

fix(cpus): workaround for Neoverse-N2 erratum 2326639

Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to

fix(cpus): workaround for Neoverse-N2 erratum 2326639

Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to
1 before the power down sequence that sets CORE_PWRDN_EN. This allows
the cpu to retry the power down and prevents the deadlock. TF-A never
clears this bit even if it wakes up from the wfi in the sequence since
it is not expected to do anything but retry to power down after and the
bit is cleared on reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest/

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9a325c5b9b498798e5efd5c79a4a6d5bed97c619

show more ...

fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour

Platforms which implement pwr_domain_pwr_down_wfi differ substantially
in behaviour. However, different cpus require similar sequences t

fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour

Platforms which implement pwr_domain_pwr_down_wfi differ substantially
in behaviour. However, different cpus require similar sequences to power
down. This patch tightens the behaviour of these platforms to end on a
wfi loop after performing platform power down. This is required so that
platforms behave more consistently on power down, in cases where the wfi
can fall through.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie29bd3a5e654780bacb4e07a6d123ac6d2467c1f

show more ...

docs(spm): add threat model for el3 spmc

Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Cha

docs(spm): add threat model for el3 spmc

Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I7f4c9370b6eefe6d1a7d1afac27e8b3a7b476072

show more ...

docs(spm): add design documentation

Add documentation how to build EL3 SPMC,
briefly describes all FF-A interfaces,
SP boot flow, SP Manifest, Power Management,
Boot Info Protocol, Runtime model and

docs(spm): add design documentation

Add documentation how to build EL3 SPMC,
briefly describes all FF-A interfaces,
SP boot flow, SP Manifest, Power Management,
Boot Info Protocol, Runtime model and state
transition and Interrupt Handling.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I630df1d50a4621b344a09e462563eacc90109de4

show more ...

chore: rename Makalu ELP to Cortex-X3

The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.

Si

chore: rename Makalu ELP to Cortex-X3

The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iebb90cf2f77330ed848a3d61c5f6928942189c5a

show more ...

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and map required memory blocks
feat(imx8mn): add hab and map required memory blocks
feat(imx8mm): add hab and map required memory blocks

show more ...

build: deprecate Arm rdn1edge and sgi575 FVP platforms

Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discon

build: deprecate Arm rdn1edge and sgi575 FVP platforms

Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discontinued. rdn1edge platform has been superseded by the
rdn2 platform, which is already supported in TF-A and CI work is
underway for this platform.

Change-Id: If2228fb73549b244c3a5b0e5746617b3f24fe771
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge "fix(cpus): workaround for Cortex-A510 erratum 2666669" into integration

Merge "feat(ethos-n)!: add support for SMMU streams" into integration

docs(imx8m): update for high assurance boot

Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentatio

docs(imx8m): update for high assurance boot

Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentation.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: Iaca97f4ac2595e35de2664a880394519f96eca07

show more ...

docs(prerequisites): upgrade to Mbed TLS 2.28.1

In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].

Note that the Mbed TLS project published version 3

docs(prerequisites): upgrade to Mbed TLS 2.28.1

In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].

Note that the Mbed TLS project published version 3.x some time ago.
However, as this is a major release with API breakages, upgrading to
this one might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to Mbed TLS 3.x after the v2.8 release
of TF-A.

[1] https://github.com/Mbed-TLS/mbedtls/tree/v2.28.1

Change-Id: I7594ad062a693d2ecc3b1705e944dce2c3c43bb2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

show more ...

docs(maintainers): add NPU driver owners

Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.

Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael

docs(maintainers): add NPU driver owners

Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.

Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2666669

Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower,
and is fixed in r1p2. The errata is mitigated by setting
IMP_CPUACTLR_EL1[38] t

fix(cpus): workaround for Cortex-A510 erratum 2666669

Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower,
and is fixed in r1p2. The errata is mitigated by setting
IMP_CPUACTLR_EL1[38] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ief27e4a155e43e75f05f2710d0c7bd5da2dec43f

show more ...

Merge changes from topic "fvp_dts_rework" into integration

* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix

Merge changes from topic "fvp_dts_rework" into integration

* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix memtimer subframe addressing
feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel
refactor(fvp): fdts: consolidate GICv2 base FVP DT files
refactor(fvp): fdts: consolidate GICv3 base FVP DT files
feat(fvp): dts: drop 32-bit .dts files
refactor(fvp): fdts: merge motherboard .dtsi files
refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
fix(fvp): fdts: unify and fix PSCI nodes

show more ...

feat(fvp): dts: drop 32-bit .dts files

Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and

feat(fvp): dts: drop 32-bit .dts files

Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and aarch64 does not make sense and is not needed.

Probably due to historic reasons (a Linux bug fixed in 2016 with Linux
commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a
different size between aarch64 and aarch32, even though the size of it
is solely governed by the parent's #address-cells property.

Consolidate this to be always 2, and always use two cells to describe
the CPU's MPIDR register.

This removes the last difference of the -aarch32 versions of the FVP
DT files, so just remove all of them. The respective versions without
that suffix can now be used with AArch32 DT clients as well.

Also remove the respective part in the documentation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e

show more ...