Merge "feat(rng-trap): add EL3 support for FEAT_RNG_TRAP" into integration

feat(rng-trap): add EL3 support for FEAT_RNG_TRAP

FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This

feat(rng-trap): add EL3 support for FEAT_RNG_TRAP

FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This patch adds a new build flag
ENABLE_FEAT_RNG_TRAP that enables the feature.
This feature is supported only in AArch64 state from Armv8.5 onwards.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89

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fix(errata): workaround for Neoverse-N2 erratum 2376738

Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTL

fix(errata): workaround for Neoverse-N2 erratum 2376738

Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
behave like PLD/PRFM LD and not cause invalidations to other
PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4ad4434f9b7210244e67046d9657d218857dced5

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docs(marvell): document UART image downloading

For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my

docs(marvell): document UART image downloading

For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my own mvebu64boot tool.

Add documentation how to build these tools and how to download TF-A
image over UART to boot TF-A without flashing it to non-volatile
storage.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa03584010a9c40496a34e6d5b9f3b78cb2cc89b

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Merge "fix(errata): workaround for Neoverse-V1 erratum 1618635" into integration

Merge "feat(sve): support full SVE vector length" into integration

docs(juno): fix broken link

The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.

Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9

docs(juno): fix broken link

The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.

Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9eda619906cdb5d

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fix(errata): workaround for Neoverse-V1 erratum 1618635

Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruct

fix(errata): workaround for Neoverse-V1 erratum 1618635

Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruction patching
mechanism, which is performed by a write sequence of
IMPLEMENTATION DEFINED registers.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest/

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168

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Merge "feat(tc): introduce TC2 platform" into integration

Merge "docs(maintainers): switch emails from Xilinx to AMD" into integration

docs(maintainers): switch emails from Xilinx to AMD

Switch emails from Xilinx to AMD after acquisition.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883

docs(maintainers): switch emails from Xilinx to AMD

Switch emails from Xilinx to AMD after acquisition.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883a9474206fc

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feat(tc): introduce TC2 platform

Added a platform support to use tc2 specific CPU cores.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e4

feat(tc): introduce TC2 platform

Added a platform support to use tc2 specific CPU cores.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd

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Merge "fix(doc): document missing RMM-EL3 runtime services" into integration

Merge "fix(errata): workaround for Cortex-X2 erratum 2371105" into integration

fix(errata): workaround for Cortex-X2 erratum 2371105

Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPU

fix(errata): workaround for Cortex-X2 erratum 2371105

Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad

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Merge "fix(errata): workaround for Cortex A78C erratum 2242638" into integration

fix(doc): document missing RMM-EL3 runtime services

This patch adds documentation for the missing RMM-EL3
runtime services:

* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE

This pa

fix(doc): document missing RMM-EL3 runtime services

This patch adds documentation for the missing RMM-EL3
runtime services:

* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE

This patch also fixes a couple of minor bugs on return codes
for delegate/undelegate internal APIs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ic721005e7851e838eebaee7865ba78fadc3309e4

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Merge "fix(errata): workaround for Cortex-A710 erratum 2371105" into integration

fix(errata): workaround for Cortex-A710 erratum 2371105

Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of

fix(errata): workaround for Cortex-A710 erratum 2371105

Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I342b095b66f808bd6c066c20c581df5341bb7c2c

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fix(errata): workaround for Cortex A78C erratum 2242638

Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU imple

fix(errata): workaround for Cortex A78C erratum 2242638

Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU implementation specific specific patch sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I35d385245a04a39b87be71c1a42312f75e1152e5

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Merge "docs(security): update info on use of OpenSSL 3.0" into integration

docs(security): update info on use of OpenSSL 3.0

OpenSSL 3.0 is a pre-requisite since v2.7 and can be installed
on the operating system by updating the previous version.
However, this may not be co

docs(security): update info on use of OpenSSL 3.0

OpenSSL 3.0 is a pre-requisite since v2.7 and can be installed
on the operating system by updating the previous version.
However, this may not be convenient for everyone, as some may
want to keep their previous versions of OpenSSL.

This update on the docs shows that there is an alternative to
install OpenSSL on the system by using a local build of
OpenSSL 3.0 and pointing both the build and run commands to
that build.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ib9ad9ee5c333f7b04e2747ae02433aa66e6397f3

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Merge "docs: re-parent BL2 platform hooks for measured boot" into integration

fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 t

fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2

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docs: re-parent BL2 platform hooks for measured boot

bl2_plat_mboot_init/finish() functions documentation was incorrectly
hooked up to BL2U-specific section.

Change-Id: I758cb8142e992b0c85ee36d5671

docs: re-parent BL2 platform hooks for measured boot

bl2_plat_mboot_init/finish() functions documentation was incorrectly
hooked up to BL2U-specific section.

Change-Id: I758cb8142e992b0c85ee36d5671fc9ecd5bde29b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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