1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24/* -------------------------------------------------- 25 * Errata Workaround for A78C Erratum 2132064. 26 * This applies to revisions r0p1 and r0p2 of A78C 27 * and is still open. 28 * Inputs: 29 * x0: variant[4:7] and revision[0:3] of current cpu. 30 * Shall clobber: x0-x17 31 * -------------------------------------------------- 32 */ 33func errata_a78c_2132064_wa 34 /* Compare x0 against revisions r0p0 - r0p1 */ 35 mov x17, x30 36 bl check_errata_2132064 37 cbz x0, 1f 38 39 /* -------------------------------------------------------- 40 * Place the data prefetcher in the most conservative mode 41 * to reduce prefetches by writing the following bits to 42 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 43 * -------------------------------------------------------- 44 */ 45 mrs x0, CORTEX_A78C_CPUECTLR_EL1 46 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT6 47 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT7 48 msr CORTEX_A78C_CPUECTLR_EL1, x0 49 isb 501: 51 ret x17 52endfunc errata_a78c_2132064_wa 53 54func check_errata_2132064 55 /* Applies to revisions r0p1 and r0p2. */ 56 mov x1, #CPU_REV(0, 1) 57 mov x2, #CPU_REV(0, 2) 58 b cpu_rev_var_range 59endfunc check_errata_2132064 60 61/* -------------------------------------------------------------------- 62 * Errata Workaround for A78C Erratum 2242638. 63 * This applies to revisions r0p1 and r0p2 of the Cortex A78C 64 * processor and is still open. 65 * x0: variant[4:7] and revision[0:3] of current cpu. 66 * Shall clobber: x0-x17 67 * -------------------------------------------------------------------- 68 */ 69func errata_a78c_2242638_wa 70 /* Compare x0 against revisions r0p1 - r0p2 */ 71 mov x17, x30 72 bl check_errata_2242638 73 cbz x0, 1f 74 75 ldr x0, =0x5 76 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 77 ldr x0, =0x10F600E000 78 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 79 ldr x0, =0x10FF80E000 80 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 81 ldr x0, =0x80000000003FF 82 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 83 84 isb 851: 86 ret x17 87endfunc errata_a78c_2242638_wa 88 89func check_errata_2242638 90 /* Applies to revisions r0p1-r0p2. */ 91 mov x1, #CPU_REV(0, 1) 92 mov x2, #CPU_REV(0, 2) 93 b cpu_rev_var_range 94endfunc check_errata_2242638 95 96func check_errata_cve_2022_23960 97#if WORKAROUND_CVE_2022_23960 98 mov x0, #ERRATA_APPLIES 99#else 100 mov x0, #ERRATA_MISSING 101#endif 102 ret 103endfunc check_errata_cve_2022_23960 104 105 /* ------------------------------------------------- 106 * The CPU Ops reset function for Cortex-A78C 107 * ------------------------------------------------- 108 */ 109func cortex_a78c_reset_func 110 mov x19, x30 111 bl cpu_get_rev_var 112 mov x18, x0 113 114#if ERRATA_A78C_2132064 115 mov x0, x18 116 bl errata_a78c_2132064_wa 117#endif 118 119#if ERRATA_A78C_2242638 120 mov x0, x18 121 bl errata_a78c_2242638_wa 122#endif 123 124#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 125 /* 126 * The Cortex-A78c generic vectors are overridden to apply errata 127 * mitigation on exception entry from lower ELs. 128 */ 129 adr x0, wa_cve_vbar_cortex_a78c 130 msr vbar_el3, x0 131#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 132 133 isb 134 ret x19 135endfunc cortex_a78c_reset_func 136 137 /* ---------------------------------------------------- 138 * HW will do the cache maintenance while powering down 139 * ---------------------------------------------------- 140 */ 141func cortex_a78c_core_pwr_dwn 142 /* --------------------------------------------------- 143 * Enable CPU power down bit in power control register 144 * --------------------------------------------------- 145 */ 146 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 147 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 148 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 149 isb 150 ret 151endfunc cortex_a78c_core_pwr_dwn 152 153#if REPORT_ERRATA 154/* 155 * Errata printing function for Cortex A78C. Must follow AAPCS. 156 */ 157func cortex_a78c_errata_report 158 stp x8, x30, [sp, #-16]! 159 160 bl cpu_get_rev_var 161 mov x8, x0 162 163 /* 164 * Report all errata. The revision-variant information is passed to 165 * checking functions of each errata. 166 */ 167 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 168 report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 169 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 170 171 ldp x8, x30, [sp], #16 172 ret 173endfunc cortex_a78c_errata_report 174#endif 175 176 /* --------------------------------------------- 177 * This function provides cortex_a78c specific 178 * register information for crash reporting. 179 * It needs to return with x6 pointing to 180 * a list of register names in ascii and 181 * x8 - x15 having values of registers to be 182 * reported. 183 * --------------------------------------------- 184 */ 185.section .rodata.cortex_a78c_regs, "aS" 186cortex_a78c_regs: /* The ascii list of register names to be reported */ 187 .asciz "cpuectlr_el1", "" 188 189func cortex_a78c_cpu_reg_dump 190 adr x6, cortex_a78c_regs 191 mrs x8, CORTEX_A78C_CPUECTLR_EL1 192 ret 193endfunc cortex_a78c_cpu_reg_dump 194 195declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 196 cortex_a78c_reset_func, \ 197 cortex_a78c_core_pwr_dwn 198