| 0a6e2147 | 11-Oct-2021 |
Robert Marko <robert.marko@sartura.hr> |
plat/marvell/a8k: add Globalscale Mochabin support
Add support for Globalscale MOCHAbin board.
Its based on Armada 7040 SoC and ships in multiple DRAM options:
* 2GB DDR4 (1CS)
* 4GB DDR4 (1CS)
* 8
plat/marvell/a8k: add Globalscale Mochabin support
Add support for Globalscale MOCHAbin board.
Its based on Armada 7040 SoC and ships in multiple DRAM options:
* 2GB DDR4 (1CS)
* 4GB DDR4 (1CS)
* 8GB DDR4 (2CS)
Since it ships in multiple DRAM configurations, an
Armada 3k style DDR_TOPOLOGY variable is added.
Currently, this only has effect on the MOCHAbin, but
I expect more boards with multiple DRAM sizes to be
supported.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305
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| cd12b195 | 13-May-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: armv8-R aarch64 fvp_r documentation
Documenting armv8-R aarch64 fvp_r features, boot sequence, and build
procedure.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I
docs: armv8-R aarch64 fvp_r documentation
Documenting armv8-R aarch64 fvp_r features, boot sequence, and build
procedure.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: If75d59acdf0f8a61cea6187967a4c35af2f31c98
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| ab5964aa | 26-Sep-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
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| 52a1e9ff | 15-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(docs/nxp/layerscape): add ls1028a soc and board support
Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc5
feat(docs/nxp/layerscape): add ls1028a soc and board support
Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc586f3718b488a6757994d65f6df69e7e165
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| 46ee50e0 | 24-May-2021 |
Saurabh Gorecha <sgorecha@codeaurora.org> |
feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f216
feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1
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| 38f79045 | 10-Aug-2021 |
Davidson K <davidson.kumaresan@arm.com> |
refactor(tc): use internal trusted storage
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secu
refactor(tc): use internal trusted storage
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.
And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.
commit 33993a3737737a03ee5a9d386d0a027bdc947c9c
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100
feat(fvp): enable external SP images in BL2 config
Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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| 9ecf9438 | 09-Sep-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "docs(stm32mp1): update doc for FIP/FCONF" into integration |
| 07f81627 | 12-Feb-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
docs(stm32mp1): update doc for FIP/FCONF
Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, f
docs(stm32mp1): update doc for FIP/FCONF
Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, for FIP.
The memory mapping is also updated.
Change-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| a138717d | 07-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "advk-serror" into integration
* changes:
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
fix(plat/marvell/a3k): update information about PCIe abort hack |
| e843fb0a | 07-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: nxp soc-lx2160a based platforms" into integration |
| 33993a37 | 26-Mar-2021 |
Balint Dobszay <balint.dobszay@arm.com> |
feat(fvp): enable external SP images in BL2 config
Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Ser
feat(fvp): enable external SP images in BL2 config
Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Services). This commit implements a workaround to enable adding
SP UUIDs to the list at build time.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Iff85d3778596d23d777dec458f131bd7a8647031
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| 7c78e4f7 | 25-Mar-2021 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
docs: nxp soc-lx2160a based platforms
Addition of documents for platforms based on
NXP SoC LX2160A.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I39ac5a9eb0b668d26301a0a24a1e6bf87f
docs: nxp soc-lx2160a based platforms
Addition of documents for platforms based on
NXP SoC LX2160A.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I39ac5a9eb0b668d26301a0a24a1e6bf87f245f02
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|
| cb9ddac9 | 26-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options" into integration |
| d01139f3 | 22-Jun-2021 |
Marcin Wojtas <mw@semihalf.com> |
feat(plat/marvell): introduce t9130_cex7_eval
This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.
Because the DRAM connectivity and SerDes settings
is shared w
feat(plat/marvell): introduce t9130_cex7_eval
This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.
Because the DRAM connectivity and SerDes settings
is shared with the CN913X DB - reuse relevant
board-specific files.
Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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| 3017e932 | 09-Jul-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug found
in U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver
for Armada 37xx SoC) which results in SError interrupt caused by AXI
SLVERR on external access (syndrome 0xbf000002) and immediate kernel
panic.
Now when proper patches are in both U-Boot and Linux kernel projects,
this workaround in TF-A should not have to be enabled by default
anymore as it has unwanted side effects like propagating all external
aborts, including non-fatal/correctable into EL3 and making them as
fatal which cause immediate abort.
Add documentation for HANDLE_EA_EL3_FIRST build option into Marvell
Armada build section.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491
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| 099c90b8 | 20-Aug-2021 |
Pali Rohár <pali@kernel.org> |
docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options
Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.
Signed-off-by: Pali Rohár <pali
docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options
Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I852f60569a9a49269ae296c56cc83eb438528bee
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| d4ad3da0 | 24-Apr-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
refactor(tegra132): deprecate platform
The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support f
refactor(tegra132): deprecate platform
The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support for this legacy platform.
This change removes this platform from the Tegra tree as a result.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a
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| be3a51ce | 13-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/versal): add support for SLS mitigation" into integration |
| 6ec0c65b | 09-Apr-2021 |
Usama Arif <usama.arif@arm.com> |
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: U
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
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|
| 6ea1a75d | 29-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(plat/marvell): move doc platform build options into own subsections" into integration |
| 92024f81 | 20-Jul-2021 |
Pali Rohár <pali@kernel.org> |
refactor(plat/marvell): move doc platform build options into own subsections
Update documentation and group platform specific build options into
their own subsections.
Signed-off-by: Pali Rohár <pa
refactor(plat/marvell): move doc platform build options into own subsections
Update documentation and group platform specific build options into
their own subsections.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I05927d8abf9f811493c49b856f06329220e7d8bb
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| bf3ce993 | 21-Apr-2021 |
Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contain
feat: adding the diphda platform
This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.
Diphda uses a FIP image located in the flash. The FIP contains the
following components:
- BL2
- BL31
- BL32
- BL32 SPMC manifest
- BL33
- The TBB certificates
The board boot relies on CoT (chain of trust). The trusted-firmware-a
BL2 is extracted from the FIP and verified by the Secure Enclave
processor. BL2 verification relies on the signature area at the
beginning of the BL2 image. This area is needed by the SecureEnclave
bootloader.
Then, the application processor is released from reset and starts by
executing BL2.
BL2 performs the actions described in the trusted-firmware-a TBB design
document.
Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
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| 302b4dfb | 21-Jul-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerabili
feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2
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| e18f4aaf | 20-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "marvell-a3k-a8k-updates" into integration
* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG
Merge changes from topic "marvell-a3k-a8k-updates" into integration
* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables
refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB
refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable
fix(plat/marvell/a3k): Fix check for external dependences
fix(plat/marvell/a8k): Add missing build dependency for BLE target
fix(plat/marvell/a8k): Correctly set include directories for individual targets
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
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| 8cf5afaf | 19-Jul-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I2b3aa9bd,I3237199b into integration
* changes:
docs: add mt6795 to deprecated list
feat(plat/mediatek/mt8195): add DCM driver |