1/* 2 * Copyright (c) 2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22/* -------------------------------------------------- 23 * Errata Workaround for Neoverse N2 Erratum 2002655. 24 * This applies to revision r0p0 of Neoverse N2. it is still open. 25 * Inputs: 26 * x0: variant[4:7] and revision[0:3] of current cpu. 27 * Shall clobber: x0-x17 28 * -------------------------------------------------- 29 */ 30func errata_n2_2002655_wa 31 /* Check revision. */ 32 mov x17, x30 33 bl check_errata_2002655 34 cbz x0, 1f 35 36 /* Apply instruction patching sequence */ 37 ldr x0,=0x6 38 msr S3_6_c15_c8_0,x0 39 ldr x0,=0xF3A08002 40 msr S3_6_c15_c8_2,x0 41 ldr x0,=0xFFF0F7FE 42 msr S3_6_c15_c8_3,x0 43 ldr x0,=0x40000001003ff 44 msr S3_6_c15_c8_1,x0 45 ldr x0,=0x7 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xBF200000 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFEF0000 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003f3 52 msr S3_6_c15_c8_1,x0 53 isb 541: 55 ret x17 56endfunc errata_n2_2002655_wa 57 58func check_errata_2002655 59 /* Applies to r0p0 */ 60 mov x1, #0x00 61 b cpu_rev_var_ls 62endfunc check_errata_2002655 63 64 /* ------------------------------------------------- 65 * The CPU Ops reset function for Neoverse N2. 66 * ------------------------------------------------- 67 */ 68func neoverse_n2_reset_func 69 mov x19, x30 70 71 /* Check if the PE implements SSBS */ 72 mrs x0, id_aa64pfr1_el1 73 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 74 b.eq 1f 75 76 /* Disable speculative loads */ 77 msr SSBS, xzr 781: 79 /* Force all cacheable atomic instructions to be near */ 80 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 81 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 82 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 83 84#if ENABLE_AMU 85 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 86 mrs x0, cptr_el3 87 orr x0, x0, #TAM_BIT 88 msr cptr_el3, x0 89 90 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 91 mrs x0, cptr_el2 92 orr x0, x0, #TAM_BIT 93 msr cptr_el2, x0 94 95 /* No need to enable the counters as this would be done at el3 exit */ 96#endif 97 98#if NEOVERSE_Nx_EXTERNAL_LLC 99 /* Some systems may have External LLC, core needs to be made aware */ 100 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 101 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 102 msr NEOVERSE_N2_CPUECTLR_EL1, x0 103#endif 104 105 bl cpu_get_rev_var 106 mov x18, x0 107 108#if ERRATA_N2_2002655 109 mov x0, x18 110 bl errata_n2_2002655_wa 111#endif 112 113 isb 114 ret x19 115endfunc neoverse_n2_reset_func 116 117func neoverse_n2_core_pwr_dwn 118 /* --------------------------------------------- 119 * Enable CPU power down bit in power control register 120 * No need to do cache maintenance here. 121 * --------------------------------------------- 122 */ 123 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 124 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 125 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 126 isb 127 ret 128endfunc neoverse_n2_core_pwr_dwn 129 130#if REPORT_ERRATA 131/* 132 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 133 */ 134func neoverse_n2_errata_report 135 stp x8, x30, [sp, #-16]! 136 137 bl cpu_get_rev_var 138 mov x8, x0 139 140 /* 141 * Report all errata. The revision-variant information is passed to 142 * checking functions of each errata. 143 */ 144 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 145 146 ldp x8, x30, [sp], #16 147 ret 148endfunc neoverse_n2_errata_report 149#endif 150 151 /* --------------------------------------------- 152 * This function provides Neoverse N2 specific 153 * register information for crash reporting. 154 * It needs to return with x6 pointing to 155 * a list of register names in ASCII and 156 * x8 - x15 having values of registers to be 157 * reported. 158 * --------------------------------------------- 159 */ 160.section .rodata.neoverse_n2_regs, "aS" 161neoverse_n2_regs: /* The ASCII list of register names to be reported */ 162 .asciz "cpupwrctlr_el1", "" 163 164func neoverse_n2_cpu_reg_dump 165 adr x6, neoverse_n2_regs 166 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 167 ret 168endfunc neoverse_n2_cpu_reg_dump 169 170declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 171 neoverse_n2_reset_func, \ 172 neoverse_n2_core_pwr_dwn 173