| a6a1dcbe | 08-Nov-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(docs): move deprecated platforms information around
We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:
a) the process for
chore(docs): move deprecated platforms information around
We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:
a) the process for deprecating a platform port;
b) the list of deprecated platforms to this day.
I think it makes more sense to move b) to the platforms ports landing
page, such that it is more visible.
This also has the nice effect to move the 'Deprecated platforms' title
as the last entry of the 'Platform ports' table of contents, like so:
- Platform ports
- 1. Allwinner ARMv8 SoCs
- 2. Arm Development Platforms
...
- 39. Broadcom Stingray
- Deprecated platforms
instead of it being lost in the middle of supported platform ports.
Regarding a), this gets moved under the "Processes & Policies" section.
More specifically, it gets clubbed with the existing platform
compatibility policy. The combined document gets renamed into a
"Platforms Ports Policy" document.
Change-Id: I6e9ce2abc68b8a8ac88e7bd5f21749c14c9a2af6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 2fe661c2 | 08-Nov-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(docs): refresh platform ports landing page
- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2
chore(docs): refresh platform ports landing page
- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2.7).
- Remove mention of Arm Morello platform, as it now has a dedicated
documentation page accessible from the table of contents
(see docs/plat/arm/morello/).
Change-Id: Ie3acdddab81f5589bb36114a8a766200f5b08ad4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 46cc41d5 | 10-Oct-2022 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): restrict RAS support for NS world
Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To
fix(ras): restrict RAS support for NS world
Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To make the current design of RAS explicit, rename this macro
to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when
switching to NS world.
Note: I am unaware of any platform which traps errors originating in
Secure world to EL3, if there is any such platform then it need to
be explicitly implemented in TF-A
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
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| de89b282 | 06-Nov-2022 |
Pali Rohár <pali@kernel.org> |
docs(marvell): fix typo 8K => A8K
It is Armada 80x0, hence A8K (like A7K).
Change-Id: I4888b472204ecd19bfe9b8c89adaa1a99b01dd5f
Signed-off-by: Pali Rohár <pali@kernel.org> |
| 78927ef6 | 02-Nov-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore(docs): update supported FVP models doc" into integration |
| 08a12c11 | 14-Sep-2022 |
laurenw-arm <lauren.wehrmeister@arm.com> |
chore(docs): update supported FVP models doc
Update supported models list according to changes for v2.8 release in
ci/tf-a-ci-scripts repository
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeiste
chore(docs): update supported FVP models doc
Update supported models list according to changes for v2.8 release in
ci/tf-a-ci-scripts repository
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica7e062db77237220bcd861837f392496db1653a
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| 6325f661 | 31-Oct-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "build: deprecate Arm rdn1edge and sgi575 FVP platforms" into integration |
| cf58b2d4 | 25-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore: rename Makalu ELP to Cortex-X3
The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.
Si
chore: rename Makalu ELP to Cortex-X3
The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iebb90cf2f77330ed848a3d61c5f6928942189c5a
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| 4e5d2623 | 21-Oct-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "imx8m-hab-support" into integration
* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and
Merge changes from topic "imx8m-hab-support" into integration
* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and map required memory blocks
feat(imx8mn): add hab and map required memory blocks
feat(imx8mm): add hab and map required memory blocks
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| 07dc8ba9 | 19-Oct-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
build: deprecate Arm rdn1edge and sgi575 FVP platforms
Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discon
build: deprecate Arm rdn1edge and sgi575 FVP platforms
Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discontinued. rdn1edge platform has been superseded by the
rdn2 platform, which is already supported in TF-A and CI work is
underway for this platform.
Change-Id: If2228fb73549b244c3a5b0e5746617b3f24fe771
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 4e7983b7 | 20-Oct-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(ethos-n)!: add support for SMMU streams" into integration |
| de7e9b56 | 26-Sep-2022 |
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> |
docs(imx8m): update for high assurance boot
Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentatio
docs(imx8m): update for high assurance boot
Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentation.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: Iaca97f4ac2595e35de2664a880394519f96eca07
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| b9203307 | 19-Aug-2022 |
Andre Przywara <andre.przywara@arm.com> |
feat(fvp): dts: drop 32-bit .dts files
Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and
feat(fvp): dts: drop 32-bit .dts files
Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and aarch64 does not make sense and is not needed.
Probably due to historic reasons (a Linux bug fixed in 2016 with Linux
commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a
different size between aarch64 and aarch32, even though the size of it
is solely governed by the parent's #address-cells property.
Consolidate this to be always 2, and always use two cells to describe
the CPU's MPIDR register.
This removes the last difference of the -aarch32 versions of the FVP
DT files, so just remove all of them. The respective versions without
that suffix can now be used with AArch32 DT clients as well.
Also remove the respective part in the documentation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e
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| b139f1cf | 15-Aug-2022 |
Mikael Olsson <mikael.olsson@arm.com> |
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
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| 156709dd | 13-Sep-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured i
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured in BL2.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b28ff489479ab04a2fade027933524cdd36e959
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| 4b2f23e5 | 15-Mar-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it ove
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
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| 4efdc488 | 31-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Idcbb893c6b9e46512308c53ba2a0bee48a022b0a
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| 158ed580 | 27-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 04f28f89 | 05-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mt8188" into integration
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move
Merge changes from topic "mt8188" into integration
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move pmic.[c|h] to common folder
refator(mediatek): move common definitions of pmic wrap to common folder
feat(mt8188): add IOMMU enable control in SiP service
feat(mt8188): add display port control in SiP service
fix(mediatek): use uppercase for definition
feat(mediatek): move dp drivers to common folder
feat(mediatek): move mtk_cirq.c drivers to cirq folder
feat(mt8188): initialize GIC
feat(mt8188): initialize systimer
feat(mt8188): initialize platform for MediaTek MT8188
refator(mediatek): remove unused files
refator(mediatek): move drivers folder in common to plat/mediatek
feat(mediatek): support coreboot BL31 loading
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| de310e1e | 07-Jul-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
feat(mt8188): initialize platform for MediaTek MT8188
- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mt
feat(mt8188): initialize platform for MediaTek MT8188
- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mtk_pm.c in lib/pm
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5f8617c42ffba2c9d3a16f3980cb75fda5624031
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| b48cd784 | 09-Aug-2022 |
Pali Rohár <pali@kernel.org> |
docs(marvell): document UART image downloading
For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my
docs(marvell): document UART image downloading
For A3K there are two different tools for booting Armada37x0 platform
over UART, one from Marvell and second from CZ.NIC. For A8K there is
just one my own mvebu64boot tool.
Add documentation how to build these tools and how to download TF-A
image over UART to boot TF-A without flashing it to non-volatile
storage.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa03584010a9c40496a34e6d5b9f3b78cb2cc89b
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| 89e4cea1 | 24-Jun-2022 |
Arthur She <arthur.she@linaro.org> |
docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9
docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9eda619906cdb5d
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| eebd2c3f | 04-Apr-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e4
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd
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| 173c3afc | 28-Apr-2022 |
Maksims Svecovs <maksims.svecovs@arm.com> |
docs: update supported FVP models documentation
Update supported models list according to changes for v2.7 release in
ci/tf-a-ci-scripts repository:
* general FVP model update: 5c54251
* CSS model u
docs: update supported FVP models documentation
Update supported models list according to changes for v2.7 release in
ci/tf-a-ci-scripts repository:
* general FVP model update: 5c54251
* CSS model update: 3bd12fb
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: I38c2ef2991b23873821c7e34ad2900b9ad023c4b
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| 103bbd56 | 11-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
docs(versal): fix the versal platform emu name
Fix the versal platform emu itr6 name.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Id9f3272c85513d8258fbbb3bd71
docs(versal): fix the versal platform emu name
Fix the versal platform emu itr6 name.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Id9f3272c85513d8258fbbb3bd719c032053b3ada
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