1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* ---------------------------------------------------- 30 * HW will do the cache maintenance while powering down 31 * ---------------------------------------------------- 32 */ 33func cortex_x3_core_pwr_dwn 34 /* --------------------------------------------------- 35 * Enable CPU power down bit in power control register 36 * --------------------------------------------------- 37 */ 38 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 39 orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 40 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 41 isb 42 ret 43endfunc cortex_x3_core_pwr_dwn 44 45func check_errata_cve_2022_23960 46#if WORKAROUND_CVE_2022_23960 47 mov x0, #ERRATA_APPLIES 48#else 49 mov x0, #ERRATA_MISSING 50#endif 51 ret 52endfunc check_errata_cve_2022_23960 53 54func cortex_x3_reset_func 55 /* Disable speculative loads */ 56 msr SSBS, xzr 57 58#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 59 /* 60 * The Cortex-X3 generic vectors are overridden to apply 61 * errata mitigation on exception entry from lower ELs. 62 */ 63 adr x0, wa_cve_vbar_cortex_x3 64 msr vbar_el3, x0 65#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 66 67 isb 68 ret 69endfunc cortex_x3_reset_func 70 71#if REPORT_ERRATA 72 /* 73 * Errata printing function for Cortex-X3. Must follow AAPCS. 74 */ 75func cortex_x3_errata_report 76 stp x8, x30, [sp, #-16]! 77 78 bl cpu_get_rev_var 79 mov x8, x0 80 81 /* 82 * Report all errata. The revision-variant information is passed to 83 * checking functions of each errata. 84 */ 85 report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960 86 87 ldp x8, x30, [sp], #16 88 ret 89endfunc cortex_x3_errata_report 90#endif 91 92 /* --------------------------------------------- 93 * This function provides Cortex-X3- 94 * specific register information for crash 95 * reporting. It needs to return with x6 96 * pointing to a list of register names in ascii 97 * and x8 - x15 having values of registers to be 98 * reported. 99 * --------------------------------------------- 100 */ 101.section .rodata.cortex_x3_regs, "aS" 102cortex_x3_regs: /* The ascii list of register names to be reported */ 103 .asciz "cpuectlr_el1", "" 104 105func cortex_x3_cpu_reg_dump 106 adr x6, cortex_x3_regs 107 mrs x8, CORTEX_X3_CPUECTLR_EL1 108 ret 109endfunc cortex_x3_cpu_reg_dump 110 111declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 112 cortex_x3_reset_func, \ 113 cortex_x3_core_pwr_dwn 114