1/* 2 * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* -------------------------------------------------- 28 * Errata Workaround for Neoverse N2 Erratum 2002655. 29 * This applies to revision r0p0 of Neoverse N2. it is still open. 30 * Inputs: 31 * x0: variant[4:7] and revision[0:3] of current cpu. 32 * Shall clobber: x0-x17 33 * -------------------------------------------------- 34 */ 35func errata_n2_2002655_wa 36 /* Check revision. */ 37 mov x17, x30 38 bl check_errata_2002655 39 cbz x0, 1f 40 41 /* Apply instruction patching sequence */ 42 ldr x0,=0x6 43 msr S3_6_c15_c8_0,x0 44 ldr x0,=0xF3A08002 45 msr S3_6_c15_c8_2,x0 46 ldr x0,=0xFFF0F7FE 47 msr S3_6_c15_c8_3,x0 48 ldr x0,=0x40000001003ff 49 msr S3_6_c15_c8_1,x0 50 ldr x0,=0x7 51 msr S3_6_c15_c8_0,x0 52 ldr x0,=0xBF200000 53 msr S3_6_c15_c8_2,x0 54 ldr x0,=0xFFEF0000 55 msr S3_6_c15_c8_3,x0 56 ldr x0,=0x40000001003f3 57 msr S3_6_c15_c8_1,x0 58 isb 591: 60 ret x17 61endfunc errata_n2_2002655_wa 62 63func check_errata_2002655 64 /* Applies to r0p0 */ 65 mov x1, #0x00 66 b cpu_rev_var_ls 67endfunc check_errata_2002655 68 69/* --------------------------------------------------------------- 70 * Errata Workaround for Neoverse N2 Erratum 2067956. 71 * This applies to revision r0p0 of Neoverse N2 and is still open. 72 * Inputs: 73 * x0: variant[4:7] and revision[0:3] of current cpu. 74 * Shall clobber: x0-x17 75 * --------------------------------------------------------------- 76 */ 77func errata_n2_2067956_wa 78 /* Compare x0 against revision r0p0 */ 79 mov x17, x30 80 bl check_errata_2067956 81 cbz x0, 1f 82 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 83 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 84 msr NEOVERSE_N2_CPUACTLR_EL1, x1 851: 86 ret x17 87endfunc errata_n2_2067956_wa 88 89func check_errata_2067956 90 /* Applies to r0p0 */ 91 mov x1, #0x00 92 b cpu_rev_var_ls 93endfunc check_errata_2067956 94 95/* --------------------------------------------------------------- 96 * Errata Workaround for Neoverse N2 Erratum 2025414. 97 * This applies to revision r0p0 of Neoverse N2 and is still open. 98 * Inputs: 99 * x0: variant[4:7] and revision[0:3] of current cpu. 100 * Shall clobber: x0-x17 101 * --------------------------------------------------------------- 102 */ 103func errata_n2_2025414_wa 104 /* Compare x0 against revision r0p0 */ 105 mov x17, x30 106 bl check_errata_2025414 107 cbz x0, 1f 108 mrs x1, NEOVERSE_N2_CPUECTLR_EL1 109 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 110 msr NEOVERSE_N2_CPUECTLR_EL1, x1 111 1121: 113 ret x17 114endfunc errata_n2_2025414_wa 115 116func check_errata_2025414 117 /* Applies to r0p0 */ 118 mov x1, #0x00 119 b cpu_rev_var_ls 120endfunc check_errata_2025414 121 122/* --------------------------------------------------------------- 123 * Errata Workaround for Neoverse N2 Erratum 2189731. 124 * This applies to revision r0p0 of Neoverse N2 and is still open. 125 * Inputs: 126 * x0: variant[4:7] and revision[0:3] of current cpu. 127 * Shall clobber: x0-x17 128 * --------------------------------------------------------------- 129 */ 130func errata_n2_2189731_wa 131 /* Compare x0 against revision r0p0 */ 132 mov x17, x30 133 bl check_errata_2189731 134 cbz x0, 1f 135 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 136 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 137 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 138 1391: 140 ret x17 141endfunc errata_n2_2189731_wa 142 143func check_errata_2189731 144 /* Applies to r0p0 */ 145 mov x1, #0x00 146 b cpu_rev_var_ls 147endfunc check_errata_2189731 148 149/* -------------------------------------------------- 150 * Errata Workaround for Neoverse N2 Erratum 2138956. 151 * This applies to revision r0p0 of Neoverse N2. it is still open. 152 * Inputs: 153 * x0: variant[4:7] and revision[0:3] of current cpu. 154 * Shall clobber: x0-x17 155 * -------------------------------------------------- 156 */ 157func errata_n2_2138956_wa 158 /* Check revision. */ 159 mov x17, x30 160 bl check_errata_2138956 161 cbz x0, 1f 162 163 /* Apply instruction patching sequence */ 164 ldr x0,=0x3 165 msr S3_6_c15_c8_0,x0 166 ldr x0,=0xF3A08002 167 msr S3_6_c15_c8_2,x0 168 ldr x0,=0xFFF0F7FE 169 msr S3_6_c15_c8_3,x0 170 ldr x0,=0x10002001003FF 171 msr S3_6_c15_c8_1,x0 172 ldr x0,=0x4 173 msr S3_6_c15_c8_0,x0 174 ldr x0,=0xBF200000 175 msr S3_6_c15_c8_2,x0 176 ldr x0,=0xFFEF0000 177 msr S3_6_c15_c8_3,x0 178 ldr x0,=0x10002001003F3 179 msr S3_6_c15_c8_1,x0 180 isb 1811: 182 ret x17 183endfunc errata_n2_2138956_wa 184 185func check_errata_2138956 186 /* Applies to r0p0 */ 187 mov x1, #0x00 188 b cpu_rev_var_ls 189endfunc check_errata_2138956 190 191/* -------------------------------------------------- 192 * Errata Workaround for Neoverse N2 Erratum 2242415. 193 * This applies to revision r0p0 of Neoverse N2. it is still open. 194 * Inputs: 195 * x0: variant[4:7] and revision[0:3] of current cpu. 196 * Shall clobber: x0-x1, x17 197 * -------------------------------------------------- 198 */ 199func errata_n2_2242415_wa 200 /* Check revision. */ 201 mov x17, x30 202 bl check_errata_2242415 203 cbz x0, 1f 204 205 /* Apply instruction patching sequence */ 206 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 207 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 208 msr NEOVERSE_N2_CPUACTLR_EL1, x1 2091: 210 ret x17 211endfunc errata_n2_2242415_wa 212 213func check_errata_2242415 214 /* Applies to r0p0 */ 215 mov x1, #0x00 216 b cpu_rev_var_ls 217endfunc check_errata_2242415 218 219/* -------------------------------------------------- 220 * Errata Workaround for Neoverse N2 Erratum 2138953. 221 * This applies to revision r0p0 of Neoverse N2. it is still open. 222 * Inputs: 223 * x0: variant[4:7] and revision[0:3] of current cpu. 224 * Shall clobber: x0-x1, x17 225 * -------------------------------------------------- 226 */ 227func errata_n2_2138953_wa 228 /* Check revision. */ 229 mov x17, x30 230 bl check_errata_2138953 231 cbz x0, 1f 232 233 /* Apply instruction patching sequence */ 234 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 235 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 236 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 237 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 2381: 239 ret x17 240endfunc errata_n2_2138953_wa 241 242func check_errata_2138953 243 /* Applies to r0p0 */ 244 mov x1, #0x00 245 b cpu_rev_var_ls 246endfunc check_errata_2138953 247 248/* -------------------------------------------------- 249 * Errata Workaround for Neoverse N2 Erratum 2138958. 250 * This applies to revision r0p0 of Neoverse N2. it is still open. 251 * Inputs: 252 * x0: variant[4:7] and revision[0:3] of current cpu. 253 * Shall clobber: x0-x1, x17 254 * -------------------------------------------------- 255 */ 256func errata_n2_2138958_wa 257 /* Check revision. */ 258 mov x17, x30 259 bl check_errata_2138958 260 cbz x0, 1f 261 262 /* Apply instruction patching sequence */ 263 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 264 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 265 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 2661: 267 ret x17 268endfunc errata_n2_2138958_wa 269 270func check_errata_2138958 271 /* Applies to r0p0 */ 272 mov x1, #0x00 273 b cpu_rev_var_ls 274endfunc check_errata_2138958 275 276/* -------------------------------------------------- 277 * Errata Workaround for Neoverse N2 Erratum 2242400. 278 * This applies to revision r0p0 of Neoverse N2. it is still open. 279 * Inputs: 280 * x0: variant[4:7] and revision[0:3] of current cpu. 281 * Shall clobber: x0-x1, x17 282 * -------------------------------------------------- 283 */ 284func errata_n2_2242400_wa 285 /* Check revision. */ 286 mov x17, x30 287 bl check_errata_2242400 288 cbz x0, 1f 289 290 /* Apply instruction patching sequence */ 291 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 292 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 293 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 294 ldr x0, =0x2 295 msr S3_6_c15_c8_0, x0 296 ldr x0, =0x10F600E000 297 msr S3_6_c15_c8_2, x0 298 ldr x0, =0x10FF80E000 299 msr S3_6_c15_c8_3, x0 300 ldr x0, =0x80000000003FF 301 msr S3_6_c15_c8_1, x0 302 isb 3031: 304 ret x17 305endfunc errata_n2_2242400_wa 306 307func check_errata_2242400 308 /* Applies to r0p0 */ 309 mov x1, #0x00 310 b cpu_rev_var_ls 311endfunc check_errata_2242400 312 313/* -------------------------------------------------- 314 * Errata Workaround for Neoverse N2 Erratum 2280757. 315 * This applies to revision r0p0 of Neoverse N2. it is still open. 316 * Inputs: 317 * x0: variant[4:7] and revision[0:3] of current cpu. 318 * Shall clobber: x0-x1, x17 319 * -------------------------------------------------- 320 */ 321func errata_n2_2280757_wa 322 /* Check revision. */ 323 mov x17, x30 324 bl check_errata_2280757 325 cbz x0, 1f 326 327 /* Apply instruction patching sequence */ 328 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 329 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 330 msr NEOVERSE_N2_CPUACTLR_EL1, x1 3311: 332 ret x17 333endfunc errata_n2_2280757_wa 334 335func check_errata_2280757 336 /* Applies to r0p0 */ 337 mov x1, #0x00 338 b cpu_rev_var_ls 339endfunc check_errata_2280757 340 341/* -------------------------------------------------- 342 * Errata Workaround for Neoverse N2 Erratum 2388450. 343 * This applies to revision r0p0 of Neoverse N2, 344 * fixed in r0p1. 345 * Inputs: 346 * x0: variant[4:7] and revision[0:3] of current cpu. 347 * Shall clobber: x0-x1, x17 348 * -------------------------------------------------- 349 */ 350func errata_n2_2388450_wa 351 /* Check revision. */ 352 mov x17, x30 353 bl check_errata_2388450 354 cbz x0, 1f 355 356 /*Set bit 40 in ACTLR2_EL1 */ 357 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 358 orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 359 msr NEOVERSE_N2_CPUACTLR2_EL1, x1 360 isb 3611: 362 ret x17 363endfunc errata_n2_2388450_wa 364 365func check_errata_2388450 366 /* Applies to r0p0, fixed in r0p1 */ 367 mov x1, #0x00 368 b cpu_rev_var_ls 369endfunc check_errata_2388450 370 371func check_errata_cve_2022_23960 372#if WORKAROUND_CVE_2022_23960 373 mov x0, #ERRATA_APPLIES 374#else 375 mov x0, #ERRATA_MISSING 376#endif 377 ret 378endfunc check_errata_cve_2022_23960 379 380 /* ------------------------------------------- 381 * The CPU Ops reset function for Neoverse N2. 382 * ------------------------------------------- 383 */ 384func neoverse_n2_reset_func 385 mov x19, x30 386 387 /* Check if the PE implements SSBS */ 388 mrs x0, id_aa64pfr1_el1 389 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 390 b.eq 1f 391 392 /* Disable speculative loads */ 393 msr SSBS, xzr 3941: 395 /* Force all cacheable atomic instructions to be near */ 396 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 397 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 398 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 399 400#if ERRATA_DSU_2313941 401 bl errata_dsu_2313941_wa 402#endif 403 404#if ERRATA_N2_2067956 405 mov x0, x18 406 bl errata_n2_2067956_wa 407#endif 408 409#if ERRATA_N2_2025414 410 mov x0, x18 411 bl errata_n2_2025414_wa 412#endif 413 414#if ERRATA_N2_2189731 415 mov x0, x18 416 bl errata_n2_2189731_wa 417#endif 418 419 420#if ERRATA_N2_2138956 421 mov x0, x18 422 bl errata_n2_2138956_wa 423#endif 424 425#if ERRATA_N2_2138953 426 mov x0, x18 427 bl errata_n2_2138953_wa 428#endif 429 430#if ERRATA_N2_2242415 431 mov x0, x18 432 bl errata_n2_2242415_wa 433#endif 434 435#if ERRATA_N2_2138958 436 mov x0, x18 437 bl errata_n2_2138958_wa 438#endif 439 440#if ERRATA_N2_2242400 441 mov x0, x18 442 bl errata_n2_2242400_wa 443#endif 444 445#if ERRATA_N2_2280757 446 mov x0, x18 447 bl errata_n2_2280757_wa 448#endif 449 450#if ERRATA_N2_2388450 451 mov x0, x18 452 bl errata_n2_2388450_wa 453#endif 454 455#if ENABLE_AMU 456 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 457 mrs x0, cptr_el3 458 orr x0, x0, #TAM_BIT 459 msr cptr_el3, x0 460 461 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 462 mrs x0, cptr_el2 463 orr x0, x0, #TAM_BIT 464 msr cptr_el2, x0 465 466 /* No need to enable the counters as this would be done at el3 exit */ 467#endif 468 469#if NEOVERSE_Nx_EXTERNAL_LLC 470 /* Some systems may have External LLC, core needs to be made aware */ 471 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 472 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 473 msr NEOVERSE_N2_CPUECTLR_EL1, x0 474#endif 475 476 bl cpu_get_rev_var 477 mov x18, x0 478 479#if ERRATA_N2_2002655 480 mov x0, x18 481 bl errata_n2_2002655_wa 482#endif 483 484#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 485 /* 486 * The Neoverse-N2 generic vectors are overridden to apply errata 487 * mitigation on exception entry from lower ELs. 488 */ 489 adr x0, wa_cve_vbar_neoverse_n2 490 msr vbar_el3, x0 491#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 492 493 isb 494 ret x19 495endfunc neoverse_n2_reset_func 496 497func neoverse_n2_core_pwr_dwn 498 /* --------------------------------------------------- 499 * Enable CPU power down bit in power control register 500 * No need to do cache maintenance here. 501 * --------------------------------------------------- 502 */ 503 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 504 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 505 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 506 isb 507 ret 508endfunc neoverse_n2_core_pwr_dwn 509 510#if REPORT_ERRATA 511/* 512 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 513 */ 514func neoverse_n2_errata_report 515 stp x8, x30, [sp, #-16]! 516 517 bl cpu_get_rev_var 518 mov x8, x0 519 520 /* 521 * Report all errata. The revision-variant information is passed to 522 * checking functions of each errata. 523 */ 524 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 525 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 526 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 527 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 528 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 529 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 530 report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 531 report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 532 report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 533 report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 534 report_errata ERRATA_N2_2388450, neoverse_n2, 2388450 535 report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960 536 report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941 537 538 ldp x8, x30, [sp], #16 539 ret 540endfunc neoverse_n2_errata_report 541#endif 542 543 /* --------------------------------------------- 544 * This function provides Neoverse N2 specific 545 * register information for crash reporting. 546 * It needs to return with x6 pointing to 547 * a list of register names in ASCII and 548 * x8 - x15 having values of registers to be 549 * reported. 550 * --------------------------------------------- 551 */ 552.section .rodata.neoverse_n2_regs, "aS" 553neoverse_n2_regs: /* The ASCII list of register names to be reported */ 554 .asciz "cpupwrctlr_el1", "" 555 556func neoverse_n2_cpu_reg_dump 557 adr x6, neoverse_n2_regs 558 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 559 ret 560endfunc neoverse_n2_cpu_reg_dump 561 562declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 563 neoverse_n2_reset_func, \ 564 neoverse_n2_core_pwr_dwn 565