feat(nuvoton): added support for npcm845x chip

Initial version

Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: If433d325a90b519ae5f02411865bffd368ff2824

docs(msm8916): document new platforms

Document the new platform build options for the MSM8916 port which now
supports multiple similar Qualcomm SoCs:

- Snapdragon 410 (PLAT=msm8916) as before
-

docs(msm8916): document new platforms

Document the new platform build options for the MSM8916 port which now
supports multiple similar Qualcomm SoCs:

- Snapdragon 410 (PLAT=msm8916) as before
- Snapdragon 615 (PLAT=msm8939)
- Snapdragon 210 (PLAT=msm8909)
- Snapdragon X5 Modem (PLAT=mdm9607)

The latter two use AArch32-only ARM Cortex-A7 cores that only support
using BL32/SP_MIN and not BL31 on AArch64.

Change-Id: I9fffe60dd0ad2acc18f006f11e91854b9e8dcb8f
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge "docs: move common build option from Arm-specific to common file" into integration

docs(morello): update the boot sequence according to the TBBR boot flow

The boot sequence mentioned in the documentation referred to an older
boot flow. This patch updates the boot sequence to the T

docs(morello): update the boot sequence according to the TBBR boot flow

The boot sequence mentioned in the documentation referred to an older
boot flow. This patch updates the boot sequence to the TBBR boot flow
that is currently being followed.

Signed-off-by: Deepthi Peter <deepthi.peter@arm.com>
Change-Id: I183458cea6d43dcf8acba2e0422920ab5541fdfc

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docs(imx9): add imx93 platform

Add i.MX9 platform introduction.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic07ca394cff6a9e3e21b7a03f9c9080d3c1ef91a

chore: rename hayes to a520

Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename hunter to a720

Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration

docs: move common build option from Arm-specific to common file

Moved common build options from Arm-specific file to common build
file.

Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-o

docs: move common build option from Arm-specific to common file

Moved common build options from Arm-specific file to common build
file.

Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs: move the Juno-specific build option to Arm build option file" into integration

Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration

docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Si

docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc

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docs: move the Juno-specific build option to Arm build option file

Moved the Juno-specific build option from the common build option
file to the Arm build option file.

Change-Id: I0f53203f0cfca4a3b

docs: move the Juno-specific build option to Arm build option file

Moved the Juno-specific build option from the common build option
file to the Arm build option file.

Change-Id: I0f53203f0cfca4a3baadab2cee4339c9694cfe8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you t

feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.

This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:

FVP_TRUSTED_SRAM_SIZE=384

This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.

Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(msm8916): document new build options

Update the MSM8916 platform documentation with the new build options
introduced in the previous changes:

- AArch32 (BL32/SP_MIN)
- UART selection

Whil

docs(msm8916): document new build options

Update the MSM8916 platform documentation with the new build options
introduced in the previous changes:

- AArch32 (BL32/SP_MIN)
- UART selection

While at it, also document the build options that allow changing the
memory addresses (PRELOADED_BL33_BASE, BL31_BASE, BL32_BASE).

Change-Id: I2370c8264982317693f69fda0b03a255f12bafe2
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge "docs: update PSCI reference" into integration

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017a

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc

feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

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Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinne

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinner): add extra CPU control registers
refactor(allwinner): consolidate sunxi_cfg.h files

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Merge "build: deprecate Arm rde1edge" into integration

feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision

feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision out there, which uses a different CPU cluster control block.
The same die revision has been spotted in some, but not all, H313 SoCs.

Apart from that IP block, the rest of the SoC seems the same, so we can
support them using the existing H616 port. The die revision can be
auto-detected, so there is no extra build option or knowledge needed.

Provide the deviating CPU power up/down sequence for the die variant.
The new IP block uses per-core instead of per-cluster registers, but
follows the same pattern otherwise.

Since the CPU ops code is shared among all Allwinner SoCs, we need to
dummy-define the new register names for the older SoCs. The actual new
code is guarded by a predicate function, that is hard coded to return
true on the other SoCs. Since this is a static inline function in a
header file, the compiler will optimise away the unneeded branch there,
so the generated code for the other SoCs stays the same.

Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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docs(juno): refer to SCP v2.12.0

Change-Id: I2844fb569abcc403525982162484dc0aa7e5a9d6
Signed-off-by: Chris Kay <chris.kay@arm.com>

docs(juno): update SCP downloads link

Change-Id: Ibe2a1d2ec019333876a4f82b70fde0a10d667f7c
Signed-off-by: Chris Kay <chris.kay@arm.com>

build: deprecate Arm rde1edge

Arm has decided to deprecate the rde1edge platform. The development
of software and fast model for this platform have been discontinued.
Hence, updated the makefile to

build: deprecate Arm rde1edge

Arm has decided to deprecate the rde1edge platform. The development
of software and fast model for this platform have been discontinued.
Hence, updated the makefile to warn about the deprecation of this
platform, and also reflected it in the documentation.

Change-Id: I0d44de4590dd5dce02c7c4b433df25dc438e6c49
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(zynqmp): make stack size configurable

If PLATFORM_STACK_SIZE not already defined, use the default value of
PLATFORM_STACK_SIZE.
This makes the stack size value configurable for different interf

feat(zynqmp): make stack size configurable

If PLATFORM_STACK_SIZE not already defined, use the default value of
PLATFORM_STACK_SIZE.
This makes the stack size value configurable for different interface
like custom packages.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I87e9fcbfb4c4092378b1ac0ff8fb6d084495d320

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