1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 84 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 85 this file name will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 98 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 99 this file name will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 105 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 106 this file name will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 184 registers in cpu context. This must be enabled, if the platform wants to use 185 this feature in the Secure world and MTE is enabled at ELX. This flag can 186 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 187 Default value is 0. 188 189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 190 registers to be saved/restored when entering/exiting an EL2 execution 191 context. This flag can take values 0 to 2, to align with the 192 ``FEATURE_DETECTION`` mechanism. Default value is 0. 193 194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 196 to be included when saving and restoring the CPU context as part of world 197 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 198 mechanism. Default value is 0. 199 200 Note that Pointer Authentication is enabled for Non-secure world irrespective 201 of the value of this flag if the CPU supports it. 202 203- ``DEBUG``: Chooses between a debug and release build. It can take either 0 204 (release) or 1 (debug) as values. 0 is the default. 205 206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 207 authenticated decryption algorithm to be used to decrypt firmware/s during 208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 209 this flag is ``none`` to disable firmware decryption which is an optional 210 feature as per TBBR. 211 212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 213 of the binary image. If set to 1, then only the ELF image is built. 214 0 is the default. 215 216- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 217 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 218 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 219 check the latest Arm ARM. 220 221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 222 Board Boot authentication at runtime. This option is meant to be enabled only 223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 224 flag has to be enabled. 0 is the default. 225 226- ``E``: Boolean option to make warnings into errors. Default is 1. 227 228 When specifying higher warnings levels (``W=1`` and higher), this option 229 defaults to 0. This is done to encourage contributors to use them, as they 230 are expected to produce warnings that would otherwise fail the build. New 231 contributions are still expected to build with ``W=0`` and ``E=1`` (the 232 default). 233 234- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 235 the normal boot flow. It must specify the entry point address of the EL3 236 payload. Please refer to the "Booting an EL3 payload" section for more 237 details. 238 239- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 240 (also known as group 1 counters). These are implementation-defined counters, 241 and as such require additional platform configuration. Default is 0. 242 243- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 244 allows platforms with auxiliary counters to describe them via the 245 ``HW_CONFIG`` device tree blob. Default is 0. 246 247- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 248 are compiled out. For debug builds, this option defaults to 1, and calls to 249 ``assert()`` are left in place. For release builds, this option defaults to 0 250 and calls to ``assert()`` function are compiled out. This option can be set 251 independently of ``DEBUG``. It can also be used to hide any auxiliary code 252 that is only required for the assertion and does not fit in the assertion 253 itself. 254 255- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 256 dumps or not. It is supported in both AArch64 and AArch32. However, in 257 AArch32 the format of the frame records are not defined in the AAPCS and they 258 are defined by the implementation. This implementation of backtrace only 259 supports the format used by GCC when T32 interworking is disabled. For this 260 reason enabling this option in AArch32 will force the compiler to only 261 generate A32 code. This option is enabled by default only in AArch64 debug 262 builds, but this behaviour can be overridden in each platform's Makefile or 263 in the build command line. 264 265- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 266 extensions. This flag can take the values 0 to 2, to align with the 267 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 268 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 269 and this option can be used to enable this feature on those systems as well. 270 This flag can take the values 0 to 2, the default is 0. 271 272- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 273 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 274 onwards. This flag can take the values 0 to 2, to align with the 275 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 276 277- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 278 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 279 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 280 optional feature available on Arm v8.0 onwards. This flag can take values 281 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 282 Default value is ``0``. 283 284- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 285 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 286 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 287 and upwards. This flag can take the values 0 to 2, to align with the 288 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 289 290- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 291 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 292 Physical Offset register) during EL2 to EL3 context save/restore operations. 293 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 294 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 295 mechanism. Default value is ``0``. 296 297- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 298 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 299 Read Trap Register) during EL2 to EL3 context save/restore operations. 300 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 301 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 302 mechanism. Default value is ``0``. 303 304- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 305 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 306 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 307 mandatory architectural feature and is enabled from v8.7 and upwards. This 308 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 309 mechanism. Default value is ``0``. 310 311- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 312 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 313 permission fault for any privileged data access from EL1/EL2 to virtual 314 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 315 mandatory architectural feature and is enabled from v8.1 and upwards. This 316 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 317 mechanism. Default value is ``0``. 318 319- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 320 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 321 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 322 mechanism. Default value is ``0``. 323 324- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 325 extension. This feature is only supported in AArch64 state. This flag can 326 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 327 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 328 Armv8.5 onwards. 329 330- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 331 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 332 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 333 later CPUs. It is enabled from v8.5 and upwards and if needed can be 334 overidden from platforms explicitly. 335 336- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 337 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 338 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 339 mechanism. Default is ``0``. 340 341- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 342 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 343 available on Arm v8.6. This flag can take values 0 to 2, to align with the 344 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 345 346 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 347 delayed by the amount of value in ``TWED_DELAY``. 348 349- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 350 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 351 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 352 architectural feature and is enabled from v8.1 and upwards. It can take 353 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 354 Default value is ``0``. 355 356- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 357 allow access to TCR2_EL2 (extended translation control) from EL2 as 358 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 359 mandatory architectural feature and is enabled from v8.9 and upwards. This 360 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 361 mechanism. Default value is ``0``. 362 363- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 364 at EL2 and below, and context switch relevant registers. This flag 365 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 366 mechanism. Default value is ``0``. 367 368- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 369 at EL2 and below, and context switch relevant registers. This flag 370 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 371 mechanism. Default value is ``0``. 372 373- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 374 at EL2 and below, and context switch relevant registers. This flag 375 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 376 mechanism. Default value is ``0``. 377 378- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 379 at EL2 and below, and context switch relevant registers. This flag 380 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 381 mechanism. Default value is ``0``. 382 383- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 384 allow use of Guarded Control Stack from EL2 as well as adding the GCS 385 registers to the EL2 context save/restore operations. This flag can take 386 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 387 Default value is ``0``. 388 389- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 390 support in GCC for TF-A. This option is currently only supported for 391 AArch64. Default is 0. 392 393- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 394 feature. MPAM is an optional Armv8.4 extension that enables various memory 395 system components and resources to define partitions; software running at 396 various ELs can assign themselves to desired partition to control their 397 performance aspects. 398 399 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 400 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 401 access their own MPAM registers without trapping into EL3. This option 402 doesn't make use of partitioning in EL3, however. Platform initialisation 403 code should configure and use partitions in EL3 as required. This option 404 defaults to ``0``. 405 406- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 407 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 408 firmware to detect and limit high activity events to assist in SoC processor 409 power domain dynamic power budgeting and limit the triggering of whole-rail 410 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 411 412- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 413 allows platforms with cores supporting MPMM to describe them via the 414 ``HW_CONFIG`` device tree blob. Default is 0. 415 416- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 417 support within generic code in TF-A. This option is currently only supported 418 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 419 in BL32 (SP_min) for AARCH32. Default is 0. 420 421- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 422 Measurement Framework(PMF). Default is 0. 423 424- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 425 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 426 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 427 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 428 software. 429 430- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 431 Management Extension. This flag can take the values 0 to 2, to align with 432 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 433 an experimental feature. 434 435- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 436 instrumentation which injects timestamp collection points into TF-A to 437 allow runtime performance to be measured. Currently, only PSCI is 438 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 439 as well. Default is 0. 440 441- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 442 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 443 registers so are enabled together. Using this option without 444 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 445 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 446 superset of SVE. SME is an optional architectural feature for AArch64 447 and TF-A support is experimental. At this time, this build option cannot be 448 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 449 build with these options will fail. This flag can take the values 0 to 2, to 450 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 451 452- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 453 version 2 (SME2) for the non-secure world only. SME2 is an optional 454 architectural feature for AArch64 and TF-A support is experimental. 455 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 456 accesses will still be trapped. This flag can take the values 0 to 2, to 457 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 458 459- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 460 Extension for secure world. Used along with SVE and FPU/SIMD. 461 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 462 This is experimental. Default is 0. 463 464- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 465 extensions. This is an optional architectural feature for AArch64. 466 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 467 mechanism. The default is 2 but is automatically disabled when the target 468 architecture is AArch32. 469 470- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 471 (SVE) for the Non-secure world only. SVE is an optional architectural feature 472 for AArch64. Note that when SVE is enabled for the Non-secure world, access 473 to SIMD and floating-point functionality from the Secure world is disabled by 474 default and controlled with ENABLE_SVE_FOR_SWD. 475 This is to avoid corruption of the Non-secure world data in the Z-registers 476 which are aliased by the SIMD and FP registers. The build option is not 477 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 478 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 479 enabled. This flag can take the values 0 to 2, to align with the 480 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be 481 used on systems that have SPM_MM enabled. The default is 1. 482 483- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 484 SVE is an optional architectural feature for AArch64. Note that this option 485 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 486 automatically disabled when the target architecture is AArch32. 487 488- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 489 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 490 default value is set to "none". "strong" is the recommended stack protection 491 level if this feature is desired. "none" disables the stack protection. For 492 all values other than "none", the ``plat_get_stack_protector_canary()`` 493 platform hook needs to be implemented. The value is passed as the last 494 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 495 496- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 497 flag depends on ``DECRYPTION_SUPPORT`` build flag. 498 499- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 500 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 501 502- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 503 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 504 on ``DECRYPTION_SUPPORT`` build flag. 505 506- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 507 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 508 build flag. 509 510- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 511 deprecated platform APIs, helper functions or drivers within Trusted 512 Firmware as error. It can take the value 1 (flag the use of deprecated 513 APIs as error) or 0. The default is 0. 514 515- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 516 targeted at EL3. When set ``0`` (default), no exceptions are expected or 517 handled at EL3, and a panic will result. The exception to this rule is when 518 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 519 occuring during normal world execution, are trapped to EL3. Any exception 520 trapped during secure world execution are trapped to the SPMC. This is 521 supported only for AArch64 builds. 522 523- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 524 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 525 Default value is 40 (LOG_LEVEL_INFO). 526 527- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 528 injection from lower ELs, and this build option enables lower ELs to use 529 Error Records accessed via System Registers to inject faults. This is 530 applicable only to AArch64 builds. 531 532 This feature is intended for testing purposes only, and is advisable to keep 533 disabled for production images. 534 535- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 536 detection mechanism. It detects whether the Architectural features enabled 537 through feature specific build flags are supported by the PE or not by 538 validating them either at boot phase or at runtime based on the value 539 possessed by the feature flag (0 to 2) and report error messages at an early 540 stage. This flag will also enable errata ordering checking for ``DEBUG`` 541 builds. 542 543 This prevents and benefits us from EL3 runtime exceptions during context save 544 and restore routines guarded by these build flags. Henceforth validating them 545 before their usage provides more control on the actions taken under them. 546 547 The mechanism permits the build flags to take values 0, 1 or 2 and 548 evaluates them accordingly. 549 550 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 551 552 :: 553 554 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 555 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 556 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 557 558 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 559 0, feature is disabled statically during compilation. If it is defined as 1, 560 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 561 implemented by the PE, a hard panic is generated. Finally, if the flag is set 562 to 2, feature is validated at runtime. 563 564 Note that the entire implementation is divided into two phases, wherein as 565 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 566 supported and is planned to be handled explicilty in phase-2 implementation. 567 568 FEATURE_DETECTION macro is disabled by default, and is currently an 569 experimental procedure. Platforms can explicitly make use of this by 570 mechanism, by enabling it to validate whether they have set their build flags 571 properly at an early phase. 572 573- ``FIP_NAME``: This is an optional build option which specifies the FIP 574 filename for the ``fip`` target. Default is ``fip.bin``. 575 576- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 577 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 578 579- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 580 581 :: 582 583 0: Encryption is done with Secret Symmetric Key (SSK) which is common 584 for a class of devices. 585 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 586 unique per device. 587 588 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 589 590- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 591 tool to create certificates as per the Chain of Trust described in 592 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 593 include the certificates in the FIP and FWU_FIP. Default value is '0'. 594 595 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 596 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 597 the corresponding certificates, and to include those certificates in the 598 FIP and FWU_FIP. 599 600 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 601 images will not include support for Trusted Board Boot. The FIP will still 602 include the corresponding certificates. This FIP can be used to verify the 603 Chain of Trust on the host machine through other mechanisms. 604 605 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 606 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 607 will not include the corresponding certificates, causing a boot failure. 608 609- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 610 inherent support for specific EL3 type interrupts. Setting this build option 611 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 612 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 613 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 614 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 615 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 616 the Secure Payload interrupts needs to be synchronously handed over to Secure 617 EL1 for handling. The default value of this option is ``0``, which means the 618 Group 0 interrupts are assumed to be handled by Secure EL1. 619 620- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 621 Interrupts, resulting from errors in NS world, will be always trapped in 622 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 623 will be trapped in the current exception level (or in EL1 if the current 624 exception level is EL0). 625 626- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 627 software operations are required for CPUs to enter and exit coherency. 628 However, newer systems exist where CPUs' entry to and exit from coherency 629 is managed in hardware. Such systems require software to only initiate these 630 operations, and the rest is managed in hardware, minimizing active software 631 management. In such systems, this boolean option enables TF-A to carry out 632 build and run-time optimizations during boot and power management operations. 633 This option defaults to 0 and if it is enabled, then it implies 634 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 635 636 If this flag is disabled while the platform which TF-A is compiled for 637 includes cores that manage coherency in hardware, then a compilation error is 638 generated. This is based on the fact that a system cannot have, at the same 639 time, cores that manage coherency in hardware and cores that don't. In other 640 words, a platform cannot have, at the same time, cores that require 641 ``HW_ASSISTED_COHERENCY=1`` and cores that require 642 ``HW_ASSISTED_COHERENCY=0``. 643 644 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 645 translation library (xlat tables v2) must be used; version 1 of translation 646 library is not supported. 647 648- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 649 implementation defined system register accesses from lower ELs. Default 650 value is ``0``. 651 652- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 653 bottom, higher addresses at the top. This build flag can be set to '1' to 654 invert this behavior. Lower addresses will be printed at the top and higher 655 addresses at the bottom. 656 657- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 658 used for generating the PKCS keys and subsequent signing of the certificate. 659 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 660 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 661 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 662 compatibility. The default value of this flag is ``rsa`` which is the TBBR 663 compliant PKCS#1 RSA 2.1 scheme. 664 665- ``KEY_SIZE``: This build flag enables the user to select the key size for 666 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 667 depend on the chosen algorithm and the cryptographic module. 668 669 +---------------------------+------------------------------------+ 670 | KEY_ALG | Possible key sizes | 671 +===========================+====================================+ 672 | rsa | 1024 , 2048 (default), 3072, 4096* | 673 +---------------------------+------------------------------------+ 674 | ecdsa | unavailable | 675 +---------------------------+------------------------------------+ 676 | ecdsa-brainpool-regular | unavailable | 677 +---------------------------+------------------------------------+ 678 | ecdsa-brainpool-twisted | unavailable | 679 +---------------------------+------------------------------------+ 680 681 682 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 683 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 684 685- ``HASH_ALG``: This build flag enables the user to select the secure hash 686 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 687 The default value of this flag is ``sha256``. 688 689- ``LDFLAGS``: Extra user options appended to the linkers' command line in 690 addition to the one set by the build system. 691 692- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 693 output compiled into the build. This should be one of the following: 694 695 :: 696 697 0 (LOG_LEVEL_NONE) 698 10 (LOG_LEVEL_ERROR) 699 20 (LOG_LEVEL_NOTICE) 700 30 (LOG_LEVEL_WARNING) 701 40 (LOG_LEVEL_INFO) 702 50 (LOG_LEVEL_VERBOSE) 703 704 All log output up to and including the selected log level is compiled into 705 the build. The default value is 40 in debug builds and 20 in release builds. 706 707- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 708 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 709 provide trust that the code taking the measurements and recording them has 710 not been tampered with. 711 712 This option defaults to 0. 713 714- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 715 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 716 the measurements and recording them as per `PSA DRTM specification`_. For 717 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 718 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 719 should have mechanism to authenticate BL31. This is an experimental feature. 720 721 This option defaults to 0. 722 723- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 724 specifies the file that contains the Non-Trusted World private key in PEM 725 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 726 727- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 728 optional. It is only needed if the platform makefile specifies that it 729 is required in order to build the ``fwu_fip`` target. 730 731- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 732 contents upon world switch. It can take either 0 (don't save and restore) or 733 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 734 wants the timer registers to be saved and restored. 735 736- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 737 tb_fw_config device tree. This flag is defined only when 738 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 739 740- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 741 for the BL image. It can be either 0 (include) or 1 (remove). The default 742 value is 0. 743 744- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 745 the underlying hardware is not a full PL011 UART but a minimally compliant 746 generic UART, which is a subset of the PL011. The driver will not access 747 any register that is not part of the SBSA generic UART specification. 748 Default value is 0 (a full PL011 compliant UART is present). 749 750- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 751 must be subdirectory of any depth under ``plat/``, and must contain a 752 platform makefile named ``platform.mk``. For example, to build TF-A for the 753 Arm Juno board, select PLAT=juno. 754 755- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 756 instead of the normal boot flow. When defined, it must specify the entry 757 point address for the preloaded BL33 image. This option is incompatible with 758 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 759 over ``PRELOADED_BL33_BASE``. 760 761- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 762 vector address can be programmed or is fixed on the platform. It can take 763 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 764 programmable reset address, it is expected that a CPU will start executing 765 code directly at the right address, both on a cold and warm reset. In this 766 case, there is no need to identify the entrypoint on boot and the boot path 767 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 768 does not need to be implemented in this case. 769 770- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 771 possible for the PSCI power-state parameter: original and extended State-ID 772 formats. This flag if set to 1, configures the generic PSCI layer to use the 773 extended format. The default value of this flag is 0, which means by default 774 the original power-state format is used by the PSCI implementation. This flag 775 should be specified by the platform makefile and it governs the return value 776 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 777 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 778 set to 1 as well. 779 780- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 781 OS-initiated mode. This option defaults to 0. 782 783- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features 784 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 785 or later CPUs. This flag can take the values 0 to 2, to align with the 786 ``FEATURE_DETECTION`` mechanism. 787 788- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors 789 originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, 790 ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. 791 792- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 793 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 794 entrypoint) or 1 (CPU reset to BL31 entrypoint). 795 The default value is 0. 796 797- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 798 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 799 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 800 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 801 802- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 803 file that contains the ROT private key in PEM format and enforces public key 804 hash generation. If ``SAVE_KEYS=1``, this 805 file name will be used to save the key. 806 807- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 808 certificate generation tool to save the keys used to establish the Chain of 809 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 810 811- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 812 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 813 target. 814 815- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 816 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 817 this file name will be used to save the key. 818 819- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 820 optional. It is only needed if the platform makefile specifies that it 821 is required in order to build the ``fwu_fip`` target. 822 823- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 824 Delegated Exception Interface to BL31 image. This defaults to ``0``. 825 826 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 827 set to ``1``. 828 829- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 830 isolated on separate memory pages. This is a trade-off between security and 831 memory usage. See "Isolating code and read-only data on separate memory 832 pages" section in :ref:`Firmware Design`. This flag is disabled by default 833 and affects all BL images. 834 835- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 836 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 837 allocated in RAM discontiguous from the loaded firmware image. When set, the 838 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 839 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 840 sections are placed in RAM immediately following the loaded firmware image. 841 842- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 843 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 844 discontiguous from loaded firmware images. When set, the platform need to 845 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 846 flag is disabled by default and NOLOAD sections are placed in RAM immediately 847 following the loaded firmware image. 848 849- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 850 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 851 UEFI+ACPI this can provide a certain amount of OS forward compatibility 852 with newer platforms that aren't ECAM compliant. 853 854- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 855 This build option is only valid if ``ARCH=aarch64``. The value should be 856 the path to the directory containing the SPD source, relative to 857 ``services/spd/``; the directory is expected to contain a makefile called 858 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 859 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 860 cannot be enabled when the ``SPM_MM`` option is enabled. 861 862- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 863 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 864 execution in BL1 just before handing over to BL31. At this point, all 865 firmware images have been loaded in memory, and the MMU and caches are 866 turned off. Refer to the "Debugging options" section for more details. 867 868- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 869 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 870 component runs at the EL3 exception level. The default value is ``0`` ( 871 disabled). This configuration supports pre-Armv8.4 platforms (aka not 872 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 873 874- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 875 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 876 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 877 mechanism should be used. 878 879- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 880 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 881 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 882 extension. This is the default when enabling the SPM Dispatcher. When 883 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 884 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 885 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 886 extension). 887 888- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 889 Partition Manager (SPM) implementation. The default value is ``0`` 890 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 891 enabled (``SPD=spmd``). 892 893- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 894 description of secure partitions. The build system will parse this file and 895 package all secure partition blobs into the FIP. This file is not 896 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 897 898- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 899 secure interrupts (caught through the FIQ line). Platforms can enable 900 this directive if they need to handle such interruption. When enabled, 901 the FIQ are handled in monitor mode and non secure world is not allowed 902 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 903 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 904 905- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 906 Platforms can configure this if they need to lower the hardware 907 limit, for example due to asymmetric configuration or limitations of 908 software run at lower ELs. The default is the architectural maximum 909 of 2048 which should be suitable for most configurations, the 910 hardware will limit the effective VL to the maximum physically supported 911 VL. 912 913- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 914 Random Number Generator Interface to BL31 image. This defaults to ``0``. 915 916- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 917 Boot feature. When set to '1', BL1 and BL2 images include support to load 918 and verify the certificates and images in a FIP, and BL1 includes support 919 for the Firmware Update. The default value is '0'. Generation and inclusion 920 of certificates in the FIP and FWU_FIP depends upon the value of the 921 ``GENERATE_COT`` option. 922 923 .. warning:: 924 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 925 already exist in disk, they will be overwritten without further notice. 926 927- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 928 specifies the file that contains the Trusted World private key in PEM 929 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 930 931- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 932 synchronous, (see "Initializing a BL32 Image" section in 933 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 934 synchronous method) or 1 (BL32 is initialized using asynchronous method). 935 Default is 0. 936 937- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 938 routing model which routes non-secure interrupts asynchronously from TSP 939 to EL3 causing immediate preemption of TSP. The EL3 is responsible 940 for saving and restoring the TSP context in this routing model. The 941 default routing model (when the value is 0) is to route non-secure 942 interrupts to TSP allowing it to save its context and hand over 943 synchronously to EL3 via an SMC. 944 945 .. note:: 946 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 947 must also be set to ``1``. 948 949- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 950 internal-trusted-storage) as SP in tb_fw_config device tree. 951 952- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 953 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 954 this delay. It can take values in the range (0-15). Default value is ``0`` 955 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 956 Platforms need to explicitly update this value based on their requirements. 957 958- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 959 linker. When the ``LINKER`` build variable points to the armlink linker, 960 this flag is enabled automatically. To enable support for armlink, platforms 961 will have to provide a scatter file for the BL image. Currently, Tegra 962 platforms use the armlink support to compile BL3-1 images. 963 964- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 965 memory region in the BL memory map or not (see "Use of Coherent memory in 966 TF-A" section in :ref:`Firmware Design`). It can take the value 1 967 (Coherent memory region is included) or 0 (Coherent memory region is 968 excluded). Default is 1. 969 970- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 971 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 972 Default is 0. 973 974- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 975 firmware configuration framework. This will move the io_policies into a 976 configuration device tree, instead of static structure in the code base. 977 978- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 979 at runtime using fconf. If this flag is enabled, COT descriptors are 980 statically captured in tb_fw_config file in the form of device tree nodes 981 and properties. Currently, COT descriptors used by BL2 are moved to the 982 device tree and COT descriptors used by BL1 are retained in the code 983 base statically. 984 985- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 986 runtime using firmware configuration framework. The platform specific SDEI 987 shared and private events configuration is retrieved from device tree rather 988 than static C structures at compile time. This is only supported if 989 SDEI_SUPPORT build flag is enabled. 990 991- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 992 and Group1 secure interrupts using the firmware configuration framework. The 993 platform specific secure interrupt property descriptor is retrieved from 994 device tree in runtime rather than depending on static C structure at compile 995 time. 996 997- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 998 This feature creates a library of functions to be placed in ROM and thus 999 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1000 is 0. 1001 1002- ``V``: Verbose build. If assigned anything other than 0, the build commands 1003 are printed. Default is 0. 1004 1005- ``VERSION_STRING``: String used in the log output for each TF-A image. 1006 Defaults to a string formed by concatenating the version number, build type 1007 and build string. 1008 1009- ``W``: Warning level. Some compiler warning options of interest have been 1010 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1011 each level enabling more warning options. Default is 0. 1012 1013 This option is closely related to the ``E`` option, which enables 1014 ``-Werror``. 1015 1016 - ``W=0`` (default) 1017 1018 Enables a wide assortment of warnings, most notably ``-Wall`` and 1019 ``-Wextra``, as well as various bad practices and things that are likely to 1020 result in errors. Includes some compiler specific flags. No warnings are 1021 expected at this level for any build. 1022 1023 - ``W=1`` 1024 1025 Enables warnings we want the generic build to include but are too time 1026 consuming to fix at the moment. It re-enables warnings taken out for 1027 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1028 to eventually be merged into ``W=0``. Some warnings are expected on some 1029 builds, but new contributions should not introduce new ones. 1030 1031 - ``W=2`` (recommended) 1032 1033 Enables warnings we want the generic build to include but cannot be enabled 1034 due to external libraries. This level is expected to eventually be merged 1035 into ``W=0``. Lots of warnings are expected, primarily from external 1036 libraries like zlib and compiler-rt, but new controbutions should not 1037 introduce new ones. 1038 1039 - ``W=3`` 1040 1041 Enables warnings that are informative but not necessary and generally too 1042 verbose and frequently ignored. A very large number of warnings are 1043 expected. 1044 1045 The exact set of warning flags depends on the compiler and TF-A warning 1046 level, however they are all succinctly set in the top-level Makefile. Please 1047 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1048 individual flags. 1049 1050- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1051 the CPU after warm boot. This is applicable for platforms which do not 1052 require interconnect programming to enable cache coherency (eg: single 1053 cluster platforms). If this option is enabled, then warm boot path 1054 enables D-caches immediately after enabling MMU. This option defaults to 0. 1055 1056- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1057 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1058 default value of this flag is ``no``. Note this option must be enabled only 1059 for ARM architecture greater than Armv8.5-A. 1060 1061- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1062 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1063 The default value of this flag is ``0``. 1064 1065 ``AT`` speculative errata workaround disables stage1 page table walk for 1066 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1067 produces either the correct result or failure without TLB allocation. 1068 1069 This boolean option enables errata for all below CPUs. 1070 1071 +---------+--------------+-------------------------+ 1072 | Errata | CPU | Workaround Define | 1073 +=========+==============+=========================+ 1074 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1075 +---------+--------------+-------------------------+ 1076 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1077 +---------+--------------+-------------------------+ 1078 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1079 +---------+--------------+-------------------------+ 1080 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1081 +---------+--------------+-------------------------+ 1082 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1083 +---------+--------------+-------------------------+ 1084 1085 .. note:: 1086 This option is enabled by build only if platform sets any of above defines 1087 mentioned in ’Workaround Define' column in the table. 1088 If this option is enabled for the EL3 software then EL2 software also must 1089 implement this workaround due to the behaviour of the errata mentioned 1090 in new SDEN document which will get published soon. 1091 1092- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1093 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1094 This flag is disabled by default. 1095 1096- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1097 host machine where a custom installation of OpenSSL is located, which is used 1098 to build the certificate generation, firmware encryption and FIP tools. If 1099 this option is not set, the default OS installation will be used. 1100 1101- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1102 functions that wait for an arbitrary time length (udelay and mdelay). The 1103 default value is 0. 1104 1105- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1106 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1107 optional architectural feature for AArch64. This flag can take the values 1108 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1109 and it is automatically disabled when the target architecture is AArch32. 1110 1111- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1112 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1113 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1114 feature for AArch64. This flag can take the values 0 to 2, to align with the 1115 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1116 disabled when the target architecture is AArch32. 1117 1118- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1119 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1120 but unused). This feature is available if trace unit such as ETMv4.x, and 1121 ETE(extending ETM feature) is implemented. This flag can take the values 1122 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1123 1124- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1125 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1126 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1127 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1128 1129- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1130 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1131 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1132 The default value is 0. 1133 1134- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1135 ``plat_can_cmo`` which will return zero if cache management operations should 1136 be skipped and non-zero otherwise. By default, this option is disabled which 1137 means platform hook won't be checked and CMOs will always be performed when 1138 related functions are called. 1139 1140- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1141 firmware interface for the BL31 image. By default its disabled (``0``). 1142 1143- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1144 errata mitigation for platforms with a non-arm interconnect using the errata 1145 ABI. By default its disabled (``0``). 1146 1147GICv3 driver options 1148-------------------- 1149 1150GICv3 driver files are included using directive: 1151 1152``include drivers/arm/gic/v3/gicv3.mk`` 1153 1154The driver can be configured with the following options set in the platform 1155makefile: 1156 1157- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1158 Enabling this option will add runtime detection support for the 1159 GIC-600, so is safe to select even for a GIC500 implementation. 1160 This option defaults to 0. 1161 1162- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1163 for GIC-600 AE. Enabling this option will introduce support to initialize 1164 the FMU. Platforms should call the init function during boot to enable the 1165 FMU and its safety mechanisms. This option defaults to 0. 1166 1167- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1168 functionality. This option defaults to 0 1169 1170- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1171 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1172 functions. This is required for FVP platform which need to simulate GIC save 1173 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1174 1175- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1176 This option defaults to 0. 1177 1178- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1179 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1180 1181Debugging options 1182----------------- 1183 1184To compile a debug version and make the build more verbose use 1185 1186.. code:: shell 1187 1188 make PLAT=<platform> DEBUG=1 V=1 all 1189 1190AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1191(for example Arm-DS) might not support this and may need an older version of 1192DWARF symbols to be emitted by GCC. This can be achieved by using the 1193``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1194the version to 4 is recommended for Arm-DS. 1195 1196When debugging logic problems it might also be useful to disable all compiler 1197optimizations by using ``-O0``. 1198 1199.. warning:: 1200 Using ``-O0`` could cause output images to be larger and base addresses 1201 might need to be recalculated (see the **Memory layout on Arm development 1202 platforms** section in the :ref:`Firmware Design`). 1203 1204Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1205``LDFLAGS``: 1206 1207.. code:: shell 1208 1209 CFLAGS='-O0 -gdwarf-2' \ 1210 make PLAT=<platform> DEBUG=1 V=1 all 1211 1212Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1213ignored as the linker is called directly. 1214 1215It is also possible to introduce an infinite loop to help in debugging the 1216post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1217``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1218section. In this case, the developer may take control of the target using a 1219debugger when indicated by the console output. When using Arm-DS, the following 1220commands can be used: 1221 1222:: 1223 1224 # Stop target execution 1225 interrupt 1226 1227 # 1228 # Prepare your debugging environment, e.g. set breakpoints 1229 # 1230 1231 # Jump over the debug loop 1232 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1233 1234 # Resume execution 1235 continue 1236 1237Firmware update options 1238----------------------- 1239 1240- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1241 in defining the firmware update metadata structure. This flag is by default 1242 set to '2'. 1243 1244- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1245 firmware bank. Each firmware bank must have the same number of images as per 1246 the `PSA FW update specification`_. 1247 This flag is used in defining the firmware update metadata structure. This 1248 flag is by default set to '1'. 1249 1250- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1251 `PSA FW update specification`_. The default value is 0, and this is an 1252 experimental feature. 1253 PSA firmware update implementation has some limitations, such as BL2 is 1254 not part of the protocol-updatable images, if BL2 needs to be updated, then 1255 it should be done through another platform-defined mechanism, and it assumes 1256 that the platform's hardware supports CRC32 instructions. 1257 1258-------------- 1259 1260*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1261 1262.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1263.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1264.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1265.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1266.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1267