1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * Top-level SMC handler for ZynqMP power management calls and 10 * IPI setup functions for communication with PMU. 11 */ 12 13 #include <errno.h> 14 15 #include <common/runtime_svc.h> 16 #if ZYNQMP_WDT_RESTART 17 #include <arch_helpers.h> 18 #include <drivers/arm/gicv2.h> 19 #include <lib/mmio.h> 20 #include <lib/spinlock.h> 21 #include <plat/common/platform.h> 22 #endif 23 24 #include <plat_private.h> 25 #include "pm_client.h" 26 #include "pm_ipi.h" 27 #include "zynqmp_pm_api_sys.h" 28 #include "zynqmp_pm_defs.h" 29 30 /* pm_up = !0 - UP, pm_up = 0 - DOWN */ 31 static int32_t pm_up, ipi_irq_flag; 32 33 #if ZYNQMP_WDT_RESTART 34 static spinlock_t inc_lock; 35 static int active_cores = 0; 36 #endif 37 38 /** 39 * typedef pm_ctx_t - Structure which contains data for power management. 40 * @api_version: version of PM API, must match with one on PMU side. 41 * @payload: payload array used to store received. 42 * data from ipi buffer registers. 43 * 44 */ 45 typedef struct { 46 uint32_t api_version; 47 uint32_t payload[PAYLOAD_ARG_CNT]; 48 } pm_ctx_t; 49 50 static pm_ctx_t pm_ctx; 51 52 #if ZYNQMP_WDT_RESTART 53 /** 54 * trigger_wdt_restart() - Trigger warm restart event to APU cores. 55 * 56 * This function triggers SGI for all active APU CPUs. SGI handler then 57 * power down CPU and call system reset. 58 * 59 */ 60 static void trigger_wdt_restart(void) 61 { 62 uint32_t core_count = 0; 63 uint32_t core_status[3]; 64 uint32_t target_cpu_list = 0; 65 int i; 66 67 for (i = 0; i < 4; i++) { 68 pm_get_node_status(NODE_APU_0 + i, core_status); 69 if (core_status[0] == 1) { 70 core_count++; 71 target_cpu_list |= (1 << i); 72 } 73 } 74 75 spin_lock(&inc_lock); 76 active_cores = core_count; 77 spin_unlock(&inc_lock); 78 79 INFO("Active Cores: %d\n", active_cores); 80 81 for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { 82 if (target_cpu_list & (1 << i)) { 83 /* trigger SGI to active cores */ 84 plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); 85 } 86 } 87 } 88 89 /** 90 * ttc_fiq_handler() - TTC Handler for timer event. 91 * @id: number of the highest priority pending interrupt of the type 92 * that this handler was registered for. 93 * @flags: security state, bit[0]. 94 * @handle: pointer to 'cpu_context' structure of the current CPU for the 95 * security state specified in the 'flags' parameter. 96 * @cookie: unused. 97 * 98 * Function registered as INTR_TYPE_EL3 interrupt handler. 99 * 100 * When WDT event is received in PMU, PMU needs to notify master to do cleanup 101 * if required. PMU sets up timer and starts timer to overflow in zero time upon 102 * WDT event. TF-A handles this timer event and takes necessary action required 103 * for warm restart. 104 * 105 * In presence of non-secure software layers (EL1/2) sets the interrupt 106 * at registered entrance in GIC and informs that PMU responded or demands 107 * action. 108 * 109 * Return: 0 on success. 110 * 111 */ 112 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, 113 void *cookie) 114 { 115 INFO("BL31: Got TTC FIQ\n"); 116 117 plat_ic_end_of_interrupt(id); 118 119 /* Clear TTC interrupt by reading interrupt register */ 120 mmio_read_32(TTC3_INTR_REGISTER_1); 121 122 /* Disable the timer interrupts */ 123 mmio_write_32(TTC3_INTR_ENABLE_1, 0); 124 125 trigger_wdt_restart(); 126 127 return 0; 128 } 129 130 /** 131 * zynqmp_sgi7_irq() - Handler for SGI7 IRQ. 132 * @id: number of the highest priority pending interrupt of the type 133 * that this handler was registered for. 134 * @flags: security state, bit[0]. 135 * @handle: pointer to 'cpu_context' structure of the current CPU for the 136 * security state specified in the 'flags' parameter. 137 * @cookie: unused. 138 * 139 * Function registered as INTR_TYPE_EL3 interrupt handler 140 * 141 * On receiving WDT event from PMU, TF-A generates SGI7 to all running CPUs. 142 * In response to SGI7 interrupt, each CPUs do clean up if required and last 143 * running CPU calls system restart. 144 * 145 * Return: This function does not return a value and it enters into wfi. 146 */ 147 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, 148 void *handle, void *cookie) 149 { 150 int i; 151 uint32_t value; 152 153 /* enter wfi and stay there */ 154 INFO("Entering wfi\n"); 155 156 spin_lock(&inc_lock); 157 active_cores--; 158 159 for (i = 0; i < 4; i++) { 160 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, 161 0xffffffff); 162 } 163 164 dsb(); 165 166 spin_unlock(&inc_lock); 167 168 if (active_cores == 0) { 169 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value); 170 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; 171 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value); 172 } 173 174 /* enter wfi and stay there */ 175 while (1) 176 wfi(); 177 } 178 179 /** 180 * pm_wdt_restart_setup() - Setup warm restart interrupts. 181 * 182 * Return: Returns status, 0 on success or error+reason. 183 * 184 * This function sets up handler for SGI7 and TTC interrupts 185 * used for warm restart. 186 */ 187 static int pm_wdt_restart_setup(void) 188 { 189 int ret; 190 191 /* register IRQ handler for SGI7 */ 192 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq); 193 if (ret) { 194 WARN("BL31: registering SGI7 interrupt failed\n"); 195 goto err; 196 } 197 198 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler); 199 if (ret) 200 WARN("BL31: registering TTC3 interrupt failed\n"); 201 202 err: 203 return ret; 204 } 205 #endif 206 207 /** 208 * pm_setup() - PM service setup. 209 * 210 * Return: On success, the initialization function must return 0. 211 * Any other return value will cause the framework to ignore 212 * the service. 213 * 214 * Initialization functions for ZynqMP power management for 215 * communicaton with PMU. 216 * 217 * Called from sip_svc_setup initialization function with the 218 * rt_svc_init signature. 219 * 220 */ 221 int32_t pm_setup(void) 222 { 223 enum pm_ret_status err; 224 225 pm_ipi_init(primary_proc); 226 227 err = pm_get_api_version(&pm_ctx.api_version); 228 if (err != PM_RET_SUCCESS) { 229 ERROR("BL31: Failed to read Platform Management API version. " 230 "Return: %d\n", err); 231 return -EINVAL; 232 } 233 if (pm_ctx.api_version < PM_VERSION) { 234 ERROR("BL31: Platform Management API version error. Expected: " 235 "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR, 236 PM_VERSION_MINOR, pm_ctx.api_version >> 16, 237 pm_ctx.api_version & 0xFFFFU); 238 return -EINVAL; 239 } 240 241 int32_t status = 0, ret = 0; 242 #if ZYNQMP_WDT_RESTART 243 status = pm_wdt_restart_setup(); 244 if (status) 245 WARN("BL31: warm-restart setup failed\n"); 246 #endif 247 248 if (status >= 0) { 249 INFO("BL31: PM Service Init Complete: API v%d.%d\n", 250 PM_VERSION_MAJOR, PM_VERSION_MINOR); 251 ret = 0; 252 } else { 253 INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); 254 ret = status; 255 } 256 257 pm_up = !status; 258 259 return ret; 260 } 261 262 /** 263 * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. 264 * @smc_fid: Function Identifier. 265 * @x1: Arguments. 266 * @x2: Arguments. 267 * @x3: Arguments. 268 * @x4: Arguments. 269 * @cookie: Unused. 270 * @handle: Pointer to caller's context structure. 271 * @flags: SECURE_FLAG or NON_SECURE_FLAG. 272 * 273 * Determines that smc_fid is valid and supported PM SMC Function ID from the 274 * list of pm_api_ids, otherwise completes the request with 275 * the unknown SMC Function ID. 276 * 277 * The SMC calls for PM service are forwarded from SIP Service SMC handler 278 * function with rt_svc_handle signature. 279 * 280 * Return: Unused. 281 * 282 */ 283 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 284 uint64_t x4, const void *cookie, void *handle, uint64_t flags) 285 { 286 enum pm_ret_status ret; 287 uint32_t payload[PAYLOAD_ARG_CNT]; 288 289 uint32_t pm_arg[5]; 290 uint32_t result[PAYLOAD_ARG_CNT] = {0}; 291 uint32_t api_id; 292 293 /* Handle case where PM wasn't initialized properly */ 294 if (pm_up == 0) 295 SMC_RET1(handle, SMC_UNK); 296 297 pm_arg[0] = (uint32_t)x1; 298 pm_arg[1] = (uint32_t)(x1 >> 32); 299 pm_arg[2] = (uint32_t)x2; 300 pm_arg[3] = (uint32_t)(x2 >> 32); 301 pm_arg[4] = (uint32_t)x3; 302 303 api_id = smc_fid & FUNCID_NUM_MASK; 304 305 switch (api_id) { 306 /* PM API Functions */ 307 case PM_SELF_SUSPEND: 308 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 309 pm_arg[3]); 310 SMC_RET1(handle, (uint64_t)ret); 311 312 case PM_REQ_SUSPEND: 313 ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 314 pm_arg[3]); 315 SMC_RET1(handle, (uint64_t)ret); 316 317 case PM_REQ_WAKEUP: 318 { 319 /* Use address flag is encoded in the 1st bit of the low-word */ 320 uint32_t set_addr = pm_arg[1] & 0x1U; 321 uint64_t address = (uint64_t)pm_arg[2] << 32U; 322 323 address |= pm_arg[1] & (~0x1U); 324 ret = pm_req_wakeup(pm_arg[0], set_addr, address, 325 pm_arg[3]); 326 SMC_RET1(handle, (uint64_t)ret); 327 } 328 329 case PM_FORCE_POWERDOWN: 330 ret = pm_force_powerdown(pm_arg[0], pm_arg[1]); 331 SMC_RET1(handle, (uint64_t)ret); 332 333 case PM_ABORT_SUSPEND: 334 ret = pm_abort_suspend(pm_arg[0]); 335 SMC_RET1(handle, (uint64_t)ret); 336 337 case PM_SET_WAKEUP_SOURCE: 338 ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]); 339 SMC_RET1(handle, (uint64_t)ret); 340 341 case PM_SYSTEM_SHUTDOWN: 342 ret = pm_system_shutdown(pm_arg[0], pm_arg[1]); 343 SMC_RET1(handle, (uint64_t)ret); 344 345 case PM_REQ_NODE: 346 ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 347 SMC_RET1(handle, (uint64_t)ret); 348 349 case PM_SET_REQUIREMENT: 350 ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], 351 pm_arg[3]); 352 SMC_RET1(handle, (uint64_t)ret); 353 354 case PM_GET_API_VERSION: 355 if (ipi_irq_flag == 0U) { 356 /* 357 * Enable IPI IRQ 358 * assume the rich OS is OK to handle callback IRQs now. 359 * Even if we were wrong, it would not enable the IRQ in 360 * the GIC. 361 */ 362 pm_ipi_irq_enable(primary_proc); 363 ipi_irq_flag = 1U; 364 } 365 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 366 ((uint64_t)pm_ctx.api_version << 32)); 367 case PM_FPGA_LOAD: 368 ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 369 SMC_RET1(handle, (uint64_t)ret); 370 371 case PM_FPGA_GET_STATUS: 372 { 373 uint32_t value = 0U; 374 375 ret = pm_fpga_get_status(&value); 376 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 377 } 378 379 case PM_SECURE_RSA_AES: 380 ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2], 381 pm_arg[3]); 382 SMC_RET1(handle, (uint64_t)ret); 383 384 case PM_GET_CALLBACK_DATA: 385 ret = pm_get_callbackdata(result, ARRAY_SIZE(result)); 386 if (ret != PM_RET_SUCCESS) { 387 result[0] = ret; 388 } 389 390 SMC_RET2(handle, 391 (uint64_t)result[0] | ((uint64_t)result[1] << 32), 392 (uint64_t)result[2] | ((uint64_t)result[3] << 32)); 393 case PM_IOCTL: 394 { 395 uint32_t value = 0U; 396 397 ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], 398 pm_arg[3], &value); 399 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 400 } 401 402 case PM_QUERY_DATA: 403 { 404 uint32_t data[4] = { 0 }; 405 406 pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], 407 pm_arg[3], data); 408 SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32), 409 (uint64_t)data[2] | ((uint64_t)data[3] << 32)); 410 } 411 412 case PM_CLOCK_ENABLE: 413 ret = pm_clock_enable(pm_arg[0]); 414 SMC_RET1(handle, (uint64_t)ret); 415 416 case PM_CLOCK_DISABLE: 417 ret = pm_clock_disable(pm_arg[0]); 418 SMC_RET1(handle, (uint64_t)ret); 419 420 case PM_CLOCK_GETSTATE: 421 { 422 uint32_t value = 0U; 423 424 ret = pm_clock_getstate(pm_arg[0], &value); 425 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 426 } 427 428 case PM_CLOCK_SETDIVIDER: 429 ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]); 430 SMC_RET1(handle, (uint64_t)ret); 431 432 case PM_CLOCK_GETDIVIDER: 433 { 434 uint32_t value = 0U; 435 436 ret = pm_clock_getdivider(pm_arg[0], &value); 437 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 438 } 439 440 case PM_CLOCK_SETRATE: 441 ret = pm_clock_setrate(pm_arg[0], 442 ((uint64_t)pm_arg[2]) << 32 | pm_arg[1]); 443 444 SMC_RET1(handle, (uint64_t)ret); 445 446 case PM_CLOCK_GETRATE: 447 { 448 uint64_t value = 0; 449 450 ret = pm_clock_getrate(pm_arg[0], &value); 451 SMC_RET2(handle, (uint64_t)ret | 452 (((uint64_t)value & 0xFFFFFFFFU) << 32U), 453 (value >> 32U) & 0xFFFFFFFFU); 454 455 } 456 457 case PM_CLOCK_SETPARENT: 458 ret = pm_clock_setparent(pm_arg[0], pm_arg[1]); 459 SMC_RET1(handle, (uint64_t)ret); 460 461 case PM_CLOCK_GETPARENT: 462 { 463 uint32_t value = 0U; 464 465 ret = pm_clock_getparent(pm_arg[0], &value); 466 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 467 } 468 469 case PM_GET_TRUSTZONE_VERSION: 470 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 471 ((uint64_t)ZYNQMP_TZ_VERSION << 32U)); 472 473 case PM_SET_SUSPEND_MODE: 474 ret = pm_set_suspend_mode(pm_arg[0]); 475 SMC_RET1(handle, (uint64_t)ret); 476 477 case PM_SECURE_SHA: 478 ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2], 479 pm_arg[3]); 480 SMC_RET1(handle, (uint64_t)ret); 481 482 case PM_SECURE_RSA: 483 ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2], 484 pm_arg[3]); 485 SMC_RET1(handle, (uint64_t)ret); 486 487 case PM_SECURE_IMAGE: 488 { 489 ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2], 490 pm_arg[3], &result[0]); 491 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), 492 result[1]); 493 } 494 495 case PM_FPGA_READ: 496 { 497 uint32_t value = 0U; 498 499 ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], 500 &value); 501 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 502 } 503 504 case PM_SECURE_AES: 505 { 506 uint32_t value = 0U; 507 508 ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value); 509 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 510 } 511 512 case PM_PLL_SET_PARAMETER: 513 ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]); 514 SMC_RET1(handle, (uint64_t)ret); 515 516 case PM_PLL_GET_PARAMETER: 517 { 518 uint32_t value = 0U; 519 520 ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value); 521 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U)); 522 } 523 524 case PM_PLL_SET_MODE: 525 ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]); 526 SMC_RET1(handle, (uint64_t)ret); 527 528 case PM_PLL_GET_MODE: 529 { 530 uint32_t mode = 0U; 531 532 ret = pm_pll_get_mode(pm_arg[0], &mode); 533 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U)); 534 } 535 536 case PM_REGISTER_ACCESS: 537 { 538 uint32_t value = 0U; 539 540 ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2], 541 pm_arg[3], &value); 542 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 543 } 544 545 case PM_EFUSE_ACCESS: 546 { 547 uint32_t value = 0U; 548 549 #if defined(ZYNQMP_SECURE_EFUSES) 550 if (is_caller_non_secure(flags)) { 551 SMC_RET1(handle, 552 (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) | 553 (uint64_t)PM_RET_ERROR_ACCESS); 554 } 555 #endif 556 ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value); 557 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 558 } 559 560 case PM_FPGA_GET_VERSION: 561 case PM_FPGA_GET_FEATURE_LIST: 562 { 563 uint32_t ret_payload[PAYLOAD_ARG_CNT]; 564 565 PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK, 566 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 567 ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); 568 SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U, 569 (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U); 570 } 571 572 case PM_FEATURE_CHECK: 573 { 574 uint32_t version = 0; 575 uint32_t bit_mask[2] = {0}; 576 577 ret = pm_feature_check(pm_arg[0], &version, bit_mask, 578 ARRAY_SIZE(bit_mask)); 579 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U), 580 (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)); 581 } 582 583 default: 584 /* Send request to the PMU */ 585 PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1], 586 pm_arg[2], pm_arg[3], pm_arg[4]); 587 ret = pm_ipi_send_sync(primary_proc, payload, result, 588 PAYLOAD_ARG_CNT); 589 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), 590 (uint64_t)result[1] | ((uint64_t)result[2] << 32U)); 591 } 592 } 593