| 992f091b | 12-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
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| 52ff3b4c | 17-Dec-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "doc: Fix indentation in build options documentation" into integration |
| 535fa663 | 17-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
doc: Fix indentation in build options documentation
Sphinx was showing the following warning message:
docs/getting_started/build-options.rst:200: WARNING: Bullet list ends
without a blank line; une
doc: Fix indentation in build options documentation
Sphinx was showing the following warning message:
docs/getting_started/build-options.rst:200: WARNING: Bullet list ends
without a blank line; unexpected unindent.
Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 186acdd9 | 16-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "cryptocell: add cryptocell 712 RSA 3K support" into integration |
| b8622922 | 15-Sep-2019 |
Gilad Ben-Yossef <gilad.benyossef@arm.com> |
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Chang
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17
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| edbce9aa | 12-Nov-2019 |
zelalem-aweke <zelalem.aweke@arm.com> |
Enable Link Time Optimization in GCC
This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.
LTO is enabled only for aarch64
Enable Link Time Optimization in GCC
This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.
LTO is enabled only for aarch64 as there seem to be
a bug in the aarch32 compiler when LTO is enabled.
The changes in the makefiles include:
- Adding -flto and associated flags to enable LTO.
- Using gcc as a wrapper at link time instead of ld.
This is recommended when using LTO as gcc internally
takes care of invoking the necessary plugins for LTO.
- Adding switches to pass options to ld.
- Adding a flag to disable fix for erratum cortex-a53-843419
unless explicitly enabled. This is needed because GCC
seem to automatically add the erratum fix when used
as a wrapper for LD.
Additionally, this patch updates the TF-A user guide with
the new build option.
Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com>
Change-Id: I1188c11974da98434b7dc9344e058cd1eacf5468
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| 76f25eb5 | 29-Nov-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "Changes to support updated register usage in SMCCC v1.2" into integration |
| 43f35ef5 | 29-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Split the User Guide into multiple files
The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information
doc: Split the User Guide into multiple files
The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information from. Currently, it covers
these topics and maybe a couple more:
- Requirements (hardware, tools, libs)
- Checking out the repo
- Basic build instructions
- A comprehensive list of build flags
- FIP packaging
- Building specifically for Juno
- Firmware update images
- EL3 payloads
- Preloaded BL33 boot flow
- Running on FVPs
- Running on Juno
I have separated these out into a few groups that become new
documents. Broadly speaking, build instructions for the tools,
for TF-A generally, and for specific scenarios are separated.
Content relating to specific platforms (Juno and the FVPs are
Arm-specific platforms, essentially) has been moved into the
documentation that is specific to those platforms, under
docs/plat/arm.
Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| e34cc0ce | 10-Nov-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Changes to support updated register usage in SMCCC v1.2
From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch
Changes to support updated register usage in SMCCC v1.2
From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch32 state, arguments are passed in registers R0-R7 and
results are returned in registers R0-R7 for SMC32 calls.
Most of the functions and macros already existed to support using
upto 8 registers for passing/returning parameters/results. Added
few helper macros for SMC calls from AArch32 state.
Link to the specification:
https://developer.arm.com/docs/den0028/c
Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| bbf0a1e4 | 21-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Final, pre-release fixes and updates
A small set of misc changes to ensure correctness before the v2.2
release tagging.
Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e
Signed-off-by: Paul
doc: Final, pre-release fixes and updates
A small set of misc changes to ensure correctness before the v2.2
release tagging.
Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 879389ed | 18-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "Fix documentation" into integration |
| 434d93d9 | 15-Oct-2019 |
Artsem Artsemenka <artsem.artsemenka@arm.com> |
Fix documentation
User guide:
1. Remove obsolete note saying only FVP is supported with AArch32
2. Switch compiler for Juno AArch32 to arm-eabi
3. Mention SOFTWARE folder in Juno Linaro release
Ind
Fix documentation
User guide:
1. Remove obsolete note saying only FVP is supported with AArch32
2. Switch compiler for Juno AArch32 to arm-eabi
3. Mention SOFTWARE folder in Juno Linaro release
Index.rst:
1. Switch default FVP model to Version 11.6 Build 45
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Ib47a2ea314e2b8394a20189bf91796de0e17de53
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| be653a69 | 04-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Misc syntax and spelling fixes
Tidying up a few Sphinx warnings that had built-up over time.
None of these are critical but it cleans up the Sphinx output.
At the same time, fixing some spelli
doc: Misc syntax and spelling fixes
Tidying up a few Sphinx warnings that had built-up over time.
None of these are critical but it cleans up the Sphinx output.
At the same time, fixing some spelling errors that were detected.
Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 862c764a | 07-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Add guide for building the docs locally
This new page contains instructions for doing a local
build of the documentation, plus information on the environment
setup that needs to be done beforeh
doc: Add guide for building the docs locally
This new page contains instructions for doing a local
build of the documentation, plus information on the environment
setup that needs to be done beforehand.
Change-Id: If563145ab40639cabbe25d0f62759981a33692c6
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 34760951 | 12-Apr-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Convert internal links to RST format
Currently links between documents are using the format:
<path/to/><filename>.rst
This was required for services like GitHub because they render each
docum
doc: Convert internal links to RST format
Currently links between documents are using the format:
<path/to/><filename>.rst
This was required for services like GitHub because they render each
document in isolation - linking to another document is like linking
to any other file, just provide the full path.
However, with the new approach, the .rst files are only the raw
source for the documents. Once the documents have been rendered
the output is now in another format (HTML in our case) and so,
when linking to another document, the link must point to the
rendered version and not the .rst file.
The RST spec provides a few methods for linking between content.
The parent of this patch enabled the automatic creation of anchors
for document titles - we will use these anchors as the targets for
our links. Additional anchors can be added by hand if needed, on
section and sub-section titles, for example.
An example of this new format, for a document with the title
"Firmware Design" is :ref:`Firmware Design`.
One big advantage of this is that anchors are not dependent on
paths. We can then move documents around, even between directories,
without breaking any links between documents. Links will need to be
updated only if the title of a document changes.
Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 5b567758 | 07-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Fix the CAS spinlock implementation" into integration |
| c97cba4e | 25-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Fix the CAS spinlock implementation
Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selecte
Fix the CAS spinlock implementation
Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selected for all ARM8.1+ platforms.
The previous CAS spinlock implementation had a bug wherein the spin_unlock()
implementation had an `sev` after `stlr` which is not sufficient. A dsb is
needed to ensure that the stlr completes prior to the sev. Having a dsb is
heavyweight and a better solution would be to use load exclusive semantics
to monitor the lock and wake up from wfe when a store happens to the lock.
The patch implements the same.
Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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|
| b48691ed | 26-Sep-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
doc: Fix GCC version to 8.3-2019.03
Change-Id: I3b866e927d93f4b690aa4891940fc8afabf4146e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 2f625c5e | 01-Oct-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "doc: Migrate to Linaro release 19.06" into integration |
| 35010bb8 | 20-Sep-2019 |
zelalem-aweke <zelalem.aweke@arm.com> |
doc: Migrate to Linaro release 19.06
- Updated Linaro release version number to 19.06
- Updated links to Linaro instructions and releases
- Removed the Linaro old releases link
Signed-off-by: zelal
doc: Migrate to Linaro release 19.06
- Updated Linaro release version number to 19.06
- Updated links to Linaro instructions and releases
- Removed the Linaro old releases link
Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com>
Change-Id: Ib786728106961e89182b42183e7b889f6fc74190
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|
| 41bda863 | 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "mp/giv3-discovery" into integration
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable mu
Merge changes from topic "mp/giv3-discovery" into integration
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable multi socket GIC redistributor frame discovery
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|
| 10107707 | 12-Aug-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Adding new optional PSCI hook pwr_domain_on_finish_late
This PSCI hook is similar to pwr_domain_on_finish but is
guaranteed to be invoked with the respective core and cluster are
participating in co
Adding new optional PSCI hook pwr_domain_on_finish_late
This PSCI hook is similar to pwr_domain_on_finish but is
guaranteed to be invoked with the respective core and cluster are
participating in coherency. This will be necessary to safely invoke
the new GICv3 API which modifies shared GIC data structures concurrently.
Change-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| f8631f51 | 14-Sep-2019 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
drivers: partition: support different block size
The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PAR
drivers: partition: support different block size
The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3
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|
| 6129e9a6 | 13-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Refactor ARMv8.3 Pointer Authentication support code" into integration |
| ed108b56 | 13-Sep-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Refactor ARMv8.3 Pointer Authentication support code
This patch provides the following features and makes modifications
listed below:
- Individual APIAKey key generation for each CPU.
- New key gene
Refactor ARMv8.3 Pointer Authentication support code
This patch provides the following features and makes modifications
listed below:
- Individual APIAKey key generation for each CPU.
- New key generation on every BL31 warm boot and TSP CPU On event.
- Per-CPU storage of APIAKey added in percpu_data[]
of cpu_data structure.
- `plat_init_apiakey()` function replaced with `plat_init_apkey()`
which returns 128-bit value and uses Generic timer physical counter
value to increase the randomness of the generated key.
The new function can be used for generation of all ARMv8.3-PAuth keys
- ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`.
- New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions
generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively;
pauth_disable_el1()` and `pauth_disable_el3()` functions disable
PAuth for EL1 and EL3 respectively;
`pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from
cpu-data structure.
- Combined `save_gp_pauth_registers()` function replaces calls to
`save_gp_registers()` and `pauth_context_save()`;
`restore_gp_pauth_registers()` replaces `pauth_context_restore()`
and `restore_gp_registers()` calls.
- `restore_gp_registers_eret()` function removed with corresponding
code placed in `el3_exit()`.
- Fixed the issue when `pauth_t pauth_ctx` structure allocated space
for 12 uint64_t PAuth registers instead of 10 by removal of macro
CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h`
and assigning its value to CTX_PAUTH_REGS_END.
- Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions
in `msr spsel` instruction instead of hard-coded values.
- Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI.
Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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