clk: sam: sckc: add at91_sckc_clk_get() to retrieve slow clock

In order to retrieve and expose clocks through SCMI, add this function
to retrieve the SCKC clock.

Signed-off-by: Clément Léger <cleme

clk: sam: sckc: add at91_sckc_clk_get() to retrieve slow clock

In order to retrieve and expose clocks through SCMI, add this function
to retrieve the SCKC clock.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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drivers: clk: sam: add at91_pmc_clk_get() function

In order to retrieve and expose clocks through SCMI, add this function
to retrieve the clocks from the PMC.

Signed-off-by: Clément Léger <clement.

drivers: clk: sam: add at91_pmc_clk_get() function

In order to retrieve and expose clocks through SCMI, add this function
to retrieve the clocks from the PMC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: add support for CFG_SCMI_MSG_SMT_FASTCALL_ENTRY

Add necessary calls to scmi_smt_fastcall_smc_entry from sm_platform
handler to be able to do SCMI calls via SMC.

Signed-off-by: Clément Lég

plat-sam: add support for CFG_SCMI_MSG_SMT_FASTCALL_ENTRY

Add necessary calls to scmi_smt_fastcall_smc_entry from sm_platform
handler to be able to do SCMI calls via SMC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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drivers: scmi-msg: add support for clock using generic clock framework

Integrating the clock framework with SCMI allows to avoid boilerplate
code to do so in platform specific files. This patch adds

drivers: scmi-msg: add support for clock using generic clock framework

Integrating the clock framework with SCMI allows to avoid boilerplate
code to do so in platform specific files. This patch adds a generic
layer that uses the generic clock framework to access and expose clocks.
SCMI clocks can be added from platform code using scmi_clk_add().
A new CFG_SCMI_MSG_USE_CLK configuration option is added to enable
this generic clock support.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: add SCMI server foundation

Add foundations for SCMI server support. This will be used to expose
clocks and regulators to non-secure world.

Signed-off-by: Clément Léger <clement.leger@boot

plat-sam: add SCMI server foundation

Add foundations for SCMI server support. This will be used to expose
clocks and regulators to non-secure world.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: nsec-service: Fix include order

Reorder includes in alphabetical order.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

clang-format: add configuration file

Adds a configuration file to be used with clang-format. This file was
copied from the Linux kernel, but with the ForEachMacros updated for
OP-TEE.

Clang-format

clang-format: add configuration file

Adds a configuration file to be used with clang-format. This file was
copied from the Linux kernel, but with the ForEachMacros updated for
OP-TEE.

Clang-format can help with formatting the code, but we are not
expecting follow it to the letter.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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plat-rzn1: increase DDR size to 1GB

There are now some RZ/N1 devices with 1GB rather than 256MB. The
first-stage bootloader does not support passing a DT to OP-TEE, so
static values are set at compi

plat-rzn1: increase DDR size to 1GB

There are now some RZ/N1 devices with 1GB rather than 256MB. The
first-stage bootloader does not support passing a DT to OP-TEE, so
static values are set at compile time. Increase the DDR size so as to
avoid OP-TEE calls failing with TEEC_ERROR_OUT_OF_MEMORY.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

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core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("

core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("core: split core/arch/arm/kernel/thread.c")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: crypto: change TEE_AEDecryptFinal() tag param's attribute

Due to tag parameter was passed in from REE side share memory
same as cipher-text source and nonce buffer/parameters.
Then memory acce

core: crypto: change TEE_AEDecryptFinal() tag param's attribute

Due to tag parameter was passed in from REE side share memory
same as cipher-text source and nonce buffer/parameters.
Then memory access sanity-check marks CCM TAG buffer as
ACCESS_DENIED, which triggers user TA panic.

Change tag parameter's attribute from [in] to [inbuf]. This fix is
expected to be addressed in next GP TEE Internal Core API specification.

Link: https://github.com/OP-TEE/optee_os/issues/5946
Signed-off-by: lei zhou <lei.zhou@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add missing conditional compilation for RISC-V

RV64 also uses kern_sp. The elf.h is also used by RV32 and RV64.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome

Add missing conditional compilation for RISC-V

RV64 also uses kern_sp. The elf.h is also used by RV32 and RV64.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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ci: add build with SPMC at S-EL2 and relocatable

Adds a build with CFG_CORE_SEL2_SPMC=y and CFG_CORE_PHYS_RELOCATABLE=y.
Dummy values are needed for CFG_TZDRAM_START and CFG_TZDRAM_SIZE since
vexpre

ci: add build with SPMC at S-EL2 and relocatable

Adds a build with CFG_CORE_SEL2_SPMC=y and CFG_CORE_PHYS_RELOCATABLE=y.
Dummy values are needed for CFG_TZDRAM_START and CFG_TZDRAM_SIZE since
vexpress-qemu_armv8a doesn't have default values for those in this
configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link ad

core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link address.

This feature is currently only supported with CFG_CORE_SEL2_SPMC=y since
the TEE core has to know the range of available memory. With SPMC at EL2
this is accomplished via get_sec_mem_from_manifest(). An SPMC at S-EL2
may need to load OP-TEE at a different address depending on
configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: parse boot info

With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The
manifest describing the OP-TEE SP is passed as a boot argument.

The manifest contains among other thin

core: ffa: parse boot info

With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The
manifest describing the OP-TEE SP is passed as a boot argument.

The manifest contains among other things the two properties
"load-address" and "mem-size". These cover the secure memory allocated
for OP-TEE to cover core and TA memory. The retrieved memory range is
saved with a call to core_mmu_set_secure_memory() to be used when
initializing MMU and other memory configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_set_secure_memory()

Adds core_mmu_set_secure_memory() for use with CFG_CORE_PHYS_RELOCATABLE
where the secure physical memory range is determined at boot.

Reviewed-by: Etienne Ca

core: add core_mmu_set_secure_memory()

Adds core_mmu_set_secure_memory() for use with CFG_CORE_PHYS_RELOCATABLE
where the secure physical memory range is determined at boot.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add dt_getprop_as_number()

Adds dt_getprop_as_number() to read a property and parse it as a number
returned as a uint64_t. The size of the property determines if it's read
as an unsigned 32-bi

core: add dt_getprop_as_number()

Adds dt_getprop_as_number() to read a property and parse it as a number
returned as a uint64_t. The size of the property determines if it's read
as an unsigned 32-bit or 64-bit integer.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: add boot info structs and defines

Adds defines to interpret FF-A Boot Info header and descriptor using two
new structs and accompanying defines.

Acked-by: Etienne Carriere <etienne.carri

core: ffa: add boot info structs and defines

Adds defines to interpret FF-A Boot Info header and descriptor using two
new structs and accompanying defines.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.c: only try to add pager vaspace when enabled

Only call add_pager_vaspace() when compiled with pager enabled to avoid
redundant looping over the memory areas to map.

Reviewed-by: Eti

core: core_mmu.c: only try to add pager vaspace when enabled

Only call add_pager_vaspace() when compiled with pager enabled to avoid
redundant looping over the memory areas to map.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: generic_ram_layout.h: remove TA_RAM_*

Removes the TA_RAM_START and TA_RAM_SIZE defines since core_mmu.c can
calculate the values based registered secure_only memory.

Reviewed-by: Etienne

core: arm: generic_ram_layout.h: remove TA_RAM_*

Removes the TA_RAM_START and TA_RAM_SIZE defines since core_mmu.c can
calculate the values based registered secure_only memory.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: virt: use core_mmu_get_ta_range()

In get_ta_ram_size() use core_mmu_get_ta_range() instead of the define
TA_RAM_SIZE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by

core: virt: use core_mmu_get_ta_range()

In get_ta_ram_size() use core_mmu_get_ta_range() instead of the define
TA_RAM_SIZE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.c: use secure_only[] where possible

Avoid using TEE_RAM_START, TEE_RAM_PH_SIZE, TA_RAM_START, and
TA_RAM_SIZE where secure_only[] can be used instead to calculate the
same numbers.

R

core: core_mmu.c: use secure_only[] where possible

Avoid using TEE_RAM_START, TEE_RAM_PH_SIZE, TA_RAM_START, and
TA_RAM_SIZE where secure_only[] can be used instead to calculate the
same numbers.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_get_ta_range()

Adds core_mmu_get_ta_range() to return the range of physical memory
reserved for TAs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Je

core: add core_mmu_get_ta_range()

Adds core_mmu_get_ta_range() to return the range of physical memory
reserved for TAs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_tee_load_pa address

Adds core_mmu_tee_load_pa for a dynamic record of where OP-TEE is loaded
into memory.

With CFG_CORE_PHYS_RELOCATABLE=y core_mmu_tee_base_pa may need to be
upd

core: add core_mmu_tee_load_pa address

Adds core_mmu_tee_load_pa for a dynamic record of where OP-TEE is loaded
into memory.

With CFG_CORE_PHYS_RELOCATABLE=y core_mmu_tee_base_pa may need to be
updated during early boot since the physical address to use isn't
determined until then.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: kernel: Fix stack pointer initialization for each hart

The RISC-V privileged specification defines that at least one hart must
have a hart ID of zero. Since at least one stack_tmp_strid

core: riscv: kernel: Fix stack pointer initialization for each hart

The RISC-V privileged specification defines that at least one hart must
have a hart ID of zero. Since at least one stack_tmp_stride is required
for calculating the initial SP value for each hart, the formula should
be address of stack_tmp plus (hartid+1) multiplied by stack_tmp_stride.

This commit fixes the formula for initializing SP of each hart,
otherwise the stack underflow happens to hart 0.

Fixes: 93e54a63925f ("riscv: kernel: entry.S: provide entry script")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: notif: fix input comment typo

Fixes inline comment typo in OP-TEE standard SMCs description and
CFG_CORE_ASYNC_NOTIF switch description.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org

core: notif: fix input comment typo

Fixes inline comment typo in OP-TEE standard SMCs description and
CFG_CORE_ASYNC_NOTIF switch description.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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