core, libutils: unpoison stack on longjmp for ASanAdds support for unpoisoning the stack when performing longjmp,to ensure correct ASan behavior.When a longjmp unwinds the stack, parts of the st
core, libutils: unpoison stack on longjmp for ASanAdds support for unpoisoning the stack when performing longjmp,to ensure correct ASan behavior.When a longjmp unwinds the stack, parts of the stack that werepoisoned during deeper calls may remain marked as inaccessible.This can lead to false ASan reports after longjmp, as the newframe reuses that memory.To avoid this, a call to asan_handle_longjmp() is added tosetjmp_a64.S, which unpoisons the stack range between the currentSP and the old SP (saved during setjmp).Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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libutils: riscv: Update setjmp() and longjmp() for ftrace supportFix the registers saving/restoring conventions. The length of jumpbuffer is increased with one more slot to restore ftrace return s
libutils: riscv: Update setjmp() and longjmp() for ftrace supportFix the registers saving/restoring conventions. The length of jumpbuffer is increased with one more slot to restore ftrace return stack.Signed-off-by: Alvin Chang <alvinga@andestech.com>Acked-by: Jerome Forissier <jerome.forissier@linaro.org>Acked-by: Sumit Garg <sumit.garg@linaro.org>Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
libutils: riscv: provide setjmp_rv.SImplement setjmp() and longjmp() in setjmp_rv.SSigned-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
riscv: create makefiles and directories tree for riscvThis commits creates the very first makefiles, directories andsubdirectories for RISC-V port. It also creates a new platform flavornamed plat
riscv: create makefiles and directories tree for riscvThis commits creates the very first makefiles, directories andsubdirectories for RISC-V port. It also creates a new platform flavornamed plat-spike. Spike is a reference functional RISC-V ISA simulatorwhich provides full system emulation and it is developed alongside theRISC-V toolchain.Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>Acked-by: Jens Wiklander <jens.wiklander@linaro.org>Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>