1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2025 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1-pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 interrupts-extended = 182 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 183 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 191 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 192 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 193 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 198 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 199 <0>, 200 <0>, 201 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 202 <0>, /* EXTI_20 */ 203 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 211 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 212 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 213 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 215 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, 221 <0>, 222 <0>, /* EXTI_40 */ 223 <0>, 224 <0>, 225 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 226 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 227 <0>, 228 <0>, 229 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 230 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 231 <0>, 232 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 233 <0>, 234 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 235 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 236 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, 241 <0>, 242 <0>, /* EXTI_60 */ 243 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 244 <0>, 245 <0>, 246 <0>, 247 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 248 <0>, 249 <0>, 250 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 251 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 252 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 253 <0>, 254 <0>, 255 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 256 }; 257 258 syscfg: syscon@50020000 { 259 compatible = "st,stm32mp157-syscfg", "syscon"; 260 reg = <0x50020000 0x400>; 261 clocks = <&rcc SYSCFG>; 262 }; 263 264 dts: thermal@50028000 { 265 compatible = "st,stm32-thermal"; 266 reg = <0x50028000 0x100>; 267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&rcc TMPSENS>; 269 clock-names = "pclk"; 270 #thermal-sensor-cells = <0>; 271 status = "disabled"; 272 }; 273 274 mdma1: dma-controller@58000000 { 275 compatible = "st,stm32h7-mdma"; 276 reg = <0x58000000 0x1000>; 277 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rcc MDMA>; 279 resets = <&rcc MDMA_R>; 280 #dma-cells = <5>; 281 dma-channels = <32>; 282 dma-requests = <48>; 283 }; 284 285 sdmmc1: mmc@58005000 { 286 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 287 arm,primecell-periphid = <0x00253180>; 288 reg = <0x58005000 0x1000>; 289 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "cmd_irq"; 291 clocks = <&rcc SDMMC1_K>; 292 clock-names = "apb_pclk"; 293 resets = <&rcc SDMMC1_R>; 294 cap-sd-highspeed; 295 cap-mmc-highspeed; 296 max-frequency = <120000000>; 297 status = "disabled"; 298 }; 299 300 sdmmc2: mmc@58007000 { 301 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 302 arm,primecell-periphid = <0x00253180>; 303 reg = <0x58007000 0x1000>; 304 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "cmd_irq"; 306 clocks = <&rcc SDMMC2_K>; 307 clock-names = "apb_pclk"; 308 resets = <&rcc SDMMC2_R>; 309 cap-sd-highspeed; 310 cap-mmc-highspeed; 311 max-frequency = <120000000>; 312 status = "disabled"; 313 }; 314 315 crc1: crc@58009000 { 316 compatible = "st,stm32f7-crc"; 317 reg = <0x58009000 0x400>; 318 clocks = <&rcc CRC1>; 319 status = "disabled"; 320 }; 321 322 usbh_ohci: usb@5800c000 { 323 compatible = "generic-ohci"; 324 reg = <0x5800c000 0x1000>; 325 clocks = <&usbphyc>, <&rcc USBH>; 326 resets = <&rcc USBH_R>; 327 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 usbh_ehci: usb@5800d000 { 332 compatible = "generic-ehci"; 333 reg = <0x5800d000 0x1000>; 334 clocks = <&usbphyc>, <&rcc USBH>; 335 resets = <&rcc USBH_R>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 companion = <&usbh_ohci>; 338 status = "disabled"; 339 }; 340 341 ltdc: display-controller@5a001000 { 342 compatible = "st,stm32-ltdc"; 343 reg = <0x5a001000 0x400>; 344 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc LTDC_PX>; 347 clock-names = "lcd"; 348 resets = <&rcc LTDC_R>; 349 status = "disabled"; 350 351 port { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 }; 356 357 iwdg2: watchdog@5a002000 { 358 compatible = "st,stm32mp1-iwdg"; 359 reg = <0x5a002000 0x400>; 360 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 362 clock-names = "pclk", "lsi"; 363 status = "disabled"; 364 }; 365 366 usbphyc: usbphyc@5a006000 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #clock-cells = <0>; 370 compatible = "st,stm32mp1-usbphyc"; 371 reg = <0x5a006000 0x1000>; 372 clocks = <&rcc USBPHY_K>; 373 resets = <&rcc USBPHY_R>; 374 vdda1v1-supply = <®11>; 375 vdda1v8-supply = <®18>; 376 status = "disabled"; 377 378 usbphyc_port0: usb-phy@0 { 379 #phy-cells = <0>; 380 reg = <0>; 381 }; 382 383 usbphyc_port1: usb-phy@1 { 384 #phy-cells = <1>; 385 reg = <1>; 386 }; 387 }; 388 389 rtc: rtc@5c004000 { 390 compatible = "st,stm32mp1-rtc"; 391 reg = <0x5c004000 0x400>; 392 clocks = <&rcc RTCAPB>, <&rcc RTC>; 393 clock-names = "pclk", "rtc_ck"; 394 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 395 }; 396 397 bsec: efuse@5c005000 { 398 compatible = "st,stm32mp15-bsec"; 399 reg = <0x5c005000 0x400>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 403 cfg0_otp: cfg0_otp@0 { 404 reg = <0x0 0x1>; 405 }; 406 part_number_otp: part_number_otp@4 { 407 reg = <0x4 0x1>; 408 }; 409 monotonic_otp: monotonic_otp@10 { 410 reg = <0x10 0x4>; 411 }; 412 nand_otp: nand_otp@24 { 413 reg = <0x24 0x4>; 414 }; 415 uid_otp: uid_otp@34 { 416 reg = <0x34 0xc>; 417 }; 418 package_otp: package_otp@40 { 419 reg = <0x40 0x4>; 420 }; 421 hw2_otp: hw2_otp@48 { 422 reg = <0x48 0x4>; 423 }; 424 ts_cal1: calib@5c { 425 reg = <0x5c 0x2>; 426 }; 427 ts_cal2: calib@5e { 428 reg = <0x5e 0x2>; 429 }; 430 pkh_otp: pkh_otp@60 { 431 reg = <0x60 0x20>; 432 }; 433 ethernet_mac_address: mac@e4 { 434 reg = <0xe4 0x8>; 435 st,non-secure-otp; 436 }; 437 }; 438 439 tamp: tamp@5c00a000 { 440 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 441 reg = <0x5c00a000 0x400>; 442 clocks = <&rcc RTCAPB>; 443 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 444 st,backup-zones = <10 5 17>; 445 }; 446 447 /* 448 * Break node order to solve dependency probe issue between 449 * pinctrl and exti. 450 */ 451 pinctrl: pinctrl@50002000 { 452 #address-cells = <1>; 453 #size-cells = <1>; 454 compatible = "st,stm32mp157-pinctrl"; 455 ranges = <0 0x50002000 0xa400>; 456 interrupt-parent = <&exti>; 457 st,syscfg = <&exti 0x60 0xff>; 458 459 gpioa: gpio@50002000 { 460 gpio-controller; 461 #gpio-cells = <2>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 reg = <0x0 0x400>; 465 clocks = <&rcc GPIOA>; 466 st,bank-name = "GPIOA"; 467 status = "disabled"; 468 }; 469 470 gpiob: gpio@50003000 { 471 gpio-controller; 472 #gpio-cells = <2>; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 reg = <0x1000 0x400>; 476 clocks = <&rcc GPIOB>; 477 st,bank-name = "GPIOB"; 478 status = "disabled"; 479 }; 480 481 gpioc: gpio@50004000 { 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 reg = <0x2000 0x400>; 487 clocks = <&rcc GPIOC>; 488 st,bank-name = "GPIOC"; 489 status = "disabled"; 490 }; 491 492 gpiod: gpio@50005000 { 493 gpio-controller; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 reg = <0x3000 0x400>; 498 clocks = <&rcc GPIOD>; 499 st,bank-name = "GPIOD"; 500 status = "disabled"; 501 }; 502 503 gpioe: gpio@50006000 { 504 gpio-controller; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 reg = <0x4000 0x400>; 509 clocks = <&rcc GPIOE>; 510 st,bank-name = "GPIOE"; 511 status = "disabled"; 512 }; 513 514 gpiof: gpio@50007000 { 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 reg = <0x5000 0x400>; 520 clocks = <&rcc GPIOF>; 521 st,bank-name = "GPIOF"; 522 status = "disabled"; 523 }; 524 525 gpiog: gpio@50008000 { 526 gpio-controller; 527 #gpio-cells = <2>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 reg = <0x6000 0x400>; 531 clocks = <&rcc GPIOG>; 532 st,bank-name = "GPIOG"; 533 status = "disabled"; 534 }; 535 536 gpioh: gpio@50009000 { 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 reg = <0x7000 0x400>; 542 clocks = <&rcc GPIOH>; 543 st,bank-name = "GPIOH"; 544 status = "disabled"; 545 }; 546 547 gpioi: gpio@5000a000 { 548 gpio-controller; 549 #gpio-cells = <2>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 reg = <0x8000 0x400>; 553 clocks = <&rcc GPIOI>; 554 st,bank-name = "GPIOI"; 555 status = "disabled"; 556 }; 557 558 gpioj: gpio@5000b000 { 559 gpio-controller; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 reg = <0x9000 0x400>; 564 clocks = <&rcc GPIOJ>; 565 st,bank-name = "GPIOJ"; 566 status = "disabled"; 567 }; 568 569 gpiok: gpio@5000c000 { 570 gpio-controller; 571 #gpio-cells = <2>; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 reg = <0xa000 0x400>; 575 clocks = <&rcc GPIOK>; 576 st,bank-name = "GPIOK"; 577 status = "disabled"; 578 }; 579 }; 580 581 pinctrl_z: pinctrl@54004000 { 582 #address-cells = <1>; 583 #size-cells = <1>; 584 compatible = "st,stm32mp157-z-pinctrl"; 585 ranges = <0 0x54004000 0x400>; 586 interrupt-parent = <&exti>; 587 st,syscfg = <&exti 0x60 0xff>; 588 589 gpioz: gpio@54004000 { 590 gpio-controller; 591 #gpio-cells = <2>; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 #access-controller-cells = <1>; 595 reg = <0 0x400>; 596 clocks = <&rcc GPIOZ>; 597 st,bank-name = "GPIOZ"; 598 st,bank-ioport = <11>; 599 status = "disabled"; 600 }; 601 }; 602 603 tzc400: tzc@5c006000 { 604 compatible = "st,stm32mp1-tzc"; 605 reg = <0x5c006000 0x1000>; 606 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&rcc TZC1>, <&rcc TZC2>; 608 st,mem-map = <0xc0000000 0x40000000>; 609 }; 610 611 etzpc: etzpc@5c007000 { 612 compatible = "st,stm32-etzpc", "simple-bus"; 613 reg = <0x5C007000 0x400>; 614 clocks = <&rcc TZPC>; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 #access-controller-cells = <1>; 618 619 timers2: timer@40000000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "st,stm32-timers"; 623 reg = <0x40000000 0x400>; 624 clocks = <&rcc TIM2_K>; 625 clock-names = "int"; 626 dmas = <&dmamux1 18 0x400 0x1>, 627 <&dmamux1 19 0x400 0x1>, 628 <&dmamux1 20 0x400 0x1>, 629 <&dmamux1 21 0x400 0x1>, 630 <&dmamux1 22 0x400 0x1>; 631 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 632 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 633 status = "disabled"; 634 635 pwm { 636 compatible = "st,stm32-pwm"; 637 #pwm-cells = <3>; 638 status = "disabled"; 639 }; 640 641 timer@1 { 642 compatible = "st,stm32h7-timer-trigger"; 643 reg = <1>; 644 status = "disabled"; 645 }; 646 647 counter { 648 compatible = "st,stm32-timer-counter"; 649 status = "disabled"; 650 }; 651 }; 652 653 timers3: timer@40001000 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 compatible = "st,stm32-timers"; 657 reg = <0x40001000 0x400>; 658 clocks = <&rcc TIM3_K>; 659 clock-names = "int"; 660 dmas = <&dmamux1 23 0x400 0x1>, 661 <&dmamux1 24 0x400 0x1>, 662 <&dmamux1 25 0x400 0x1>, 663 <&dmamux1 26 0x400 0x1>, 664 <&dmamux1 27 0x400 0x1>, 665 <&dmamux1 28 0x400 0x1>; 666 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 667 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 668 status = "disabled"; 669 670 pwm { 671 compatible = "st,stm32-pwm"; 672 #pwm-cells = <3>; 673 status = "disabled"; 674 }; 675 676 timer@2 { 677 compatible = "st,stm32h7-timer-trigger"; 678 reg = <2>; 679 status = "disabled"; 680 }; 681 682 counter { 683 compatible = "st,stm32-timer-counter"; 684 status = "disabled"; 685 }; 686 }; 687 688 timers4: timer@40002000 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 compatible = "st,stm32-timers"; 692 reg = <0x40002000 0x400>; 693 clocks = <&rcc TIM4_K>; 694 clock-names = "int"; 695 dmas = <&dmamux1 29 0x400 0x1>, 696 <&dmamux1 30 0x400 0x1>, 697 <&dmamux1 31 0x400 0x1>, 698 <&dmamux1 32 0x400 0x1>; 699 dma-names = "ch1", "ch2", "ch3", "ch4"; 700 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 701 status = "disabled"; 702 703 pwm { 704 compatible = "st,stm32-pwm"; 705 #pwm-cells = <3>; 706 status = "disabled"; 707 }; 708 709 timer@3 { 710 compatible = "st,stm32h7-timer-trigger"; 711 reg = <3>; 712 status = "disabled"; 713 }; 714 715 counter { 716 compatible = "st,stm32-timer-counter"; 717 status = "disabled"; 718 }; 719 }; 720 721 timers5: timer@40003000 { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 compatible = "st,stm32-timers"; 725 reg = <0x40003000 0x400>; 726 clocks = <&rcc TIM5_K>; 727 clock-names = "int"; 728 dmas = <&dmamux1 55 0x400 0x1>, 729 <&dmamux1 56 0x400 0x1>, 730 <&dmamux1 57 0x400 0x1>, 731 <&dmamux1 58 0x400 0x1>, 732 <&dmamux1 59 0x400 0x1>, 733 <&dmamux1 60 0x400 0x1>; 734 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 735 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 736 status = "disabled"; 737 738 pwm { 739 compatible = "st,stm32-pwm"; 740 #pwm-cells = <3>; 741 status = "disabled"; 742 }; 743 744 timer@4 { 745 compatible = "st,stm32h7-timer-trigger"; 746 reg = <4>; 747 status = "disabled"; 748 }; 749 750 counter { 751 compatible = "st,stm32-timer-counter"; 752 status = "disabled"; 753 }; 754 }; 755 756 timers6: timer@40004000 { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 compatible = "st,stm32-timers"; 760 reg = <0x40004000 0x400>; 761 clocks = <&rcc TIM6_K>; 762 clock-names = "int"; 763 dmas = <&dmamux1 69 0x400 0x1>; 764 dma-names = "up"; 765 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 766 status = "disabled"; 767 768 timer@5 { 769 compatible = "st,stm32h7-timer-trigger"; 770 reg = <5>; 771 status = "disabled"; 772 }; 773 }; 774 775 timers7: timer@40005000 { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 compatible = "st,stm32-timers"; 779 reg = <0x40005000 0x400>; 780 clocks = <&rcc TIM7_K>; 781 clock-names = "int"; 782 dmas = <&dmamux1 70 0x400 0x1>; 783 dma-names = "up"; 784 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 785 status = "disabled"; 786 787 timer@6 { 788 compatible = "st,stm32h7-timer-trigger"; 789 reg = <6>; 790 status = "disabled"; 791 }; 792 }; 793 794 timers12: timer@40006000 { 795 #address-cells = <1>; 796 #size-cells = <0>; 797 compatible = "st,stm32-timers"; 798 reg = <0x40006000 0x400>; 799 clocks = <&rcc TIM12_K>; 800 clock-names = "int"; 801 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 802 status = "disabled"; 803 804 pwm { 805 compatible = "st,stm32-pwm"; 806 #pwm-cells = <3>; 807 status = "disabled"; 808 }; 809 810 timer@11 { 811 compatible = "st,stm32h7-timer-trigger"; 812 reg = <11>; 813 status = "disabled"; 814 }; 815 }; 816 817 timers13: timer@40007000 { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 compatible = "st,stm32-timers"; 821 reg = <0x40007000 0x400>; 822 clocks = <&rcc TIM13_K>; 823 clock-names = "int"; 824 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 825 status = "disabled"; 826 827 pwm { 828 compatible = "st,stm32-pwm"; 829 #pwm-cells = <3>; 830 status = "disabled"; 831 }; 832 833 timer@12 { 834 compatible = "st,stm32h7-timer-trigger"; 835 reg = <12>; 836 status = "disabled"; 837 }; 838 }; 839 840 timers14: timer@40008000 { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 compatible = "st,stm32-timers"; 844 reg = <0x40008000 0x400>; 845 clocks = <&rcc TIM14_K>; 846 clock-names = "int"; 847 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 848 status = "disabled"; 849 850 pwm { 851 compatible = "st,stm32-pwm"; 852 #pwm-cells = <3>; 853 status = "disabled"; 854 }; 855 856 timer@13 { 857 compatible = "st,stm32h7-timer-trigger"; 858 reg = <13>; 859 status = "disabled"; 860 }; 861 }; 862 863 lptimer1: timer@40009000 { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 compatible = "st,stm32-lptimer"; 867 reg = <0x40009000 0x400>; 868 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&rcc LPTIM1_K>; 870 clock-names = "mux"; 871 wakeup-source; 872 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 873 status = "disabled"; 874 875 pwm { 876 compatible = "st,stm32-pwm-lp"; 877 #pwm-cells = <3>; 878 status = "disabled"; 879 }; 880 881 trigger@0 { 882 compatible = "st,stm32-lptimer-trigger"; 883 reg = <0>; 884 status = "disabled"; 885 }; 886 887 counter { 888 compatible = "st,stm32-lptimer-counter"; 889 status = "disabled"; 890 }; 891 }; 892 893 spi2: spi@4000b000 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 compatible = "st,stm32h7-spi"; 897 reg = <0x4000b000 0x400>; 898 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&rcc SPI2_K>; 900 resets = <&rcc SPI2_R>; 901 dmas = <&dmamux1 39 0x400 0x05>, 902 <&dmamux1 40 0x400 0x05>; 903 dma-names = "rx", "tx"; 904 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 905 status = "disabled"; 906 }; 907 908 i2s2: audio-controller@4000b000 { 909 compatible = "st,stm32h7-i2s"; 910 #sound-dai-cells = <0>; 911 reg = <0x4000b000 0x400>; 912 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 913 dmas = <&dmamux1 39 0x400 0x01>, 914 <&dmamux1 40 0x400 0x01>; 915 dma-names = "rx", "tx"; 916 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 917 status = "disabled"; 918 }; 919 920 spi3: spi@4000c000 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 compatible = "st,stm32h7-spi"; 924 reg = <0x4000c000 0x400>; 925 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&rcc SPI3_K>; 927 resets = <&rcc SPI3_R>; 928 dmas = <&dmamux1 61 0x400 0x05>, 929 <&dmamux1 62 0x400 0x05>; 930 dma-names = "rx", "tx"; 931 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 932 status = "disabled"; 933 }; 934 935 i2s3: audio-controller@4000c000 { 936 compatible = "st,stm32h7-i2s"; 937 #sound-dai-cells = <0>; 938 reg = <0x4000c000 0x400>; 939 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 940 dmas = <&dmamux1 61 0x400 0x01>, 941 <&dmamux1 62 0x400 0x01>; 942 dma-names = "rx", "tx"; 943 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 944 status = "disabled"; 945 }; 946 947 spdifrx: audio-controller@4000d000 { 948 compatible = "st,stm32h7-spdifrx"; 949 #sound-dai-cells = <0>; 950 reg = <0x4000d000 0x400>; 951 clocks = <&rcc SPDIF_K>; 952 clock-names = "kclk"; 953 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 954 dmas = <&dmamux1 93 0x400 0x01>, 955 <&dmamux1 94 0x400 0x01>; 956 dma-names = "rx", "rx-ctrl"; 957 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 958 status = "disabled"; 959 }; 960 961 usart2: serial@4000e000 { 962 compatible = "st,stm32h7-uart"; 963 reg = <0x4000e000 0x400>; 964 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&rcc USART2_K>; 966 wakeup-source; 967 dmas = <&dmamux1 43 0x400 0x15>, 968 <&dmamux1 44 0x400 0x11>; 969 dma-names = "rx", "tx"; 970 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 971 status = "disabled"; 972 }; 973 974 usart3: serial@4000f000 { 975 compatible = "st,stm32h7-uart"; 976 reg = <0x4000f000 0x400>; 977 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&rcc USART3_K>; 979 wakeup-source; 980 dmas = <&dmamux1 45 0x400 0x15>, 981 <&dmamux1 46 0x400 0x11>; 982 dma-names = "rx", "tx"; 983 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 984 status = "disabled"; 985 }; 986 987 uart4: serial@40010000 { 988 compatible = "st,stm32h7-uart"; 989 reg = <0x40010000 0x400>; 990 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&rcc UART4_K>; 992 wakeup-source; 993 dmas = <&dmamux1 63 0x400 0x15>, 994 <&dmamux1 64 0x400 0x11>; 995 dma-names = "rx", "tx"; 996 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 997 status = "disabled"; 998 }; 999 1000 uart5: serial@40011000 { 1001 compatible = "st,stm32h7-uart"; 1002 reg = <0x40011000 0x400>; 1003 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&rcc UART5_K>; 1005 wakeup-source; 1006 dmas = <&dmamux1 65 0x400 0x15>, 1007 <&dmamux1 66 0x400 0x11>; 1008 dma-names = "rx", "tx"; 1009 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 1010 status = "disabled"; 1011 }; 1012 1013 i2c1: i2c@40012000 { 1014 compatible = "st,stm32mp15-i2c"; 1015 reg = <0x40012000 0x400>; 1016 interrupt-names = "event", "error"; 1017 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&rcc I2C1_K>; 1020 resets = <&rcc I2C1_R>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 st,syscfg-fmp = <&syscfg 0x4 0x1>; 1024 wakeup-source; 1025 i2c-analog-filter; 1026 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 1027 status = "disabled"; 1028 }; 1029 1030 i2c2: i2c@40013000 { 1031 compatible = "st,stm32mp15-i2c"; 1032 reg = <0x40013000 0x400>; 1033 interrupt-names = "event", "error"; 1034 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&rcc I2C2_K>; 1037 resets = <&rcc I2C2_R>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 st,syscfg-fmp = <&syscfg 0x4 0x2>; 1041 wakeup-source; 1042 i2c-analog-filter; 1043 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c3: i2c@40014000 { 1048 compatible = "st,stm32mp15-i2c"; 1049 reg = <0x40014000 0x400>; 1050 interrupt-names = "event", "error"; 1051 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&rcc I2C3_K>; 1054 resets = <&rcc I2C3_R>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1058 wakeup-source; 1059 i2c-analog-filter; 1060 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 1061 status = "disabled"; 1062 }; 1063 1064 i2c5: i2c@40015000 { 1065 compatible = "st,stm32mp15-i2c"; 1066 reg = <0x40015000 0x400>; 1067 interrupt-names = "event", "error"; 1068 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&rcc I2C5_K>; 1071 resets = <&rcc I2C5_R>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1075 wakeup-source; 1076 i2c-analog-filter; 1077 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1078 status = "disabled"; 1079 }; 1080 1081 cec: cec@40016000 { 1082 compatible = "st,stm32-cec"; 1083 reg = <0x40016000 0x400>; 1084 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&rcc CEC_K>, <&rcc CEC>; 1086 clock-names = "cec", "hdmi-cec"; 1087 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1088 status = "disabled"; 1089 }; 1090 1091 dac: dac@40017000 { 1092 compatible = "st,stm32h7-dac-core"; 1093 reg = <0x40017000 0x400>; 1094 clocks = <&rcc DAC12>; 1095 clock-names = "pclk"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1099 status = "disabled"; 1100 1101 dac1: dac@1 { 1102 compatible = "st,stm32-dac"; 1103 #io-channel-cells = <1>; 1104 reg = <1>; 1105 status = "disabled"; 1106 }; 1107 1108 dac2: dac@2 { 1109 compatible = "st,stm32-dac"; 1110 #io-channel-cells = <1>; 1111 reg = <2>; 1112 status = "disabled"; 1113 }; 1114 }; 1115 1116 uart7: serial@40018000 { 1117 compatible = "st,stm32h7-uart"; 1118 reg = <0x40018000 0x400>; 1119 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&rcc UART7_K>; 1121 wakeup-source; 1122 dmas = <&dmamux1 79 0x400 0x15>, 1123 <&dmamux1 80 0x400 0x11>; 1124 dma-names = "rx", "tx"; 1125 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1126 status = "disabled"; 1127 }; 1128 1129 uart8: serial@40019000 { 1130 compatible = "st,stm32h7-uart"; 1131 reg = <0x40019000 0x400>; 1132 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&rcc UART8_K>; 1134 wakeup-source; 1135 dmas = <&dmamux1 81 0x400 0x15>, 1136 <&dmamux1 82 0x400 0x11>; 1137 dma-names = "rx", "tx"; 1138 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1139 status = "disabled"; 1140 }; 1141 1142 timers1: timer@44000000 { 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 compatible = "st,stm32-timers"; 1146 reg = <0x44000000 0x400>; 1147 clocks = <&rcc TIM1_K>; 1148 clock-names = "int"; 1149 dmas = <&dmamux1 11 0x400 0x1>, 1150 <&dmamux1 12 0x400 0x1>, 1151 <&dmamux1 13 0x400 0x1>, 1152 <&dmamux1 14 0x400 0x1>, 1153 <&dmamux1 15 0x400 0x1>, 1154 <&dmamux1 16 0x400 0x1>, 1155 <&dmamux1 17 0x400 0x1>; 1156 dma-names = "ch1", "ch2", "ch3", "ch4", 1157 "up", "trig", "com"; 1158 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1159 status = "disabled"; 1160 1161 pwm { 1162 compatible = "st,stm32-pwm"; 1163 #pwm-cells = <3>; 1164 status = "disabled"; 1165 }; 1166 1167 timer@0 { 1168 compatible = "st,stm32h7-timer-trigger"; 1169 reg = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 counter { 1174 compatible = "st,stm32-timer-counter"; 1175 status = "disabled"; 1176 }; 1177 }; 1178 1179 timers8: timer@44001000 { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 compatible = "st,stm32-timers"; 1183 reg = <0x44001000 0x400>; 1184 clocks = <&rcc TIM8_K>; 1185 clock-names = "int"; 1186 dmas = <&dmamux1 47 0x400 0x1>, 1187 <&dmamux1 48 0x400 0x1>, 1188 <&dmamux1 49 0x400 0x1>, 1189 <&dmamux1 50 0x400 0x1>, 1190 <&dmamux1 51 0x400 0x1>, 1191 <&dmamux1 52 0x400 0x1>, 1192 <&dmamux1 53 0x400 0x1>; 1193 dma-names = "ch1", "ch2", "ch3", "ch4", 1194 "up", "trig", "com"; 1195 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1196 status = "disabled"; 1197 1198 pwm { 1199 compatible = "st,stm32-pwm"; 1200 #pwm-cells = <3>; 1201 status = "disabled"; 1202 }; 1203 1204 timer@7 { 1205 compatible = "st,stm32h7-timer-trigger"; 1206 reg = <7>; 1207 status = "disabled"; 1208 }; 1209 1210 counter { 1211 compatible = "st,stm32-timer-counter"; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 usart6: serial@44003000 { 1217 compatible = "st,stm32h7-uart"; 1218 reg = <0x44003000 0x400>; 1219 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&rcc USART6_K>; 1221 wakeup-source; 1222 dmas = <&dmamux1 71 0x400 0x15>, 1223 <&dmamux1 72 0x400 0x11>; 1224 dma-names = "rx", "tx"; 1225 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1226 status = "disabled"; 1227 }; 1228 1229 spi1: spi@44004000 { 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 compatible = "st,stm32h7-spi"; 1233 reg = <0x44004000 0x400>; 1234 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&rcc SPI1_K>; 1236 resets = <&rcc SPI1_R>; 1237 dmas = <&dmamux1 37 0x400 0x05>, 1238 <&dmamux1 38 0x400 0x05>; 1239 dma-names = "rx", "tx"; 1240 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1241 status = "disabled"; 1242 }; 1243 1244 i2s1: audio-controller@44004000 { 1245 compatible = "st,stm32h7-i2s"; 1246 #sound-dai-cells = <0>; 1247 reg = <0x44004000 0x400>; 1248 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1249 dmas = <&dmamux1 37 0x400 0x01>, 1250 <&dmamux1 38 0x400 0x01>; 1251 dma-names = "rx", "tx"; 1252 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1253 status = "disabled"; 1254 }; 1255 1256 spi4: spi@44005000 { 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 compatible = "st,stm32h7-spi"; 1260 reg = <0x44005000 0x400>; 1261 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&rcc SPI4_K>; 1263 resets = <&rcc SPI4_R>; 1264 dmas = <&dmamux1 83 0x400 0x05>, 1265 <&dmamux1 84 0x400 0x05>; 1266 dma-names = "rx", "tx"; 1267 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1268 status = "disabled"; 1269 }; 1270 1271 timers15: timer@44006000 { 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 compatible = "st,stm32-timers"; 1275 reg = <0x44006000 0x400>; 1276 clocks = <&rcc TIM15_K>; 1277 clock-names = "int"; 1278 dmas = <&dmamux1 105 0x400 0x1>, 1279 <&dmamux1 106 0x400 0x1>, 1280 <&dmamux1 107 0x400 0x1>, 1281 <&dmamux1 108 0x400 0x1>; 1282 dma-names = "ch1", "up", "trig", "com"; 1283 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1284 status = "disabled"; 1285 1286 pwm { 1287 compatible = "st,stm32-pwm"; 1288 #pwm-cells = <3>; 1289 status = "disabled"; 1290 }; 1291 1292 timer@14 { 1293 compatible = "st,stm32h7-timer-trigger"; 1294 reg = <14>; 1295 status = "disabled"; 1296 }; 1297 }; 1298 1299 timers16: timer@44007000 { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 compatible = "st,stm32-timers"; 1303 reg = <0x44007000 0x400>; 1304 clocks = <&rcc TIM16_K>; 1305 clock-names = "int"; 1306 dmas = <&dmamux1 109 0x400 0x1>, 1307 <&dmamux1 110 0x400 0x1>; 1308 dma-names = "ch1", "up"; 1309 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1310 status = "disabled"; 1311 1312 pwm { 1313 compatible = "st,stm32-pwm"; 1314 #pwm-cells = <3>; 1315 status = "disabled"; 1316 }; 1317 timer@15 { 1318 compatible = "st,stm32h7-timer-trigger"; 1319 reg = <15>; 1320 status = "disabled"; 1321 }; 1322 }; 1323 1324 timers17: timer@44008000 { 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 compatible = "st,stm32-timers"; 1328 reg = <0x44008000 0x400>; 1329 clocks = <&rcc TIM17_K>; 1330 clock-names = "int"; 1331 dmas = <&dmamux1 111 0x400 0x1>, 1332 <&dmamux1 112 0x400 0x1>; 1333 dma-names = "ch1", "up"; 1334 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1335 status = "disabled"; 1336 1337 pwm { 1338 compatible = "st,stm32-pwm"; 1339 #pwm-cells = <3>; 1340 status = "disabled"; 1341 }; 1342 1343 timer@16 { 1344 compatible = "st,stm32h7-timer-trigger"; 1345 reg = <16>; 1346 status = "disabled"; 1347 }; 1348 }; 1349 1350 spi5: spi@44009000 { 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 compatible = "st,stm32h7-spi"; 1354 reg = <0x44009000 0x400>; 1355 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1356 clocks = <&rcc SPI5_K>; 1357 resets = <&rcc SPI5_R>; 1358 dmas = <&dmamux1 85 0x400 0x05>, 1359 <&dmamux1 86 0x400 0x05>; 1360 dma-names = "rx", "tx"; 1361 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1362 status = "disabled"; 1363 }; 1364 1365 sai1: sai@4400a000 { 1366 compatible = "st,stm32h7-sai"; 1367 #address-cells = <1>; 1368 #size-cells = <1>; 1369 ranges = <0 0x4400a000 0x400>; 1370 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1371 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1372 resets = <&rcc SAI1_R>; 1373 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1374 status = "disabled"; 1375 1376 sai1a: audio-controller@4400a004 { 1377 #sound-dai-cells = <0>; 1378 1379 compatible = "st,stm32-sai-sub-a"; 1380 reg = <0x4 0x20>; 1381 clocks = <&rcc SAI1_K>; 1382 clock-names = "sai_ck"; 1383 dmas = <&dmamux1 87 0x400 0x01>; 1384 status = "disabled"; 1385 }; 1386 1387 sai1b: audio-controller@4400a024 { 1388 #sound-dai-cells = <0>; 1389 compatible = "st,stm32-sai-sub-b"; 1390 reg = <0x24 0x20>; 1391 clocks = <&rcc SAI1_K>; 1392 clock-names = "sai_ck"; 1393 dmas = <&dmamux1 88 0x400 0x01>; 1394 status = "disabled"; 1395 }; 1396 }; 1397 1398 sai2: sai@4400b000 { 1399 compatible = "st,stm32h7-sai"; 1400 #address-cells = <1>; 1401 #size-cells = <1>; 1402 ranges = <0 0x4400b000 0x400>; 1403 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1404 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1405 resets = <&rcc SAI2_R>; 1406 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1407 status = "disabled"; 1408 1409 sai2a: audio-controller@4400b004 { 1410 #sound-dai-cells = <0>; 1411 compatible = "st,stm32-sai-sub-a"; 1412 reg = <0x4 0x20>; 1413 clocks = <&rcc SAI2_K>; 1414 clock-names = "sai_ck"; 1415 dmas = <&dmamux1 89 0x400 0x01>; 1416 status = "disabled"; 1417 }; 1418 1419 sai2b: audio-controller@4400b024 { 1420 #sound-dai-cells = <0>; 1421 compatible = "st,stm32-sai-sub-b"; 1422 reg = <0x24 0x20>; 1423 clocks = <&rcc SAI2_K>; 1424 clock-names = "sai_ck"; 1425 dmas = <&dmamux1 90 0x400 0x01>; 1426 status = "disabled"; 1427 }; 1428 }; 1429 1430 sai3: sai@4400c000 { 1431 compatible = "st,stm32h7-sai"; 1432 #address-cells = <1>; 1433 #size-cells = <1>; 1434 ranges = <0 0x4400c000 0x400>; 1435 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1436 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1437 resets = <&rcc SAI3_R>; 1438 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1439 status = "disabled"; 1440 1441 sai3a: audio-controller@4400c004 { 1442 #sound-dai-cells = <0>; 1443 compatible = "st,stm32-sai-sub-a"; 1444 reg = <0x04 0x20>; 1445 clocks = <&rcc SAI3_K>; 1446 clock-names = "sai_ck"; 1447 dmas = <&dmamux1 113 0x400 0x01>; 1448 status = "disabled"; 1449 }; 1450 1451 sai3b: audio-controller@4400c024 { 1452 #sound-dai-cells = <0>; 1453 compatible = "st,stm32-sai-sub-b"; 1454 reg = <0x24 0x20>; 1455 clocks = <&rcc SAI3_K>; 1456 clock-names = "sai_ck"; 1457 dmas = <&dmamux1 114 0x400 0x01>; 1458 status = "disabled"; 1459 }; 1460 }; 1461 1462 dfsdm: dfsdm@4400d000 { 1463 compatible = "st,stm32mp1-dfsdm"; 1464 reg = <0x4400d000 0x800>; 1465 clocks = <&rcc DFSDM_K>; 1466 clock-names = "dfsdm"; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1470 status = "disabled"; 1471 1472 dfsdm0: filter@0 { 1473 compatible = "st,stm32-dfsdm-adc"; 1474 #io-channel-cells = <1>; 1475 reg = <0>; 1476 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1477 dmas = <&dmamux1 101 0x400 0x01>; 1478 dma-names = "rx"; 1479 status = "disabled"; 1480 }; 1481 1482 dfsdm1: filter@1 { 1483 compatible = "st,stm32-dfsdm-adc"; 1484 #io-channel-cells = <1>; 1485 reg = <1>; 1486 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1487 dmas = <&dmamux1 102 0x400 0x01>; 1488 dma-names = "rx"; 1489 status = "disabled"; 1490 }; 1491 1492 dfsdm2: filter@2 { 1493 compatible = "st,stm32-dfsdm-adc"; 1494 #io-channel-cells = <1>; 1495 reg = <2>; 1496 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1497 dmas = <&dmamux1 103 0x400 0x01>; 1498 dma-names = "rx"; 1499 status = "disabled"; 1500 }; 1501 1502 dfsdm3: filter@3 { 1503 compatible = "st,stm32-dfsdm-adc"; 1504 #io-channel-cells = <1>; 1505 reg = <3>; 1506 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1507 dmas = <&dmamux1 104 0x400 0x01>; 1508 dma-names = "rx"; 1509 status = "disabled"; 1510 }; 1511 1512 dfsdm4: filter@4 { 1513 compatible = "st,stm32-dfsdm-adc"; 1514 #io-channel-cells = <1>; 1515 reg = <4>; 1516 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1517 dmas = <&dmamux1 91 0x400 0x01>; 1518 dma-names = "rx"; 1519 status = "disabled"; 1520 }; 1521 1522 dfsdm5: filter@5 { 1523 compatible = "st,stm32-dfsdm-adc"; 1524 #io-channel-cells = <1>; 1525 reg = <5>; 1526 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&dmamux1 92 0x400 0x01>; 1528 dma-names = "rx"; 1529 status = "disabled"; 1530 }; 1531 }; 1532 1533 dma1: dma-controller@48000000 { 1534 compatible = "st,stm32-dma"; 1535 reg = <0x48000000 0x400>; 1536 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&rcc DMA1>; 1545 resets = <&rcc DMA1_R>; 1546 #dma-cells = <4>; 1547 st,mem2mem; 1548 dma-requests = <8>; 1549 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1550 status = "disabled"; 1551 }; 1552 1553 dma2: dma-controller@48001000 { 1554 compatible = "st,stm32-dma"; 1555 reg = <0x48001000 0x400>; 1556 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&rcc DMA2>; 1565 resets = <&rcc DMA2_R>; 1566 #dma-cells = <4>; 1567 st,mem2mem; 1568 dma-requests = <8>; 1569 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1570 status = "disabled"; 1571 }; 1572 1573 dmamux1: dma-router@48002000 { 1574 compatible = "st,stm32h7-dmamux"; 1575 reg = <0x48002000 0x40>; 1576 #dma-cells = <3>; 1577 dma-requests = <128>; 1578 dma-masters = <&dma1 &dma2>; 1579 dma-channels = <16>; 1580 clocks = <&rcc DMAMUX>; 1581 resets = <&rcc DMAMUX_R>; 1582 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1583 status = "disabled"; 1584 }; 1585 1586 adc: adc@48003000 { 1587 compatible = "st,stm32mp1-adc-core"; 1588 reg = <0x48003000 0x400>; 1589 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1592 clock-names = "bus", "adc"; 1593 interrupt-controller; 1594 st,syscfg = <&syscfg>; 1595 #interrupt-cells = <1>; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1599 status = "disabled"; 1600 1601 adc1: adc@0 { 1602 compatible = "st,stm32mp1-adc"; 1603 #io-channel-cells = <1>; 1604 reg = <0x0>; 1605 interrupt-parent = <&adc>; 1606 interrupts = <0>; 1607 dmas = <&dmamux1 9 0x400 0x01>; 1608 dma-names = "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 adc2: adc@100 { 1613 compatible = "st,stm32mp1-adc"; 1614 #io-channel-cells = <1>; 1615 reg = <0x100>; 1616 interrupt-parent = <&adc>; 1617 interrupts = <1>; 1618 dmas = <&dmamux1 10 0x400 0x01>; 1619 dma-names = "rx"; 1620 status = "disabled"; 1621 }; 1622 }; 1623 1624 sdmmc3: mmc@48004000 { 1625 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1626 arm,primecell-periphid = <0x00253180>; 1627 reg = <0x48004000 0x400>; 1628 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1629 interrupt-names = "cmd_irq"; 1630 clocks = <&rcc SDMMC3_K>; 1631 clock-names = "apb_pclk"; 1632 resets = <&rcc SDMMC3_R>; 1633 cap-sd-highspeed; 1634 cap-mmc-highspeed; 1635 max-frequency = <120000000>; 1636 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1637 status = "disabled"; 1638 }; 1639 1640 usbotg_hs: usb-otg@49000000 { 1641 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1642 reg = <0x49000000 0x10000>; 1643 clocks = <&rcc USBO_K>; 1644 clock-names = "otg"; 1645 resets = <&rcc USBO_R>; 1646 reset-names = "dwc2"; 1647 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1648 g-rx-fifo-size = <512>; 1649 g-np-tx-fifo-size = <32>; 1650 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1651 dr_mode = "otg"; 1652 otg-rev = <0x200>; 1653 usb33d-supply = <&usb33>; 1654 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1655 status = "disabled"; 1656 }; 1657 1658 dcmi: dcmi@4c006000 { 1659 compatible = "st,stm32-dcmi"; 1660 reg = <0x4c006000 0x400>; 1661 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1662 resets = <&rcc CAMITF_R>; 1663 clocks = <&rcc DCMI>; 1664 clock-names = "mclk"; 1665 dmas = <&dmamux1 75 0x400 0x01>; 1666 dma-names = "tx"; 1667 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1668 status = "disabled"; 1669 }; 1670 1671 lptimer2: timer@50021000 { 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 compatible = "st,stm32-lptimer"; 1675 reg = <0x50021000 0x400>; 1676 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1677 clocks = <&rcc LPTIM2_K>; 1678 clock-names = "mux"; 1679 wakeup-source; 1680 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1681 status = "disabled"; 1682 1683 pwm { 1684 compatible = "st,stm32-pwm-lp"; 1685 #pwm-cells = <3>; 1686 status = "disabled"; 1687 }; 1688 1689 trigger@1 { 1690 compatible = "st,stm32-lptimer-trigger"; 1691 reg = <1>; 1692 status = "disabled"; 1693 }; 1694 1695 counter { 1696 compatible = "st,stm32-lptimer-counter"; 1697 status = "disabled"; 1698 }; 1699 }; 1700 1701 lptimer3: timer@50022000 { 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 compatible = "st,stm32-lptimer"; 1705 reg = <0x50022000 0x400>; 1706 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1707 clocks = <&rcc LPTIM3_K>; 1708 clock-names = "mux"; 1709 wakeup-source; 1710 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1711 status = "disabled"; 1712 1713 pwm { 1714 compatible = "st,stm32-pwm-lp"; 1715 #pwm-cells = <3>; 1716 status = "disabled"; 1717 }; 1718 1719 trigger@2 { 1720 compatible = "st,stm32-lptimer-trigger"; 1721 reg = <2>; 1722 status = "disabled"; 1723 }; 1724 }; 1725 1726 lptimer4: timer@50023000 { 1727 compatible = "st,stm32-lptimer"; 1728 reg = <0x50023000 0x400>; 1729 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1730 clocks = <&rcc LPTIM4_K>; 1731 clock-names = "mux"; 1732 wakeup-source; 1733 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1734 status = "disabled"; 1735 1736 pwm { 1737 compatible = "st,stm32-pwm-lp"; 1738 #pwm-cells = <3>; 1739 status = "disabled"; 1740 }; 1741 }; 1742 1743 lptimer5: timer@50024000 { 1744 compatible = "st,stm32-lptimer"; 1745 reg = <0x50024000 0x400>; 1746 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1747 clocks = <&rcc LPTIM5_K>; 1748 clock-names = "mux"; 1749 wakeup-source; 1750 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1751 status = "disabled"; 1752 1753 pwm { 1754 compatible = "st,stm32-pwm-lp"; 1755 #pwm-cells = <3>; 1756 status = "disabled"; 1757 }; 1758 }; 1759 1760 vrefbuf: vrefbuf@50025000 { 1761 compatible = "st,stm32-vrefbuf"; 1762 reg = <0x50025000 0x8>; 1763 regulator-min-microvolt = <1500000>; 1764 regulator-max-microvolt = <2500000>; 1765 clocks = <&rcc VREF>; 1766 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1767 status = "disabled"; 1768 }; 1769 1770 sai4: sai@50027000 { 1771 compatible = "st,stm32h7-sai"; 1772 #address-cells = <1>; 1773 #size-cells = <1>; 1774 ranges = <0 0x50027000 0x400>; 1775 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1776 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1777 resets = <&rcc SAI4_R>; 1778 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1779 status = "disabled"; 1780 1781 sai4a: audio-controller@50027004 { 1782 #sound-dai-cells = <0>; 1783 compatible = "st,stm32-sai-sub-a"; 1784 reg = <0x04 0x20>; 1785 clocks = <&rcc SAI4_K>; 1786 clock-names = "sai_ck"; 1787 dmas = <&dmamux1 99 0x400 0x01>; 1788 status = "disabled"; 1789 }; 1790 1791 sai4b: audio-controller@50027024 { 1792 #sound-dai-cells = <0>; 1793 compatible = "st,stm32-sai-sub-b"; 1794 reg = <0x24 0x20>; 1795 clocks = <&rcc SAI4_K>; 1796 clock-names = "sai_ck"; 1797 dmas = <&dmamux1 100 0x400 0x01>; 1798 status = "disabled"; 1799 }; 1800 }; 1801 1802 hash1: hash@54002000 { 1803 compatible = "st,stm32f756-hash"; 1804 reg = <0x54002000 0x400>; 1805 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1806 clocks = <&rcc HASH1>; 1807 resets = <&rcc HASH1_R>; 1808 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1809 dma-names = "in"; 1810 dma-maxburst = <2>; 1811 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1812 status = "disabled"; 1813 }; 1814 1815 rng1: rng@54003000 { 1816 compatible = "st,stm32-rng"; 1817 reg = <0x54003000 0x400>; 1818 clocks = <&rcc RNG1_K>; 1819 resets = <&rcc RNG1_R>; 1820 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1821 status = "disabled"; 1822 }; 1823 1824 fmc: memory-controller@58002000 { 1825 #address-cells = <2>; 1826 #size-cells = <1>; 1827 compatible = "st,stm32mp1-fmc2-ebi"; 1828 reg = <0x58002000 0x1000>; 1829 clocks = <&rcc FMC_K>; 1830 resets = <&rcc FMC_R>; 1831 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1832 status = "disabled"; 1833 1834 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1835 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1836 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1837 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1838 <4 0 0x80000000 0x10000000>; /* NAND */ 1839 1840 nand-controller@4,0 { 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 compatible = "st,stm32mp1-fmc2-nfc"; 1844 reg = <4 0x00000000 0x1000>, 1845 <4 0x08010000 0x1000>, 1846 <4 0x08020000 0x1000>, 1847 <4 0x01000000 0x1000>, 1848 <4 0x09010000 0x1000>, 1849 <4 0x09020000 0x1000>; 1850 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1851 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1852 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1853 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1854 dma-names = "tx", "rx", "ecc"; 1855 status = "disabled"; 1856 }; 1857 }; 1858 1859 qspi: spi@58003000 { 1860 compatible = "st,stm32f469-qspi"; 1861 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1862 reg-names = "qspi", "qspi_mm"; 1863 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1864 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1865 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1866 dma-names = "tx", "rx"; 1867 clocks = <&rcc QSPI_K>; 1868 resets = <&rcc QSPI_R>; 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1872 status = "disabled"; 1873 }; 1874 1875 ethernet0: ethernet@5800a000 { 1876 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1877 reg = <0x5800a000 0x2000>; 1878 reg-names = "stmmaceth"; 1879 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1880 interrupt-names = "macirq"; 1881 clock-names = "stmmaceth", 1882 "mac-clk-tx", 1883 "mac-clk-rx", 1884 "eth-ck", 1885 "ptp_ref", 1886 "ethstp"; 1887 clocks = <&rcc ETHMAC>, 1888 <&rcc ETHTX>, 1889 <&rcc ETHRX>, 1890 <&rcc ETHCK_K>, 1891 <&rcc ETHPTP_K>, 1892 <&rcc ETHSTP>; 1893 st,syscon = <&syscfg 0x4>; 1894 snps,mixed-burst; 1895 snps,pbl = <2>; 1896 snps,en-tx-lpi-clockgating; 1897 snps,axi-config = <&stmmac_axi_config_0>; 1898 snps,tso; 1899 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1900 status = "disabled"; 1901 1902 stmmac_axi_config_0: stmmac-axi-config { 1903 snps,wr_osr_lmt = <0x7>; 1904 snps,rd_osr_lmt = <0x7>; 1905 snps,blen = <0 0 0 0 16 8 4>; 1906 }; 1907 }; 1908 1909 usart1: serial@5c000000 { 1910 compatible = "st,stm32h7-uart"; 1911 reg = <0x5c000000 0x400>; 1912 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1913 clocks = <&rcc USART1_K>; 1914 wakeup-source; 1915 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1916 status = "disabled"; 1917 }; 1918 1919 spi6: spi@5c001000 { 1920 #address-cells = <1>; 1921 #size-cells = <0>; 1922 compatible = "st,stm32h7-spi"; 1923 reg = <0x5c001000 0x400>; 1924 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1925 clocks = <&rcc SPI6_K>; 1926 resets = <&rcc SPI6_R>; 1927 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1928 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1929 dma-names = "rx", "tx"; 1930 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1931 status = "disabled"; 1932 }; 1933 1934 i2c4: i2c@5c002000 { 1935 compatible = "st,stm32mp15-i2c"; 1936 reg = <0x5c002000 0x400>; 1937 interrupt-names = "event", "error"; 1938 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&rcc I2C4_K>; 1941 resets = <&rcc I2C4_R>; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1945 wakeup-source; 1946 i2c-analog-filter; 1947 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1948 status = "disabled"; 1949 }; 1950 1951 iwdg1: watchdog@5c003000 { 1952 compatible = "st,stm32mp1-iwdg"; 1953 reg = <0x5C003000 0x400>; 1954 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1956 clock-names = "pclk", "lsi"; 1957 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1958 status = "disabled"; 1959 }; 1960 1961 i2c6: i2c@5c009000 { 1962 compatible = "st,stm32mp15-i2c"; 1963 reg = <0x5c009000 0x400>; 1964 interrupt-names = "event", "error"; 1965 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1967 clocks = <&rcc I2C6_K>; 1968 resets = <&rcc I2C6_R>; 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1972 wakeup-source; 1973 i2c-analog-filter; 1974 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1975 status = "disabled"; 1976 }; 1977 }; 1978 }; 1979 1980 mlahb: ahb { 1981 compatible = "st,mlahb", "simple-bus"; 1982 #address-cells = <1>; 1983 #size-cells = <1>; 1984 ranges; 1985 dma-ranges = <0x00000000 0x38000000 0x10000>, 1986 <0x10000000 0x10000000 0x60000>, 1987 <0x30000000 0x30000000 0x60000>; 1988 1989 m4_rproc: m4@10000000 { 1990 compatible = "st,stm32mp1-m4"; 1991 reg = <0x10000000 0x40000>, 1992 <0x30000000 0x40000>, 1993 <0x38000000 0x10000>; 1994 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1995 reset-names = "mcu_rst", "hold_boot"; 1996 st,syscfg-tz = <&rcc 0x000 0x1>; 1997 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1998 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1999 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 2000 status = "disabled"; 2001 }; 2002 }; 2003}; 2004