core: kernel: fix include order in spinlock.h

Fix order of #include directives in spinlock.h.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.fo

core: kernel: fix include order in spinlock.h

Fix order of #include directives in spinlock.h.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon: Update header files location

The header files in core/drivers/crypto/hisilicon/includes
are only used by the source files in core/drivers/crypto/hisilicon,
so move the he

drivers: crypto: hisilicon: Update header files location

The header files in core/drivers/crypto/hisilicon/includes
are only used by the source files in core/drivers/crypto/hisilicon,
so move the header file from core/drivers/crypto/hisilicon/include
to core/drivers/crypto/hisilicon/.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon:Add HASH and HMAC algorithm

Add HASH and HMAC algorithm by SEC, and support SHA1,
SHA224, SHA256, SHA384, SHA512, MD5, SM3, and HMAC
algorithms based on these algorithms.

drivers: crypto: hisilicon:Add HASH and HMAC algorithm

Add HASH and HMAC algorithm by SEC, and support SHA1,
SHA224, SHA256, SHA384, SHA512, MD5, SM3, and HMAC
algorithms based on these algorithms.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove assertions on device handlers

Remove assertions added by the commit referred below. They are useless
since the handlers are registered only if the related device (stm32_cryp

drivers: crypto: remove assertions on device handlers

Remove assertions added by the commit referred below. They are useless
since the handlers are registered only if the related device (stm32_cryp
or stm32_saes) has its driver successfully probed. These assertion also
prevent enabling both CFG_STM32_SAES and CFG_STM32_CRYP for a platform
which is a valid configuration for when we rely on the DT to state
which of both is enabled.

Fixes: 03de2c7bb316 ("drivers: crypto: stm32_saes: fallback to software on 192bit AES keys")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>

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core: pager: fix arguments passed to calloc in alloc_merged_pgt_array()

An error was reported when compiling with GCC14 on this calloc:

core/arch/arm/mm/tee_pager.c: In function 'alloc_merged_pgt_a

core: pager: fix arguments passed to calloc in alloc_merged_pgt_array()

An error was reported when compiling with GCC14 on this calloc:

core/arch/arm/mm/tee_pager.c: In function 'alloc_merged_pgt_array':
core/arch/arm/mm/tee_pager.c:934:35: warning: 'calloc' sizes specified
with 'sizeof' in the earlier argument and not in the later argument
[-Wcalloc-transposed-args]
934 | pgt_array = calloc(sizeof(struct pgt *), pgt_count);
| ^~~~~~

Looking at the code, it seems that pgt_count and sizeof(struct pgt *)
are inverted.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Fixes: 60e367146042 ("core: pager fix alloc_merged_pgt_array()")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix possible overflow in shdr_alloc_and_copy()

Prior to this patch, if SHDR_GET_SIZE() overflows it will return 0 and
further down in the function lead to an out-of-bounds access. So fix
this

core: fix possible overflow in shdr_alloc_and_copy()

Prior to this patch, if SHDR_GET_SIZE() overflows it will return 0 and
further down in the function lead to an out-of-bounds access. So fix
this with an explicit test before using shdr_size in
shdr_alloc_and_copy().

Fixes: 064663e8bd27 ("core: crypto: add struct shdr helper functions")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Fix store 32-bit thread_core_local flags

The thread_core_local flags is a 32-bit variable. Thus, we must
explicitly use "sw" instruction, which means store 32-bit value into
specific me

core: riscv: Fix store 32-bit thread_core_local flags

The thread_core_local flags is a 32-bit variable. Thus, we must
explicitly use "sw" instruction, which means store 32-bit value into
specific memory address, to operate the thread_core_local flags.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driv

drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driver that uses FFA interface to print trace logs.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: regulator: split regulator_supported_voltages() assertions

Split assertions in regulator_supported_voltages() to ease debugging,
providing a better indication of which condition is not fulf

drivers: regulator: split regulator_supported_voltages() assertions

Split assertions in regulator_supported_voltages() to ease debugging,
providing a better indication of which condition is not fulfilled.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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drivers: regulator: fix error case in regulator_supported_voltages()

Fix case when .supported_voltages() handler is supported. If successful
it shall assert voltage description data. If it returns
T

drivers: regulator: fix error case in regulator_supported_voltages()

Fix case when .supported_voltages() handler is supported. If successful
it shall assert voltage description data. If it returns
TEE_ERROR_NOT_SUPPORTED, it shall use the pre-filled fallback description.

Fixes: af5b9881111c ("drivers: regulator: supported voltage consider levels bounds")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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Squashed commit upgrading to libtomcrypt-1.18.2-develop-20240412

Squash merging branch import/libtomcrypt-1.18.2-develop-20240412

165e1fe7816a ("core: ltc: update for libtomcrypt changes")
ff29487

Squashed commit upgrading to libtomcrypt-1.18.2-develop-20240412

Squash merging branch import/libtomcrypt-1.18.2-develop-20240412

165e1fe7816a ("core: ltc: update for libtomcrypt changes")
ff294871020d ("core: ltc: rsa_verify_hash: fix panic on hash mismatch")
43363afc3d5e ("core: ltc: add fault mitigation in crypto_acipher_rsassa_verify()")
d3040d8bc691 ("libtomcrypt: Remove prng_state* NULL pointer check from ed25519_make_key()")
a1e9686a20cf ("libtomcrypt: ctr_encrypt(): adjust for OP-TEE CE accelerated routines")
eba1524a3989 ("libtomcrypt: define LTC_MPI at the same time as LTC_DER")
e8f42d80d27f ("core: libtomcrypt: Remove prng_state* NULL pointer check from x25519_make_key()")
edb8618bfe6c ("core: ltc: add SM2 curve parameters")
1713825bebd1 ("core: ltc: make key in accel_ecb_encrypt() and accel_ecb_decrypt() const")
53d2509130ce ("core: ltc: fix 'switch case misses default'")
5c7e0de468d1 ("core: ltc: add custom DH key generation function dh_make_key()")
cba20f6a156e ("core: ltc: tomcrypt_custom.h: OP-TEE thread support")
7f247add8fd9 ("libtomcrypt: implement zeromem() with memzero_explicit()")
96ac368c5e68 ("LTC: add GHASH acceleration")
79bd5cb8391c ("ltc: make cipher_descriptor a pointer to descriptors")
a9f0d677e922 ("ltc: make hash_descriptor a pointer to descriptors")
82feb7ac9709 ("ltc: make prng_descriptor a pointer to descriptors")
ae75124e3113 ("libtomcrypt: tomcrypt_private.h: add HASH_PROCESS_NBLOCKS")
a4281f43ea65 ("ECC: optimize the pool of temporary variables")
b32f84118399 ("Import LibTomCrypt v1.18.2 branch "develop" (Apr 12, 2024)")
035c58eeb602 ("Remove LibTomCrypt")

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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core: spmc: fix direct request handler

The FF-A direct request handling has an error: if the destination ID is
the SPMC ID, the handler is trying to forward the message to an SP with
this ID, which

core: spmc: fix direct request handler

The FF-A direct request handling has an error: if the destination ID is
the SPMC ID, the handler is trying to forward the message to an SP with
this ID, which is obviously non-existent so this gives an error.

Fixes: 19ad526cb139 ("core: spmc, sp: cleanup FF-A ID handling")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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drivers: pm: sam: map SFRBU with DT_MAP_SECURE attribute for sama7g5

As sama7g5's SFRBU is always secured map it as secured and do not
need to configure the security through the matrix.

Signed-off-

drivers: pm: sam: map SFRBU with DT_MAP_SECURE attribute for sama7g5

As sama7g5's SFRBU is always secured map it as secured and do not
need to configure the security through the matrix.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: rename pm_init functions for later sama7g5 support

PM support for sama7g5 will reuse some existing functions.
Rename sama5d2_pm_init() to sam_pm_init().
Rename sama5d2_pm_init_all(

drivers: pm: sam: rename pm_init functions for later sama7g5 support

PM support for sama7g5 will reuse some existing functions.
Rename sama5d2_pm_init() to sam_pm_init().
Rename sama5d2_pm_init_all() to sam_pm_init_all().

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: atmel_shdwc: enable RTT (Real-time Timer) Wake-up

For sama7g5 the Wake-up can be caused by RTT.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@li

drivers: atmel_shdwc: enable RTT (Real-time Timer) Wake-up

For sama7g5 the Wake-up can be caused by RTT.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: atmel_shdwc: update to call the initialize for PM for sama7g5

For sama7g5 case do not return before calling the initialize function
for PM.

Signed-off-by: Tony Han <tony.han@microchip.com>

drivers: atmel_shdwc: update to call the initialize for PM for sama7g5

For sama7g5 case do not return before calling the initialize function
for PM.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: use fdt64_ld() to read possibly unaligned kaslr-seed

Read possibly unaligned kaslr-seed using `fdt64_ld()`
to avoid ubsan panic while booting with `CFG_CORE_ASLR=y`

Acked-by: Jens Wiklan

core: arm: use fdt64_ld() to read possibly unaligned kaslr-seed

Read possibly unaligned kaslr-seed using `fdt64_ld()`
to avoid ubsan panic while booting with `CFG_CORE_ASLR=y`

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Abhishek Revadekar <abhishek.rvdkr@yahoo.com>

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core: fix undefined references to ubsan functions

Add UBSan handlers for `__ubsan_handle_type_mismatch_v1` and
`__ubsan_handle_pointer_overflow` to remove undefined references error.

Acked-by: Jens

core: fix undefined references to ubsan functions

Add UBSan handlers for `__ubsan_handle_type_mismatch_v1` and
`__ubsan_handle_pointer_overflow` to remove undefined references error.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Abhishek Revadekar <abhishek.rvdkr@yahoo.com>

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core: callout: disable obsolete timeouts

In callout_service_cb() when a timeout interrupt is received there's a
check to see if this is the last scheduled CPU. If not the interrupt is
ignored, but n

core: callout: disable obsolete timeouts

In callout_service_cb() when a timeout interrupt is received there's a
check to see if this is the last scheduled CPU. If not the interrupt is
ignored, but not disabled causing it to trigger again and again. So fix
this by disabling the timeout too.

Fixes: cf707bd0d695 ("core: add callout service")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mmu: fix memory regions found from ff-a manifest

Fix the 6th parameter of add_phys_mem() in collect_device_mem_ranges()
that has to be the size of memory region and not the end address of the

core: mmu: fix memory regions found from ff-a manifest

Fix the 6th parameter of add_phys_mem() in collect_device_mem_ranges()
that has to be the size of memory region and not the end address of the
region.

Fixes: 72a6827a6353 ("core: arm: SPMC obtain device memory info from DTB")
Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers:implement HiSilicon Security Engine(SEC) module.

HiSilicon SEC is used in security applications such as
authentication and data encryption and decryption. This
module implement the hardware

drivers:implement HiSilicon Security Engine(SEC) module.

HiSilicon SEC is used in security applications such as
authentication and data encryption and decryption. This
module implement the hardware initialization of the SEC.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: hisilicon: add DH algorithm

add operation of DH algorithm, including alloc_keypair,
gen_keypair and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Etienne Car

drivers: crypto: hisilicon: add DH algorithm

add operation of DH algorithm, including alloc_keypair,
gen_keypair and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: fix ce_aes_xts_{de,en}crypt()

In ce_aes_xts_encrypt() and ce_aes_xts_decrypt(), if the main interleave
loop (.LxtsencNx or .LxtsdecNx) ends with all blocks completed the v7
register doe

core: arm64: fix ce_aes_xts_{de,en}crypt()

In ce_aes_xts_encrypt() and ce_aes_xts_decrypt(), if the main interleave
loop (.LxtsencNx or .LxtsdecNx) ends with all blocks completed the v7
register doesn't hold the needed .Lxts_mul_x needed to compute the next
tweak correctly. So fix this by loading .Lxts_mul_x in v7 before ending
the loop.

Fixes: 06d2e4167a6b ("core: add accelerated AES routines")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ltc: sub.mk: reorganize and simplify

Reorganize the LTC sub.mk by collecting configuration and files in
groups by algorithm or feature.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.or

core: ltc: sub.mk: reorganize and simplify

Reorganize the LTC sub.mk by collecting configuration and files in
groups by algorithm or feature.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ltc: merge sub.mk's into a single sub.mk

Merge all sub.mk's below core/lib/libtomcrypt/src at the end of
core/lib/libtomcrypt/sub.mk.

It gives an easier overview of what is compiled, but it a

core: ltc: merge sub.mk's into a single sub.mk

Merge all sub.mk's below core/lib/libtomcrypt/src at the end of
core/lib/libtomcrypt/sub.mk.

It gives an easier overview of what is compiled, but it also makes it
easier when syncing core/lib/libtomcrypt/src with LTC upstream since
it's out of the way.

Unused sub.mk's are removed.

Removes the now unused _CFG_CORE_LTC_CIPHER, _CFG_CORE_LTC_AUTHENC and
_CFG_CORE_LTC_MAC from core/crypto.mk.

The global LTC build flag -Wno-declaration-after-statement is removed and
only supplied to the few source files that need it.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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