core: rename secure_mmu_unifiedtlbinvXXX() into tlbi_XXX()

secure_mmu_unifiedtlbinvall() => tlbi_all()
secure_mmu_unifiedtlbinv_byasid() => tlbi_asid()
secure_mmu_unifiedtlbinvbymva() => tlbi_mva_cu

core: rename secure_mmu_unifiedtlbinvXXX() into tlbi_XXX()

secure_mmu_unifiedtlbinvall() => tlbi_all()
secure_mmu_unifiedtlbinv_byasid() => tlbi_asid()
secure_mmu_unifiedtlbinvbymva() => tlbi_mva_curasid()

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: review TLB invalidation sequences

Align the AArch64 and AArch32 implementation of the TLB invalidation
sequences, mainly on synchronization barrier and implementation comments.

Signed-off-by:

core: review TLB invalidation sequences

Align the AArch64 and AArch32 implementation of the TLB invalidation
sequences, mainly on synchronization barrier and implementation comments.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: remove secure_mmu_unifiedtlbinv_curasid()

Remove duplicated code.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add tlbi and dsb instructions

Add 32bit and 64bit dsbish and dsbishst instructions.
Add 32bit write_tlbimvaais macro for TLB maintenance.

Signed-off-by: Etienne Carriere <etienne.carriere@lin

core: add tlbi and dsb instructions

Add 32bit and 64bit dsbish and dsbishst instructions.
Add 32bit write_tlbimvaais macro for TLB maintenance.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: assign non-sec DDR configuration from DT

Assigns non-secure DDR configuration from device tree if CFG_DT=y. Already
present DDR configuration from register_nsec_ddr() is overridden.

Reviewed-

core: assign non-sec DDR configuration from DT

Assigns non-secure DDR configuration from device tree if CFG_DT=y. Already
present DDR configuration from register_nsec_ddr() is overridden.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

plat-vexpress: use register_nsec_ddr()

Plat-vexpress uses register_nsec_ddr() to define the non-secure DDR
memory.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carri

plat-vexpress: use register_nsec_ddr()

Plat-vexpress uses register_nsec_ddr() to define the non-secure DDR
memory.

Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

ABI change: add OPTEE_MSG_ATTR_NONCONTIG handling

This patch introduces new attribute OPTEE_MSG_ATTR_NONCONTIG to allow
Normal World pass arbitrary list of physical pages as a shared buffer.

To rea

ABI change: add OPTEE_MSG_ATTR_NONCONTIG handling

This patch introduces new attribute OPTEE_MSG_ATTR_NONCONTIG to allow
Normal World pass arbitrary list of physical pages as a shared buffer.

To read this list of page address two new functions are added:
- msg_param_extract_pages() is a helper function that read pages list
into provided array

- msg_param_mobj_from_noncontig_param() constructs mobj from provided
struct optee_msg_param parameter. This mobj then can be used in
various parts of OP-TEE

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: update cache helpers

Updates AArch64 and ARMv7 cache helpers from lib/aarch32/cache_helpers.S
and lib/aarch64/cache_helpers.S in ARM-TF,
https://github.com/ARM-software/arm-trusted-firmware/tr

core: update cache helpers

Updates AArch64 and ARMv7 cache helpers from lib/aarch32/cache_helpers.S
and lib/aarch64/cache_helpers.S in ARM-TF,
https://github.com/ARM-software/arm-trusted-firmware/tree/2bd26faf62411c75111fea4b23c542865383b068

The imported routines only covers the inner cache. Already present ARMv7
cache routines are replaced by the new equivalent routines. The AArch64
routines are updated with the resent changes in ARM-TF.

The imported files are modified to better fit into OP-TEE, some
functions and defines are renamed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch{32,64} pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm32_macros.S: add cache related macros

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm32_macros.S: sort macros

Sorts macros and fixes the macro write_bpial

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm.h: add cache related defines

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix incorrect IRQ mask for CFG_ARM_GICV3

For GICV3 situation, IRQ is used as native interrupt. This patch
also suppressed assert in thread_user_save_vfp().

Signed-off-by: Zhizhou Zhang <zhizh

core: fix incorrect IRQ mask for CFG_ARM_GICV3

For GICV3 situation, IRQ is used as native interrupt. This patch
also suppressed assert in thread_user_save_vfp().

Signed-off-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm64: bugfix invalidate touched init memory

The entire range of memory touched during init need to be invalidated in
the caches before enabling the caches.

Prior to this patch with CFG_WITH_

core: arm64: bugfix invalidate touched init memory

The entire range of memory touched during init need to be invalidated in
the caches before enabling the caches.

Prior to this patch with CFG_WITH_PAGER=y the caches where only
invalidated until __init_end which isn't enough, memory up to
__tmp_hashes_end is actually touched. With this patch the range is
increased to __tmp_hashes_end which is the same as is used in the arm32
code.

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey 32/64)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey 64-bit pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: reduce init size

Dramatically reduces init size by excluding __wq_rpc() from the init
graph. Without __wq_rpc() in the init grapth, the entire LibTomCrypt is
removed for the init graph.

Teste

core: reduce init size

Dramatically reduces init size by excluding __wq_rpc() from the init
graph. Without __wq_rpc() in the init grapth, the entire LibTomCrypt is
removed for the init graph.

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v8 pager)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: reduce unpaged size

Reduces unpaged size by excluding __thread_std_smc_entry() from the
unpaged graph.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklande

core: reduce unpaged size

Reduces unpaged size by excluding __thread_std_smc_entry() from the
unpaged graph.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm: use weak symbols to reduce dependency graphs

Makes functions that need to be excluded from unpaged and init parts of
the TEE binary weak. When building the dependency graph for init and
u

core: arm: use weak symbols to reduce dependency graphs

Makes functions that need to be excluded from unpaged and init parts of
the TEE binary weak. When building the dependency graph for init and
unpaged parts an empty version of those functions (from
core/arch/arm/kernel/link_dummies.c) are used instead.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: bugfix undefined behavior in expand_prel31()

Fixes undefined behavior in expand_prel31() detected with
CFG_CORE_SANITIZE_UNDEFINED=y

ERROR: [0x0] TEE-CORE: Undefined behavior shift_out_of_b

core: bugfix undefined behavior in expand_prel31()

Fixes undefined behavior in expand_prel31() detected with
CFG_CORE_SANITIZE_UNDEFINED=y

ERROR: [0x0] TEE-CORE: Undefined behavior shift_out_of_bounds at core/arch/arm/kernel/unwind_arm32.c:102 col 42
ERROR: [0x0] TEE-CORE: Panic at core/kernel/ubsan.c:189 <__ubsan_handle_shift_out_of_bounds>

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: ubsan: fix __ubsan_handle_nonnull_arg()

Fixes error:
core/kernel/ubsan.c:114:6: error: conflicting types for built-in function '__ubsan_handle_nonnull_arg' [-Werror]
void __ubsan_handle_nonnu

core: ubsan: fix __ubsan_handle_nonnull_arg()

Fixes error:
core/kernel/ubsan.c:114:6: error: conflicting types for built-in function '__ubsan_handle_nonnull_arg' [-Werror]
void __ubsan_handle_nonnull_arg(struct nonnull_arg_data *data, size_t arg_no);
^~~~~~~~~~~~~~~~~~~~~~~~~~
core/kernel/ubsan.c:229:6: error: conflicting types for built-in function '__ubsan_handle_nonnull_arg' [-Werror]
void __ubsan_handle_nonnull_arg(struct nonnull_arg_data *data,
^~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors

When compiling with gcc 6.2.1

For the record: with GCC 6.0.0 __ubsan_handle_nonnull_arg() was changed to
take only one argument.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

ltc: Enable RSA_CRT_HARDENING and RSA_CRT_BLINDING

Enable the hardening flags by default. This should make it robust to the
Bellcore attack when using RSA with CRT.

Fixes: OP-TEE-2016-0003 which wa

ltc: Enable RSA_CRT_HARDENING and RSA_CRT_BLINDING

Enable the hardening flags by default. This should make it robust to the
Bellcore attack when using RSA with CRT.

Fixes: OP-TEE-2016-0003 which was reported by Applus+ Laboratories.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260, GP)

show more ...

ltc: Implement mp_rand for mpa_desc

When enabling the flag LTC_RSA_BLINDING the code uses the mp_rand()
function, which isn't implemented for the mpa_desc descriptor. Implement
it as rand() in mpa_d

ltc: Implement mp_rand for mpa_desc

When enabling the flag LTC_RSA_BLINDING the code uses the mp_rand()
function, which isn't implemented for the mpa_desc descriptor. Implement
it as rand() in mpa_desc and mpa_get_random_digits() in libmpa.

Fixes: OP-TEE-2016-0003 which was reported by Applus+ Laboratories.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260, GP)

show more ...

ltc: fix formatting related to exptmod

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@lin

ltc: fix formatting related to exptmod

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260, GP)

show more ...

ltc: remove LTC_LINARO_FIX_RSAWITHOUTCRT

LTC_LINARO_FIX_RSAWITHOUTCRT is used to handle the case where the CRT
optimized algorithm cannot be used because the optimized parameters are
missing. In the

ltc: remove LTC_LINARO_FIX_RSAWITHOUTCRT

LTC_LINARO_FIX_RSAWITHOUTCRT is used to handle the case where the CRT
optimized algorithm cannot be used because the optimized parameters are
missing. In the official LibTomCrypt tree, there is an official fix for
this.

Please see commits (official LibTomCrypt tree):
01f184540232 ("harden RSA CRT by implementing the proposed
countermeasure from ch. 1.3 of [1]")
a6e89d58d4fb ("RSA in CRT optimization parameters are empty")
2bb3f0246f65 ("RSA in case CRT optimization parameters are not
populated")

Those patches were brought into OP-TEE with this patch
a50cb361d9e5 ("ltc: sync from official develop branch")

And therefore there is no need to keep the LTC_LINARO_FIX_RSAWITHOUTCRT
any longer, hence this patch removes the flag and the code related to
that particular flag.

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260, GP)

show more ...

core: fix listing of init resources in linker file

Fix the missing space character to separate entries at generation of
init_entries.txt file. This file content is used as an argument list
string fo

core: fix listing of init resources in linker file

Fix the missing space character to separate entries at generation of
init_entries.txt file. This file content is used as an argument list
string for the linker tool.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

msg_param.h: add `const` qualifier for read-only functions

msg_param_get_buf_size() and msg_param_attr_is_tmem() only read
from their parameter, so that parameter can be declared as `const`

Signed

msg_param.h: add `const` qualifier for read-only functions

msg_param_get_buf_size() and msg_param_attr_is_tmem() only read
from their parameter, so that parameter can be declared as `const`

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

mobj: mobj_reg_shm: fix bug in offset calculation

Wrong variable was used to calculate offset.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@

mobj: mobj_reg_shm: fix bug in offset calculation

Wrong variable was used to calculate offset.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...