Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores

Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores ARM SoCs.

plat-rockchip support features:
1.Support SMP cpu boot up and power down;
2.Support system reset;
3.Support GIC driver initialization.

make PLATFORM=rockchip-rk322x

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add udelay function

Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jero

core: add udelay function

Using ARM Generic Timer to support time delay, make sure CNTFRQ
register has been initialized before use.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: serial8250_uart: use 32-bit accesses to the uart registers

Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviou

drivers: serial8250_uart: use 32-bit accesses to the uart registers

Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviously, using
32-bit accesses to the registers is more flexible for other plaforms
to use serial8250 uart.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org> (serial8250_uart, TI-AM57xx)

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core: arm: boot: fix get_memory

From Power_ePAPR_APPROVED_v1.1.pdf chapter 3.4 Memory node,
there is no address-cells and size-cells property for in
memory node. Memory node only support three prope

core: arm: boot: fix get_memory

From Power_ePAPR_APPROVED_v1.1.pdf chapter 3.4 Memory node,
there is no address-cells and size-cells property for in
memory node. Memory node only support three properties "device_type",
"reg" and "initial-mapped-area".

When prase the memory node, need to use the address/size-cells of
root node.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xt

plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xtest 4002 (s)
---------+--------------------
512 KiB | 16
544 KiB | 6
640 KiB | 0.07

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mmu: fix core_mmu_add_mapping()

Use dsb_ishst() to make sure the new entry visible before continuing.

A9 Unified main TLB:
supports hardware page table walks to perform look-ups in the L

core: arm: mmu: fix core_mmu_add_mapping()

Use dsb_ishst() to make sure the new entry visible before continuing.

A9 Unified main TLB:
supports hardware page table walks to perform look-ups in the L1 data
cache

To A7 and A15, they both support coherent walk, see ID_MMFR3:
Updates to the translation tables do not require a clean to the point of
unification to ensure visibility by subsequent translation table walks

Note: I did not find doc talking coherent walk for A8, so A8 may need
cached flushed when update TLB?

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor edits to commit message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: add snvs srtc support

Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabili

drivers: add snvs srtc support

Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.

Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.

The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm.mk: export-ta_arm32: Set default value for CROSS_COMPILE

When building 32-bit optee_os, CROSS_COMPILE32 defaults to CROSS_COMPILE
if not set, and CROSS_COMPILE defaults to arm-linux-gnueabihf- i

arm.mk: export-ta_arm32: Set default value for CROSS_COMPILE

When building 32-bit optee_os, CROSS_COMPILE32 defaults to CROSS_COMPILE
if not set, and CROSS_COMPILE defaults to arm-linux-gnueabihf- if not
set.

When building 32-bit optee_test, CROSS_COMPILE32 also defaults to
CROSS_COMPILE if not set, but if CROSS_COMPILE is not set, there is no
default value, causing the native compiler to be used and generating
errors and confusion.

This patch makes the behavior and expectations consistent across both
optee_os and optee_test.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey: Set default value for CONSOLE_UART_BASE in conf.mk

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

hikey: add support for hikey960

The HiKey 960 development platform is based around the Huawei Kirin 960
octa-core ARM big.LITTLE processor with four ARM Cortex-A73 and four
Cortex-A53 cores with 3GB

hikey: add support for hikey960

The HiKey 960 development platform is based around the Huawei Kirin 960
octa-core ARM big.LITTLE processor with four ARM Cortex-A73 and four
Cortex-A53 cores with 3GB of LPDDR4 SDRAM memory, 32GB of UFS 2.0 flash
storage, and the latest generation Mali G71 MP8 graphics processor.

See https://www.96boards.org/product/hikey960 for more details.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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hikey: Flavorize hikey

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

hikey: use defines for pl011 uart base addresses

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: arm32: fix native_intr_handler()

Prior to this patch when a native interrupt was received in IRQ mode
r12 wasn't saved on the stack. There's two problems with that:
1. r12 isn't a callee prese

core: arm32: fix native_intr_handler()

Prior to this patch when a native interrupt was received in IRQ mode
r12 wasn't saved on the stack. There's two problems with that:
1. r12 isn't a callee preserved register, but must be preserved
in an exception handler
2. Without r12 an odd number of registers was saved breaking the
8 byte alignment of the stack pointer

This patch fixes this by also saving r12 on the stack when handling a
native interrupt in IRQ mode.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: gcc 7 ready

Remove the armv7 compiler option -mno-apcs-float as it's not supported
by gcc 7. -apcs-float has be default disabled since at least gcc 4.8.

Reviewed-by: Igor Opaniuk <igor.opaniu

core: gcc 7 ready

Remove the armv7 compiler option -mno-apcs-float as it's not supported
by gcc 7. -apcs-float has be default disabled since at least gcc 4.8.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: avoid page faults with pager lock held

When a normal thread takes the pager lock there must be no page faults
while the lock is held. This is has so far been ensured by feeding the
func

core: pager: avoid page faults with pager lock held

When a normal thread takes the pager lock there must be no page faults
while the lock is held. This is has so far been ensured by feeding the
function to the KEEP_PAGER() macro, but this will only take care of the
actual code not stack usage. This patch introduces a new pager lock
function, pager_lock_check_stack() which will make sure that the
estimated needed stack is mapped before the lock is acquired.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assert only normal thread takes a mutex

Adds thread_is_in_normal_mode() which returns true if the current thread
is in normal mode. Adds an assert(thread_is_in_normal_mode()) in
__mutex_lock()

core: assert only normal thread takes a mutex

Adds thread_is_in_normal_mode() which returns true if the current thread
is in normal mode. Adds an assert(thread_is_in_normal_mode()) in
__mutex_lock().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mutex: simplify code with xsave/xrestore spin lock

cpu_spin_lock_xsave/cpu_spin_unlock_xrestore could be used
to simplify the code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by

core: arm: mutex: simplify code with xsave/xrestore spin lock

cpu_spin_lock_xsave/cpu_spin_unlock_xrestore could be used
to simplify the code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: fix imx6solo boot

i.MX6SOLO is almost same with i.MX6DualLite, with difference that
6S has one cpu core, but DualLite has two cpu cores.
i.MX6Solo also needs a9_plat_init.S and imx6.

core: arm: imx: fix imx6solo boot

i.MX6SOLO is almost same with i.MX6DualLite, with difference that
6S has one cpu core, but DualLite has two cpu cores.
i.MX6Solo also needs a9_plat_init.S and imx6.c for basic initialization.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey: use core_mmu_get_va() whenever possible

The ability to get the va of a pa is now available as a core function,
i.e. core_mmu_get_va() so the platform specific nsec_periph_base() is
not requir

hikey: use core_mmu_get_va() whenever possible

The ability to get the va of a pa is now available as a core function,
i.e. core_mmu_get_va() so the platform specific nsec_periph_base() is
not required anymore.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix the size of dynamic shared memory buffers

Prior to this patch MEM_AREA_SHM_VASPACE was initialized with
RES_VASPACE_SIZE which is wrong. With this patch MEM_AREA_SHM_VASPACE is
initialized

core: fix the size of dynamic shared memory buffers

Prior to this patch MEM_AREA_SHM_VASPACE was initialized with
RES_VASPACE_SIZE which is wrong. With this patch MEM_AREA_SHM_VASPACE is
initialized with SHM_VASPACE_SIZE instead.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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core: remove the useless mem_map_inited

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

core: pager: more details in deadlock report

Adds more details to deadlock report inside pager.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.

core: pager: more details in deadlock report

Adds more details to deadlock report inside pager.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: attempt to detect deadlock on spin locks

Attempts to detect and report deadlock on spin locks..

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wikland

core: attempt to detect deadlock on spin locks

Attempts to detect and report deadlock on spin locks..

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: abort: fix get_fault_type()

Fixes get_fault_type() to accurately report abort in abort handler also
in AArch64.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wik

core: abort: fix get_fault_type()

Fixes get_fault_type() to accurately report abort in abort handler also
in AArch64.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v8)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: deprecate platform stm-orly2

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>