core: fix crash during syscall ftrace

Syscall ftrace collects data during a syscall. get_fbuf() checks if
thread_get_id_may_fail() != -1 to see if a function is called under
normal thread execution.

core: fix crash during syscall ftrace

Syscall ftrace collects data during a syscall. get_fbuf() checks if
thread_get_id_may_fail() != -1 to see if a function is called under
normal thread execution. This can lead to an inconsistent state if a
native interrupt occur while ftrace_enter() or ftrace_return() is
recording data in the ftrace buffer. So fix this by using
thread_is_in_normal_mode() to exclude ftrace during interrupt
processing.

Reported-by: Jerome Forissier <jerome.forissier@linaro.org>
Closes: https://github.com/OP-TEE/optee_os/issues/7216
Fixes: 099918f6744c ("ftrace: Add support for syscall function tracer")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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drivers: sam: fix getting interrupts from DT

The issue is found on sama5d2 platform.
Get interrupt fails due to the change of function parameter (from
count by bytes to count by words), fixed by mak

drivers: sam: fix getting interrupts from DT

The issue is found on sama5d2 platform.
Get interrupt fails due to the change of function parameter (from
count by bytes to count by words), fixed by making corresponding
changes to the function called later.

Fixes: 63873401cb04 ("core: interrupt: fix property count in dt_get_irq_type_prio()")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fs_htree: Fix wrong AAD length in authenc_init()

In authenc_init(), AAD length field passed to
crypto_authenc_init() does not match with the total
AAd data passed via crypto_authenc_update_aad

core: fs_htree: Fix wrong AAD length in authenc_init()

In authenc_init(), AAD length field passed to
crypto_authenc_init() does not match with the total
AAd data passed via crypto_authenc_update_aad() for
lower layer crypto computation.

To fix this issue and to support the legacy without
breaking existing REE file system content, introduce
a config CFG_REE_FS_HTREE_HASH_SIZE_COMPAT.

By default this config is enabled to support the legacy
REE FS hash tree that uses truncated hash implementation.

Link: https://github.com/OP-TEE/optee_os/issues/7331
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: update recorded SP first after MMU is enabled

With CFG_CORE_ASLR=y, stored addresses must be updated after MMU has
been enabled to match the map offset. In particular the recorded stack
p

core: arm: update recorded SP first after MMU is enabled

With CFG_CORE_ASLR=y, stored addresses must be updated after MMU has
been enabled to match the map offset. In particular the recorded stack
pointers in thread_core_local[] must be updated to match the new offset
before any calls can be done into C code or check_stack_limits() with
CFG_CORE_DEBUG_CHECK_STACKS=y might catch an inconsistent stack pointer.

Currently, boot_mem_relocate() is called before the recorded stack
pointers have been updated and causes a crash with CFG_CORE_ASLR=y and
CFG_CORE_DEBUG_CHECK_STACKS=y. So fix this by calling delaying the call
to boot_mem_relocate() to after the stack pointers in
thread_core_local[] has been updated.

Reported-by: Jerome Forissier <jerome.forissier@linaro.org>
Closes: https://github.com/OP-TEE/optee_os/issues/7363
Fixes: ea991d7459f6 ("core: arm: remove THREAD_CORE_LOCAL_STACKCHECK_RECURSION")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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core: riscv: allow enabling CFG_WITH_STACK_CANARIES

Remove force disablement of randomized stack canary for OP-TEE core.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin

core: riscv: allow enabling CFG_WITH_STACK_CANARIES

Remove force disablement of randomized stack canary for OP-TEE core.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: support random stack canaries for stack protector

Call plat_get_random_stack_canaries() and update the value of
__stack_chk_guard during early initialization, so that the
random stack c

core: riscv: support random stack canaries for stack protector

Call plat_get_random_stack_canaries() and update the value of
__stack_chk_guard during early initialization, so that the
random stack canaries can be used to detect stack overflow
and buffer overflow.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: move plat_get_random_stack_canaries() to common part

Other architectures (e.g. RISC-V) may want to call
plat_get_random_stack_canaries() for random stack
canaries. Move it from ARM architectur

core: move plat_get_random_stack_canaries() to common part

Other architectures (e.g. RISC-V) may want to call
plat_get_random_stack_canaries() for random stack
canaries. Move it from ARM architecture directory
to common part.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix configuration to disable stack protector

Fix the configuration to explicitly disable the compile
option of core stack protector.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
R

core: fix configuration to disable stack protector

Fix the configuration to explicitly disable the compile
option of core stack protector.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: fix discovered ns-mem check

When discovering or assigning available non-secure physical memory it's
checked against overlaps with other memory types. Memory types reserving
virtual memory spac

core: fix discovered ns-mem check

When discovering or assigning available non-secure physical memory it's
checked against overlaps with other memory types. Memory types reserving
virtual memory space should be excluded including the two recently added
types MEM_AREA_NEX_DYN_VASPACE and MEM_AREA_TEE_DYN_VASPACE. This was
missed when the memory types where added so add the check to exclude
them now.

This fixes an error like:
E/TC:0   check_phys_mem_is_outside:455 Non-sec mem (0:0x60000000) overlaps map (type 10 0:0x100000)
E/TC:0   Panic at core/mm/core_mmu.c:459 <check_phys_mem_is_outside>

Fixes: 96f43358c593 ("core: add nex_dyn_vaspace and tee_dyn_vaspace areas")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: disable CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID with se05x

Commit fc80dabbd5a7 ("core: imx: enable
CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID by default") created a
regression when se05x

core: imx: disable CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID with se05x

Commit fc80dabbd5a7 ("core: imx: enable
CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID by default") created a
regression when se05x is used on iMX platforms, as its own
implementation of tee_otp_get_die_id cannot be called so early in the
boot process, since the stack itself is not properly initialized at that
time.

Forcely disable CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID when se05x is
used to restore back to the previous working behavior.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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drivers: stm32_rifsc: remove semaphore acquisition when applying the conf

Remove the semaphore acquisition when applying the configuration
so that they are taken, if necessary, during the firewall b

drivers: stm32_rifsc: remove semaphore acquisition when applying the conf

Remove the semaphore acquisition when applying the configuration
so that they are taken, if necessary, during the firewall bus probe.
This avoids semaphores from being taken by OP-TEE when the peripheral
isn't used.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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tree wide: fix header files dependencies in linker files

When linking with a generated linker script like kern.ld.S, dependencies
with header file are not regenerated.
Same issue as
commit acdc32afe

tree wide: fix header files dependencies in linker files

When linking with a generated linker script like kern.ld.S, dependencies
with header file are not regenerated.
Same issue as
commit acdc32afe18f ("mk/compile.mk: fix header dependency in .d file")

Add option -MP used to fix error generated when removing header files.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: ffa: enable FF-A version 1.2 for virtualization

With Xen version 4.20 released we can announce version 1.2 for OP-TEE
when negotiating the version to use. So remove the special check for

core: arm: ffa: enable FF-A version 1.2 for virtualization

With Xen version 4.20 released we can announce version 1.2 for OP-TEE
when negotiating the version to use. So remove the special check for
CFG_NS_VIRTUALIZATION=y when exchanging versions.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx_csu: add SA settings for i.MX6ULL

Add the CSU SA settings for i.MX6ULL. The i.MX6ULL implements the same
non-Trustzone aware masters as the i.MX6UL, so the same settings can be
used. Th

drivers: imx_csu: add SA settings for i.MX6ULL

Add the CSU SA settings for i.MX6ULL. The i.MX6ULL implements the same
non-Trustzone aware masters as the i.MX6UL, so the same settings can be
used. This setting ensures that no non-TrustZone aware master is able
to read secure memory. Information on the CSU SA register values were
taken from i.MX6ULL Security Reference Manual rev 0.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: riscv: add SiFive Unleashed and Unmatched board support

Add SiFive Unleashed and Unmatched board support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland

core: riscv: add SiFive Unleashed and Unmatched board support

Add SiFive Unleashed and Unmatched board support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Acked-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: drivers: support SiFive UART

Add sifive uart support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zo

core: drivers: support SiFive UART

Add sifive uart support.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Acked-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: kernel: support booting non-contiguous non-zero-based hart IDs

Currently, OP-TEE assumes 0 <= hartid < CFG_TEE_CORE_NB_CORE,
and must be contiguous, which fails to accommodate different
CPU t

riscv: kernel: support booting non-contiguous non-zero-based hart IDs

Currently, OP-TEE assumes 0 <= hartid < CFG_TEE_CORE_NB_CORE,
and must be contiguous, which fails to accommodate different
CPU topologies. For example, some RISC-V platforms, such as
the HiFive Unmatched board, do not run Linux and OP-TEE on
hart0, as it is a monitor core without supervisor mode support.

To address this, introduce hart_index, which is used to index
per-hart structures, such as thread_core_local and root_pgt.
The hart_index will range from 0 to (CFG_TEE_CORE_NB_CORE - 1),
and the primary hart will have an index of 0.

Additionally, a new function, boot_primary_init_core_ids(),
is added to initialize secondary hart IDs for booting via
sbi_hsm_hart_start().

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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riscv: kernel: sbi: introduce sbi_hsm_hart_get_status() function

Introduce sbi_hsm_hart_get_status() function and add comment for
sbi_hsm_hart_start().

Signed-off-by: Yu-Chien Peter Lin <peter.lin@

riscv: kernel: sbi: introduce sbi_hsm_hart_get_status() function

Introduce sbi_hsm_hart_get_status() function and add comment for
sbi_hsm_hart_start().

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: plat-virt: move stack alignment definition

The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configurat

riscv: plat-virt: move stack alignment definition

The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configuration to riscv.h.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: kernel: entry.S: remove unused boot_args array

The boot_args array is unused anywhere and its contents
are cleared during the zeroing of the .bss section, so it
serves no purpose. Removing it

riscv: kernel: entry.S: remove unused boot_args array

The boot_args array is unused anywhere and its contents
are cleared during the zeroing of the .bss section, so it
serves no purpose. Removing it simplifies the code.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: disable ELE on i.MX8ULP by default

On i.MX8ULP, there is only one MU to communicate with ELE,
which cannot be dedicated on OP-TEE side all the time.
There may be ELE services running on L

core: imx: disable ELE on i.MX8ULP by default

On i.MX8ULP, there is only one MU to communicate with ELE,
which cannot be dedicated on OP-TEE side all the time.
There may be ELE services running on Linux side, which can
cause conflict with OP-TEE, So disabling ELE by default.
Moreover i.MX8ULP also has CAAM, so HUK and Random number
are coming from CAAM.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rockchip: rk3588: add OTP_S support and HUK

Add OTP_S support for Rockchip rk3588
Add tee_otp_get_hw_unique_key()

Signed-off-by: Ed Tubbs <ectubbs@gmail.com>
Acked-by: Etienne Carriere <etienn

plat-rockchip: rk3588: add OTP_S support and HUK

Add OTP_S support for Rockchip rk3588
Add tee_otp_get_hw_unique_key()

Signed-off-by: Ed Tubbs <ectubbs@gmail.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: pta: fix virt_to_phys() self tests

Only test on VCORE_FREE_* addresses if CFG_DYN_CONFIG=y since those
addresses otherwise are unmapped or even unassigned.

Fixes: a05b3a459a3b ("core: pta: ad

core: pta: fix virt_to_phys() self tests

Only test on VCORE_FREE_* addresses if CFG_DYN_CONFIG=y since those
addresses otherwise are unmapped or even unassigned.

Fixes: a05b3a459a3b ("core: pta: add self tests for virt_to_phys()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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ta: enable ubsan support for TAs

Introduce CFG_TA_SANITIZE_UNDEFINED config to sanitize trusted
applications. If CFG_TA_SANITIZE_UNDEFINED is set sanitize flags are
propagated to internal TAs (avb,

ta: enable ubsan support for TAs

Introduce CFG_TA_SANITIZE_UNDEFINED config to sanitize trusted
applications. If CFG_TA_SANITIZE_UNDEFINED is set sanitize flags are
propagated to internal TAs (avb, pkcs11, remoteproc, trusted_keys) and
external TAs, which are built with the devkit.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ldelf: enable ubsan support

Ubsan support was previously limited to core code. This commit moves the
ubsan runtime implementation to libutils, making it available for ldelf
and trusted applications.

ldelf: enable ubsan support

Ubsan support was previously limited to core code. This commit moves the
ubsan runtime implementation to libutils, making it available for ldelf
and trusted applications.

As a result, ldelf will now be built with ubsan support when
CFG_CORE_SANITIZE_UNDEFINED is enabled.

Additionally, to avoid potential infinite recursion, ubsan
instrumentation is explicitly disabled for ubsan.c.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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