core: riscv: Preparation to support CFG_BOOT_MEM

Refer to commit d461c892a15a ("core: arm: enable CFG_BOOT_MEM
unconditionally") and commit f12843460d47 ("core: mm: allocate
temporary memory map arr

core: riscv: Preparation to support CFG_BOOT_MEM

Refer to commit d461c892a15a ("core: arm: enable CFG_BOOT_MEM
unconditionally") and commit f12843460d47 ("core: mm: allocate
temporary memory map array"), call the boot_mem_*() functions as
needed from entry.S and boot.c for RISC-V architecture.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: imx: enable ELE by default

Enable ELE by default on all ELE supported devices

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked

core: imx: enable ELE by default

Enable ELE by default on all ELE supported devices

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: rng: get random number from ELE

TEE_GenerateRandom() supported by ELE get random command on imx93 & imx91.

Issues in the ELE FW have been found when both, secure and
non-secure worlds

drivers: ele: rng: get random number from ELE

TEE_GenerateRandom() supported by ELE get random command on imx93 & imx91.

Issues in the ELE FW have been found when both, secure and
non-secure worlds are communicating with ELE.

To prevent any issue, rely on RNG software in OPTEE. The compilation of
hw_get_random_bytes() is conditioned by CFG_WITH_SOFTWARE_PRNG.
Set CFG_WITH_SOFTWARE_PRNG=y by default.

With CFG_WITH_SOFTWARE_PRNG enabled in OP-TEE, ELE will not be used
in OP-TEE at runtime and Linux can access the ELE without conflicts.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: enable TRUST MU in OP-TEE for i.MX93-EVK/i.MX91-EVK

There is TRUST MU available on i.MX91 and i.MX93 platforms.

TRUST MU can be used to access some HW features of Edgelock Enclave whi

drivers: ele: enable TRUST MU in OP-TEE for i.MX93-EVK/i.MX91-EVK

There is TRUST MU available on i.MX91 and i.MX93 platforms.

TRUST MU can be used to access some HW features of Edgelock Enclave which
Normal MU cannot, but for now it is configured to be used to communicate
with ELE FW.

So Kernel will use Normal MU and OP-TEE will use TRUST MU.

There is special setup needed to write to Trust MU.
* First for TRUST-MU we must write a valid command to TR0 before we can
write any of the remaining registers, and TR15 is reserved for special
USM command.
* The CMD field for TR0 is bits 31:26 and must be greater than
the value of the watermark set in SCM_CR2[31:22]. Typically
if you just set the MSB (bit 31) its enough.
* SIZE must be programmed in bits 19:16 of TR0, we cannot write
TRn past the specified size in this bit field

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: add SAB init command

There has been addition of SAB init command for initializing
the Edgeleock enclave services.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens

drivers: ele: add SAB init command

There has been addition of SAB init command for initializing
the Edgeleock enclave services.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: update session open command parameters

Update session open command parameters to be compatible with
ELE FW API doc

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jen

drivers: ele: update session open command parameters

Update session open command parameters to be compatible with
ELE FW API doc

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: allocate data in heap for HUK derivation

Use the heap and the ELE memory allocator instead of using the stack.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahi

drivers: ele: allocate data in heap for HUK derivation

Use the heap and the ELE memory allocator instead of using the stack.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: use the baseline API to retrieve the UID

Use the baseline API instead of the HSM to retrieve the UID. These two
API calls are duplicates and the HSM call is soon deprecated.

Signed-of

drivers: ele: use the baseline API to retrieve the UID

Use the baseline API instead of the HSM to retrieve the UID. These two
API calls are duplicates and the HSM call is soon deprecated.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: disable ASLR for imx8ulp

On imx8ulp, the RNG code from ELE is not available at resume. Disable
the ASLR feature and make it available for imx93 only.

Signed-off-by: Clement Faure <cle

drivers: ele: disable ASLR for imx8ulp

On imx8ulp, the RNG code from ELE is not available at resume. Disable
the ASLR feature and make it available for imx93 only.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: add memory management functions

Add memory management function

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Et

drivers: ele: add memory management functions

Add memory management function

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: getting common macros and functions in header file

Taking out macros and functions from c file and put them in
header file for being used by the other files of crypto driver.

Signed-o

drivers: ele: getting common macros and functions in header file

Taking out macros and functions from c file and put them in
header file for being used by the other files of crypto driver.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: move ELE to a dedicated directory

Created a new folder in core/drivers/crypto named ele
and moved ele.c in that folder.
This is done for making the base for further crypto driver
based

drivers: ele: move ELE to a dedicated directory

Created a new folder in core/drivers/crypto named ele
and moved ele.c in that folder.
This is done for making the base for further crypto driver
based on ELE.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: add APLIC and IMSIC support for QEMU virt platform

- Add APLIC and IMSIC configurations for the QEMU virt platform.
- Override the interrupt controller initialization and interrupt

riscv: plat-virt: add APLIC and IMSIC support for QEMU virt platform

- Add APLIC and IMSIC configurations for the QEMU virt platform.
- Override the interrupt controller initialization and interrupt handler
functions when using APLIC or IMSIC.

Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add RISC-V APLIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the APLIC, which can serve as a new external interrupt controller to
replace the

drivers: add RISC-V APLIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the APLIC, which can serve as a new external interrupt controller to
replace the original Platform-Level Interrupt Controller (PLIC) or as a
device to convert wired interrupts into message-signaled interrupts
(MSIs) and forward them to the Incoming MSI Controller (IMSIC).

The APLIC driver supports both "direct delivery mode" and
"MSI delivery mode." Use the `CFG_RISCV_APLIC` flag to enable the
APLIC driver in "direct delivery mode," and use the
`CFG_RISCV_APLIC_MSI` flag to enable the APLIC driver in "MSI
delivery mode" when selecting `CFG_RISCV_IMSIC`.

APLIC initialization can be done through the device tree.

For more details, see: https://github.com/riscv/riscv-aia

Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add RISC-V IMSIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records i

drivers: add RISC-V IMSIC interrupt driver

The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records incoming message-signaled interrupts (MSIs).

This commit enables the initialization of the IMSIC based on the device
tree and adds control and status registers (CSRs) for indirect access to
the IMSIC as well as for reading interrupt identities.

Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.

For more details, see: https://github.com/riscv/riscv-aia

Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: Remove unused call_initcalls()

Remove call_initcalls() since there is no architecture calls it.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wi

core: kernel: Remove unused call_initcalls()

Remove call_initcalls() since there is no architecture calls it.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: arm: Remove dummy call_initcalls()

Remove call_initcalls() since we will remove prototype of this function.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jen

core: arm: Remove dummy call_initcalls()

Remove call_initcalls() since we will remove prototype of this function.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Call call_driver_initcalls() late

Calls call_early_initcalls() and call_service_initcalls() directly
instead of call_initcalls() from init_tee_runtime().

This commit is to synchronize

core: riscv: Call call_driver_initcalls() late

Calls call_early_initcalls() and call_service_initcalls() directly
instead of call_initcalls() from init_tee_runtime().

This commit is to synchronize the initcalls with ARM architecture,
introduced in 27ed6973 (core: arm: call call_driver_initcalls() late).

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Introduce boot_init_primary_final()

Introduce boot_init_primary_final() and move the call to
call_finalcalls() into that function.

This commit is to synchronize the boot stages with AR

core: riscv: Introduce boot_init_primary_final()

Introduce boot_init_primary_final() and move the call to
call_finalcalls() into that function.

This commit is to synchronize the boot stages with ARM architecture,
introduced in d0c23684 (core: arm: introduce boot_init_primary_final()).

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: do not acknowledge end of interrupt for special GIC interrupt IDs

According to the ARM documentation for GICV2/3/4, there is no need to
write to the end of interrupt register for some special

core: do not acknowledge end of interrupt for special GIC interrupt IDs

According to the ARM documentation for GICV2/3/4, there is no need to
write to the end of interrupt register for some special IDs. Apply this
recommendation to avoid writing to IO memory in this time sensitive
sequence.

Also distinguish unhandled interrupts with an error log.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix debug event fault value for ARM32 with LPAE

According to ARM documentation, the debug event fault value is indeed
0b100010, which is 0x22, not 0x12. Fix this value in
core_mmu_get_fault_ty

core: fix debug event fault value for ARM32 with LPAE

According to ARM documentation, the debug event fault value is indeed
0b100010, which is 0x22, not 0x12. Fix this value in
core_mmu_get_fault_type().

Fixes: 0eff3e9bf016 ("arm32: Adds LPAE support")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal

plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal Access was caught and print the SERC register and panic()
if that is the case.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add platform-specific abort handler

Platforms may have specific code to handle an abort when fault type
is FAULT_TYPE_IGNORE. Add plat_abort_handler() that can be overridden
at platform level

core: add platform-specific abort handler

Platforms may have specific code to handle an abort when fault type
is FAULT_TYPE_IGNORE. Add plat_abort_handler() that can be overridden
at platform level.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: imx: rngb: early initialization

The RNGB module must be ready during init_tee_runtime to provide a
random stack canary value during bootup.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundr

drivers: imx: rngb: early initialization

The RNGB module must be ready during init_tee_runtime to provide a
random stack canary value during bootup.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: interrupt: fix interrupt_set_{affinity|wake}() description

Fix inline description of itr_num argument for interrupt_set_affinity()
and interrupt_set_wake().

Fixes: b2d6db21ec5e ("core: interr

core: interrupt: fix interrupt_set_{affinity|wake}() description

Fix inline description of itr_num argument for interrupt_set_affinity()
and interrupt_set_wake().

Fixes: b2d6db21ec5e ("core: interrupt: helper function for raise_pi, raise_sgi, set_affinity")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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