core: lpae: fix 'idx' boundary check in core_mmu_entry_to_finer_grained()

Table entry index, 'idx', was checked for [0, tbl_info->num_entries],
while it should be [0, tbl_info->num_entries[.

Signed

core: lpae: fix 'idx' boundary check in core_mmu_entry_to_finer_grained()

Table entry index, 'idx', was checked for [0, tbl_info->num_entries],
while it should be [0, tbl_info->num_entries[.

Signed-off-by: Izik Dubnov <izik@amazon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Fix r7 clobbering in reset_primary

During reset_primary, r7 is used to keep the content of r2 register
given at OP-TEE start. However, r7 is clobbered during boot. This lead
to r2 being incorr

core: Fix r7 clobbering in reset_primary

During reset_primary, r7 is used to keep the content of r2 register
given at OP-TEE start. However, r7 is clobbered during boot. This lead
to r2 being incorrectly restored when returning to normal world. Use
r9 instead of r7 where needed to avoid clobbering it.

Fixes: 59ac3801b756 ("core: split boot_init_primary")
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm64: remove duplicate definition of THREAD_CTX_SIZE

Following commit 1b302ac09816 ("core: enable FF-A with SPM Core at
S-EL1"), the THREAD_CTX_SIZE macro is now defined twice on arm64
(in $(

core: arm64: remove duplicate definition of THREAD_CTX_SIZE

Following commit 1b302ac09816 ("core: enable FF-A with SPM Core at
S-EL1"), the THREAD_CTX_SIZE macro is now defined twice on arm64
(in $(out-dir)/core/include/generated/asm-defines.h).

Kill the definition in the #ifdef ARM64 block and keep the common
one.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because

core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because physical
address can be mapped in the same time in different virtual
regions with different length. So the first found region
which contains the requested physical address possibly
doesn`t have enough mapped data. This is fixed by adding
the length parameter to phys_to_virt() function. Length
parameter can be set to 1 if caller knows that requested
(pa + len) doesn`t cross mapping granule boundary.

core_mmu_get_va() and io_pa_or_va() functions now are
take length parameter too as they based on phys_to_virt()
in case of MMU enabled.

Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)

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core: arm: implement cpu_idle()

Implement cpu_idle() on arm and arm64, based on wfi(). With this patch,
a panicked CPU no longer burns cycles needlessly.

Signed-off-by: Jerome Forissier <jerome@for

core: arm: implement cpu_idle()

Implement cpu_idle() on arm and arm64, based on wfi(). With this patch,
a panicked CPU no longer burns cycles needlessly.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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arm64: add wfi()

arm32.h has a wfi() function but not arm64.h. Add it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Et

arm64: add wfi()

arm32.h has a wfi() function but not arm64.h. Add it.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: panic: introduce cpu_idle() function

Adds a cpu_idle() weak function to panic.h/panic.c, which can later be
implemented in arch-specific code. The purpose is to avoid a busy loop
(which is the

core: panic: introduce cpu_idle() function

Adds a cpu_idle() weak function to panic.h/panic.c, which can later be
implemented in arch-specific code. The purpose is to avoid a busy loop
(which is the default implementation) when __do_panic() is done but
cannot return.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: rename TA_VASPACE to TS_VASPACE

The TA_VASPACE memory will be used by both TAs and SPs.
Rename it to TS_VASPACE so it is clearer that it can be used by both.

Signed-off-by: Jelle Sels <jelle.

core: rename TA_VASPACE to TS_VASPACE

The TA_VASPACE memory will be used by both TAs and SPs.
Rename it to TS_VASPACE so it is clearer that it can be used by both.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Squashed commit upgrading to mbedtls-2.27.0

Squash merging branch import/mbedtls-2.27.0

335b95f50f90 ("core: libmbedtls: add ctr_drbg.c to core sources")
9ad9df8b36e4 ("core: libtomcrypt: libmbed

Squashed commit upgrading to mbedtls-2.27.0

Squash merging branch import/mbedtls-2.27.0

335b95f50f90 ("core: libmbedtls: add ctr_drbg.c to core sources")
9ad9df8b36e4 ("core: libtomcrypt: libmbedtls: mbedtls_mpi_montred() now returns void")
ade0994c57b3 ("libmbedtls: add SM2 curve")
3041cf9726e2 ("libmbedtls: mbedtls_mpi_exp_mod(): optimize mempool usage")
a2e7a4cd262d ("libmbedtls: mbedtls_mpi_exp_mod(): reduce stack usage")
87efbd27f8e0 ("libmbedtls: mbedtls_mpi_exp_mod() initialize W")
e7c59b9b1d5f ("libmbedtls: fix no CRT issue")
d76bd278d9e2 ("libmbedtls: add interfaces in mbedtls for context memory operation")
e5b6c167f809 ("libmedtls: mpi_miller_rabin: increase count limit")
b81d896a903d ("libmbedtls: add mbedtls_mpi_init_mempool()")
3fbd8660c09d ("libmbedtls: make mbedtls_mpi_mont*() available")
2cc759c67e37 ("mbedtls: configure mbedtls to reach for config")
48bf81758c6e ("mbedtls: remove default include/mbedtls/config.h")
3602df84d7b3 ("Import mbedtls-2.27.0")

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-totalcompute: Introduce TC1 platform

The different platform parameters, such as GIC, UART, etc
are similar between TC0 and TC1. tc0_spmc_pm.c is also renamed to
tc_spmc_pm.c as its common to bo

plat-totalcompute: Introduce TC1 platform

The different platform parameters, such as GIC, UART, etc
are similar between TC0 and TC1. tc0_spmc_pm.c is also renamed to
tc_spmc_pm.c as its common to both platforms.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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mm: fix mobj split by adding core_mmu_find_mapping_exclusive() helper

Fixes: ff01e2452169 ("mm: split mobj_tee_ram onto rw/rx parts")

This fixes mobj splitting onto RX/RW parts. Now split can be do

mm: fix mobj split by adding core_mmu_find_mapping_exclusive() helper

Fixes: ff01e2452169 ("mm: split mobj_tee_ram onto rw/rx parts")

This fixes mobj splitting onto RX/RW parts. Now split can be done
incorrectly if RX and RW regions doesn`t mapped contiguosly. Added helper
core_mmu_find_mapping_exclusive() allows to find unique mapping for
specified type and length independently of their order, so then RX/RW
regions for mobjects should be determined correctly.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>

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core: add new init and nexus memory types

Adds the new memory types MEM_AREA_INIT_RAM_RO, MEM_AREA_INIT_RAM_RX and
MEM_AREA_NEX_RAM_RO to make sure that the memory types
MEM_AREA_TEE_RAM_RX, MEM_ARE

core: add new init and nexus memory types

Adds the new memory types MEM_AREA_INIT_RAM_RO, MEM_AREA_INIT_RAM_RX and
MEM_AREA_NEX_RAM_RO to make sure that the memory types
MEM_AREA_TEE_RAM_RX, MEM_AREA_TEE_RAM_RO and MEM_AREA_TEE_RAM_RW are
used only once. This is needed when to uniquely identify those memory
areas in mobj_init() and mobj_phys_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Anton Rybakov <a.rybakov@omp.ru>

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plat-marvell: Add HUK support for OcteonTX2 Platforms

Added support for fetching Hardware Unique Key(HUK)
from the OcteonTX2 platform.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Reviewed

plat-marvell: Add HUK support for OcteonTX2 Platforms

Added support for fetching Hardware Unique Key(HUK)
from the OcteonTX2 platform.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Reviewed-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Reviewed-by: Bharat Bhushan <bbhushan2@marvell.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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plat-totalcompute: Add support for S-EL2 SPMC

This patch adds CFG_CORE_SEL2_SPMC support. Defines CFG_TZDRAM_START
address with memory region reserved for SPMC. Adds secondary cpu boot
request handl

plat-totalcompute: Add support for S-EL2 SPMC

This patch adds CFG_CORE_SEL2_SPMC support. Defines CFG_TZDRAM_START
address with memory region reserved for SPMC. Adds secondary cpu boot
request handler. Disables configuring GIC if SEL2 SPMC is enabled.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-totalcompute: Add OP-TEE SP manifest file

Add Secure Partition manifest file. This file is used when OP-TEE is build
with CFG_CORE_SEL2_SPMC support when creating the SP binary image.

Signed-o

plat-totalcompute: Add OP-TEE SP manifest file

Add Secure Partition manifest file. This file is used when OP-TEE is build
with CFG_CORE_SEL2_SPMC support when creating the SP binary image.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-totalcompute: define tzdram start address for S-EL1 SPMC config

Define TZDRAM_START for CFG_CORE_SEL1_SPMC config

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-

plat-totalcompute: define tzdram start address for S-EL1 SPMC config

Define TZDRAM_START for CFG_CORE_SEL1_SPMC config

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: Total Compute platform support

Initial support for Total Compute platform[1]
- defines tc0 platform configuration
- enables CFG_ARM64_core by default
- defines TZCDRAM_BASE

L

core: arm: Total Compute platform support

Initial support for Total Compute platform[1]
- defines tc0 platform configuration
- enables CFG_ARM64_core by default
- defines TZCDRAM_BASE

Link: [1] https://community.arm.com/developer/tools-software/oss-platforms/w/docs/606/total-compute

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: remove redundant mobj_put() in vm_map_pad()

When mobj_get_cattr() fails vm_map_pad() doesn't need to
call mobj_put() which is expected to balance mobj_get() called
only after mobj_get_catt

core: mm: remove redundant mobj_put() in vm_map_pad()

When mobj_get_cattr() fails vm_map_pad() doesn't need to
call mobj_put() which is expected to balance mobj_get() called
only after mobj_get_cattr() succeeds. The issue was introduced
in release 3.8.0 with struct mobj reference counting.

Signed-off-by: Gavin Liu <Gavin.Liu@mediatek.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: optimize speed of AES CBC MAC

The current AES CBC MAC implementation invokes the AES CBC algorithm via
crypto_cipher_update() for each 16-byte block of the input data. This
can be inefficien

crypto: optimize speed of AES CBC MAC

The current AES CBC MAC implementation invokes the AES CBC algorithm via
crypto_cipher_update() for each 16-byte block of the input data. This
can be inefficient especially with hardware accelerated implementations
which may have a significant overhead (I am thinking of proprietary
implementations of MBed TLS for example).

This commit introduces a new config option:
CFG_CRYPTO_CBC_MAC_BUNDLE_BLOCKS (default 64) which allows to bundle
several 16-byte blocks of input data when calling the AES CBC function.
Therefore with the default value, data are processed 1 KB at a time
(assuming the caller provides enough data of course). There is a small
memory overhead (malloc) of the same size at most.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-ls: ls1012a: Fix GIC offset

The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Si

core: plat-ls: ls1012a: Fix GIC offset

The GIC offset for LS1012A is different than the one for
LS1043A and LS1046A.
Fixing for LS1012A

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: increase CFG_DTB_MAX_SIZE to 256KiB

On stm32mp1 platform the external DTB that may be passed by former
boot stage may overflow the default 64kB of CFG_DTB_MAX_SIZE hence
increase it t

plat-stm32mp1: increase CFG_DTB_MAX_SIZE to 256KiB

On stm32mp1 platform the external DTB that may be passed by former
boot stage may overflow the default 64kB of CFG_DTB_MAX_SIZE hence
increase it to 256kB which is reasonable for that platform.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: fix shres2str_state() prototype

Reported by GCC-10.2 when build plat-stm32mp1 with CFG_TEE_CORE_LOG_LEVEL=3.

core/arch/arm/plat-stm32mp1/shared_resources.c: In function ‘register_per

plat-stm32mp1: fix shres2str_state() prototype

Reported by GCC-10.2 when build plat-stm32mp1 with CFG_TEE_CORE_LOG_LEVEL=3.

core/arch/arm/plat-stm32mp1/shared_resources.c: In function ‘register_periph’:
core/arch/arm/plat-stm32mp1/shared_resources.c:212:24: warning: implicit conversion from ‘enum shres_state’ to ‘enum stm32mp_shres’ [-Wenum-conversion]
212 | shres2str_state(state));
| ^~~~~

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: increase CFG_DTB_MAX_SIZE to 128KiB

On imx6q, imx6qp, imx6dl and imx7d platforms, we get the following error
at boot:

E/TC:0 0 init_external_dt:1099 Invalid Device Tree at 0x18000000: er

core: imx: increase CFG_DTB_MAX_SIZE to 128KiB

On imx6q, imx6qp, imx6dl and imx7d platforms, we get the following error
at boot:

E/TC:0 0 init_external_dt:1099 Invalid Device Tree at 0x18000000: error -3

i.MX device trees compiled with _symbols_ nodes makes DTB bigger than 56KiB.
Increase the CFG_DTB_MAX_SIZE from 56KiB to 128KiB for all imx6 and imx7
platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-marvell: Add support for OcteonTX2 CNF95xx and CN98xx

Add support for OcteonTX2 CNF95xx and CN98xx platforms
from Marvell.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerom

plat-marvell: Add support for OcteonTX2 CNF95xx and CN98xx

Add support for OcteonTX2 CNF95xx and CN98xx platforms
from Marvell.

Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-marvell: Add support for OcteonTX2 CN96xx SoC

Add support for OcteonTX2 CN96xx SoC from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-o

plat-marvell: Add support for OcteonTX2 CN96xx SoC

Add support for OcteonTX2 CN96xx SoC from Marvell.

Only tested 64-bit mode with default configurations:

1. Build command
make PLATFORM=marvell-otx2t96
2. Passed xtest

Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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