core: dynamic allocation of threads and their stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of threads and their
stacks.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Revie

core: dynamic allocation of threads and their stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of threads and their
stacks.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add thread_count to thread_init_threads()

Add a thread_count parameter to thread_init_threads(). This must currently
always be equal to CFG_NUM_THREADS, but may become a dynamic configuration

core: add thread_count to thread_init_threads()

Add a thread_count parameter to thread_init_threads(). This must currently
always be equal to CFG_NUM_THREADS, but may become a dynamic configuration
parameter with CFG_DYN_CONFIG=y in later patches.

The array threads[] is changed into a pointer to allow dynamic
allocation in later patches. The assembly code is updated accordingly to
handle a pointer instead of an array.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Tested-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: shared xlat tables for NEX_DYN_VASPACE

Mappings in MEM_AREA_NEX_DYN_VASPACE belong to the nexus and are must to
be the same for all partitions. Since these mappings must be updated in
the

core: mm: shared xlat tables for NEX_DYN_VASPACE

Mappings in MEM_AREA_NEX_DYN_VASPACE belong to the nexus and are must to
be the same for all partitions. Since these mappings must be updated in
the partitions after the MMU has been enabled. Partitions share
translation tables for this mappings, so we only need to update in one
translation table when adding or removing mappings.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: dynamic allocation of thread_core_local and its stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of thread_core_local
and the two stacks, tmp_stack and abt_stack, recorded in it.

Si

core: dynamic allocation of thread_core_local and its stacks

With CFG_DYN_CONFIG enabled, use dynamic allocation of thread_core_local
and the two stacks, tmp_stack and abt_stack, recorded in it.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: add core_count to thread_init_thread_core_local()

Add a core_count parameter to thread_init_thread_core_local() to enable
dynamic configuration of the number of supported cores when configured

core: add core_count to thread_init_thread_core_local()

Add a core_count parameter to thread_init_thread_core_local() to enable
dynamic configuration of the number of supported cores when configured
with CFG_DYN_STACK_CONFIG=y, or it must be equal to
CFG_TEE_CORE_NB_CORE. This is needed in later patches where the number
of cores is configured dynamically.

The array thread_core_local[] is changed into a pointer to allow dynamic
allocation in later patches. The assembly code is updated accordingly to
handle a pointer instead of an array.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: virt: share TA memory with core

With CFG_NS_VIRTUALIZATION=y it is assumed that all physical OP-TEE
memory, core and TA, is equally secure. When a guest is created,
register the allocated

core: arm: virt: share TA memory with core

With CFG_NS_VIRTUALIZATION=y it is assumed that all physical OP-TEE
memory, core and TA, is equally secure. When a guest is created,
register the allocated physical TA memory in the physical core memory
pool instead of physical TA memory pool. This lets the partition to
allocate from a single pool reserved for the partition instead of trying
to guess how much core memory it might need.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mm: fix core_mmu_xlat_table_alloc() for nexus

core_mmu_xlat_table_alloc() allocates new translation tables from
boot_mem until during early boot and after the MMU has been enabled with
ne

core: arm: mm: fix core_mmu_xlat_table_alloc() for nexus

core_mmu_xlat_table_alloc() allocates new translation tables from
boot_mem until during early boot and after the MMU has been enabled with
nex_phys_mem_core_alloc() or phys_mem_core_alloc(). However, the logic
selecting which function to call doesn't take the default partition into
account. The default partition has only a nexus physical memory pool so
nex_phys_mem_core_alloc() must be called if that partition is active. So
fix the problem with an extra check for default_partition.

Fixes: a28e4a0fe48d ("core: arm: mm: dynamic allocation of LPAE translation tables")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-ti: replace stack_tmp_stride usage

The function resume_springboard() needs to restore the tmp_stack before
the rest of the resume process can be started. Since the commit
05994c760d5d ("core: t

plat-ti: replace stack_tmp_stride usage

The function resume_springboard() needs to restore the tmp_stack before
the rest of the resume process can be started. Since the commit
05994c760d5d ("core: thread: get stacks from recorded end-va") we can
now read the address of the tmp_stack from thread_core_local. So update
resume_springboard() as needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: pta: update virt_to_phys() self tests

Update pointer in the virt_to_phys() test for a TEE_RAM to make sure
it's pointer in the TEE_RAM area since stack pointers may be mapped
differently with

core: pta: update virt_to_phys() self tests

Update pointer in the virt_to_phys() test for a TEE_RAM to make sure
it's pointer in the TEE_RAM area since stack pointers may be mapped
differently with CFG_DYN_CONFIG=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: increase tmp stack size for debug

Increase STACK_TMP_SIZE when CFG_CORE_DEBUG_CHECK_STACKS=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jero

core: arm64: increase tmp stack size for debug

Increase STACK_TMP_SIZE when CFG_CORE_DEBUG_CHECK_STACKS=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: ffa: add test logical SP

Add a test LSP with UUID 54b5440e-a3d2-48d1-872a-7b6cbfc34855 to see
that LSPs can be found and reached from the normal world.

Signed-off-by: Jens Wiklander <jen

core: arm: ffa: add test logical SP

Add a test LSP with UUID 54b5440e-a3d2-48d1-872a-7b6cbfc34855 to see
that LSPs can be found and reached from the normal world.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Akshay Belsare <akshay.belsare@amd.com>

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core: arm: ffa: add framework for Logical SPs

Add a framework to register Logical Secure Partitions in parallel with
OP-TEE at S-EL1. This is akin to Pseudo TAs, it provides an ABI but it's
part of

core: arm: ffa: add framework for Logical SPs

Add a framework to register Logical Secure Partitions in parallel with
OP-TEE at S-EL1. This is akin to Pseudo TAs, it provides an ABI but it's
part of the OP-TEE binary. A critical difference is that it's only
available for FF-A and can only use the non-threaded environment, that
is, no mutexes or RPC.

The logical OP-TEE core partition is registered in the framework. The
SPMC is also registered in the framework, but with a nil UUID so it's
not returned by FFA_PARTITION_INFO_GET.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Akshay Belsare <akshay.belsare@amd.com>

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core: ffa: only accept FFA_RUN for S-EL0 SPs

OP-TEE core is never preemted with FFA_INTERRUPT so it must never be
resumed with FFA_RUN. However, S-EL0 SPs are preempted with
FFA_INTERRUPT so those a

core: ffa: only accept FFA_RUN for S-EL0 SPs

OP-TEE core is never preemted with FFA_INTERRUPT so it must never be
resumed with FFA_RUN. However, S-EL0 SPs are preempted with
FFA_INTERRUPT so those are still resumed using FFA_RUN.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Akshay Belsare <akshay.belsare@amd.com>

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core: ffa: sp_partition_info_get() takes uuid_words[]

Replace the TEE_UUID *ffa_uuid parameter with uint32_t ffa_uuid_words[4]
to simplify how sp_partition_info_get() is called.

Signed-off-by: Jens

core: ffa: sp_partition_info_get() takes uuid_words[]

Replace the TEE_UUID *ffa_uuid parameter with uint32_t ffa_uuid_words[4]
to simplify how sp_partition_info_get() is called.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Akshay Belsare <akshay.belsare@amd.com>

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core: ffa: add spmc_is_reserved_id()

Add spmc_is_reserved_id() and replace direct checks against spmd_id and
spmc_id. spmd_id and spmc_id are changed to static variables since they
don't need to be

core: ffa: add spmc_is_reserved_id()

Add spmc_is_reserved_id() and replace direct checks against spmd_id and
spmc_id. spmd_id and spmc_id are changed to static variables since they
don't need to be exported any longer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Akshay Belsare <akshay.belsare@amd.com>

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core: pta: add self tests for transfer list

Add self tests for transfer list.
Adapt CFG_TRANSFER_LIST with its dependencies and add
CFG_TRANSFER_LIST_TEST.

Signed-off-by: Raymond Mao <raymond.mao@l

core: pta: add self tests for transfer list

Add self tests for transfer list.
Adapt CFG_TRANSFER_LIST with its dependencies and add
CFG_TRANSFER_LIST_TEST.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: remove the last appended void transfer entry

transfer_list_set_data_size() appends a void entry for the following
entries to meet the alignment requirement even when it is the last
one

core: kernel: remove the last appended void transfer entry

transfer_list_set_data_size() appends a void entry for the following
entries to meet the alignment requirement even when it is the last
one, thus add a check before appending.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: kernel: fix bug in transfer_list_add()

Fix the missing cast on the target address when doing memmove.
Get the address of entry data via transfer_list_entry_data()
instead of adding offset.

Fi

core: kernel: fix bug in transfer_list_add()

Fix the missing cast on the target address when doing memmove.
Get the address of entry data via transfer_list_entry_data()
instead of adding offset.

Fixes: a12225022bd5 ("core: add transfer list API")
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: reserve physical nexus memory for manifest

In reinit_manifest_dt() when reserving physical memory for the manifest,
allocate from physical nexus memory instead to support ns-virtualizatio

core: ffa: reserve physical nexus memory for manifest

In reinit_manifest_dt() when reserving physical memory for the manifest,
allocate from physical nexus memory instead to support ns-virtualization.

Fixes: 414123ae8ca5 ("core: ffa: reserve physical memory for manifest")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: applies FF-A v1.2 features on StandaloneMm

edk2's StandaloneMm will be applied with FF-A v1.2.
while applying, StandaloneMm doesn't create anymore PHIT hob by itself
but it should be passed fr

core: applies FF-A v1.2 features on StandaloneMm

edk2's StandaloneMm will be applied with FF-A v1.2.
while applying, StandaloneMm doesn't create anymore PHIT hob by itself
but it should be passed from other software stack.

To make StandaloneMm runs properly, create Hob information and
deliver it using FF-A Boot protocol according to FF-A specification [1].

Also, apply FF-A management protocol to change it [2] to
get/set memory permission instead of using DIRECT_REQ_MSG.

Also, implements some FF-A ABIs to communication StandaloneMm properly.

Link: https://developer.arm.com/documentation/den0077/latest [1]
Link: https://developer.arm.com/documentation/den0140/latest [2]

Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>

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core: introduce libefi for StandaloneMm

According to Platform Initialization (PI) Specification [1] and
Discussion on edk2 mailing list [2],
StandaloneMm shouldn't create Hob but it should be passed

core: introduce libefi for StandaloneMm

According to Platform Initialization (PI) Specification [1] and
Discussion on edk2 mailing list [2],
StandaloneMm shouldn't create Hob but it should be passed from TF-A.
That's why StandaloneMm in Arm wouldn't produce Hob by itself [3] but
other software stack should pass boot information via PHIT Hob.

This patch introduces libefi including create Hob to deliver
boot information to StandaloneMm and defines related data structures.

Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1]
Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2]
Link: https://github.com/tianocore/edk2/pull/6116 [3]

Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>

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riscv: mm: Fix core_mmu_entry_is_branch()

We must also check V bit to determine non-leaf PTE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.co

riscv: mm: Fix core_mmu_entry_is_branch()

We must also check V bit to determine non-leaf PTE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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riscv: mm: support Sv48 and Sv57 address translation for core and TA

Add the macros for Sv57 address translation mode. Add CFG_RISCV_MMU_MODE
into riscv.mk and set it as 39 by default to enable Sv39

riscv: mm: support Sv48 and Sv57 address translation for core and TA

Add the macros for Sv57 address translation mode. Add CFG_RISCV_MMU_MODE
into riscv.mk and set it as 39 by default to enable Sv39 virtual address
translation scheme.

Currently, TA virtual memory occupies 1GB space, and TAs page table
should be an entry inside a level 2 (VPN[2]) page table, which is
decided by user_va_idx variable. For Sv39 translation scheme, it starts
from VPN[2], so nothing to do. For Sv48 translation scheme, we need to
allocate entry 0 of level 3 (VPN[3]) page table, and let it point to the
level 2 page table used by TA. For Sv57 translation scheme, we need to
further allocate entry 0 of level 4 (VPN[4]) page table, and let it
point to the level 3 page table.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: Explicitly set user VA range inside L2(RV64) and L1(RV32) VPN

Add macros for level and bit shift of virtual page number (VPN) encoded
in RISC-V virtual address. Explicitly set range of us

riscv: mm: Explicitly set user VA range inside L2(RV64) and L1(RV32) VPN

Add macros for level and bit shift of virtual page number (VPN) encoded
in RISC-V virtual address. Explicitly set range of user virtual address
inside level 2 VPN by giving CORE_MMU_VPN2_SHIFT since the
CORE_MMU_BASE_TABLE_SHIFT is not always based on level 2 VPN if the MMU
scheme is not Sv39.

For RV32, there is only two-level VPN. The user VA range would be inside
level 1 VPN.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: clean up macro definitions

Rename RISCV_SATP_ASID_SIZE to RISCV_SATP_ASID_WIDTH since it is used to
represent width of bits. Also remove redundant RISCV_MMU_ASID_WIDTH
since we already ha

riscv: mm: clean up macro definitions

Rename RISCV_SATP_ASID_SIZE to RISCV_SATP_ASID_WIDTH since it is used to
represent width of bits. Also remove redundant RISCV_MMU_ASID_WIDTH
since we already have RISCV_SATP_ASID_WIDTH. Fix a minor compiler
warning due to inconsistent data types on variable comparison.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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